diff options
| -rw-r--r-- | configs/common/Caches.py | 3 | ||||
| -rw-r--r-- | configs/common/O3_ARM_v7a.py | 2 | ||||
| -rw-r--r-- | src/cpu/minor/cpu.hh | 3 | ||||
| -rw-r--r-- | src/cpu/minor/lsq.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.hh | 1 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.hh | 1 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 5 | ||||
| -rw-r--r-- | src/mem/cache/Cache.py | 2 | ||||
| -rw-r--r-- | src/mem/cache/base.cc | 5 | ||||
| -rw-r--r-- | src/mem/cache/base.hh | 2 |
10 files changed, 10 insertions, 18 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py index c65910e23..af1dee626 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -76,7 +76,6 @@ class IOCache(Cache): mshrs = 20 size = '1kB' tgts_per_mshr = 12 - forward_snoops = False class PageTableWalkerCache(Cache): assoc = 2 @@ -85,7 +84,7 @@ class PageTableWalkerCache(Cache): mshrs = 10 size = '1kB' tgts_per_mshr = 12 - forward_snoops = False + # the x86 table walker actually writes to the table-walker cache if buildEnv['TARGET_ISA'] == 'x86': is_read_only = False diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py index 103158290..a38273c10 100644 --- a/configs/common/O3_ARM_v7a.py +++ b/configs/common/O3_ARM_v7a.py @@ -149,7 +149,6 @@ class O3_ARM_v7a_ICache(Cache): tgts_per_mshr = 8 size = '32kB' assoc = 2 - forward_snoops = False is_read_only = True # Writeback clean lines as well writeback_clean = True @@ -176,7 +175,6 @@ class O3_ARM_v7aWalkCache(Cache): size = '1kB' assoc = 8 write_buffers = 16 - forward_snoops = False is_read_only = True # Writeback clean lines as well writeback_clean = True diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 82dac6aa9..dad015e89 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -107,9 +107,6 @@ class MinorCPU : public BaseCPU : MasterPort(name_, &cpu_), cpu(cpu_) { } - protected: - /** Snooping a coherence request, do nothing. */ - virtual void recvTimingSnoopReq(PacketPtr pkt) { } }; protected: diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh index 8a7d78216..33d7c506b 100644 --- a/src/cpu/minor/lsq.hh +++ b/src/cpu/minor/lsq.hh @@ -103,8 +103,12 @@ class LSQ : public Named void recvReqRetry() { lsq.recvReqRetry(); } + bool isSnooping() const override { return true; } + void recvTimingSnoopReq(PacketPtr pkt) { return lsq.recvTimingSnoopReq(pkt); } + + void recvFunctionalSnoop(PacketPtr pkt) { } }; DcachePort dcachePort; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index eed5811cb..2065202f7 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -147,7 +147,6 @@ class FullO3CPU : public BaseO3CPU /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ virtual bool recvTimingResp(PacketPtr pkt); - virtual void recvTimingSnoopReq(PacketPtr pkt) { } /** Handles doing a retry of a failed fetch. */ virtual void recvReqRetry(); diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index c643bfe58..098ecd759 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -127,7 +127,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU { } protected: - virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } bool recvTimingResp(PacketPtr pkt) { diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index da8320793..035f05158 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -164,11 +164,6 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: - /** - * Snooping a coherence request, do nothing. - */ - virtual void recvTimingSnoopReq(PacketPtr pkt) {} - TimingSimpleCPU* cpu; struct TickEvent : public Event diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 531337f19..263b2fea8 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -64,8 +64,6 @@ class BaseCache(MemObject): tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") write_buffers = Param.Unsigned(8, "Number of write buffers") - forward_snoops = Param.Bool(True, - "Forward snoops from mem side to cpu side") is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 41b6f38aa..a3ceaafa3 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -77,7 +77,7 @@ BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) fillLatency(p->response_latency), responseLatency(p->response_latency), numTarget(p->tgts_per_mshr), - forwardSnoops(p->forward_snoops), + forwardSnoops(true), isReadOnly(p->is_read_only), blocked(0), order(0), @@ -86,6 +86,8 @@ BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), system(p->system) { + // forward snoops is overridden in init() once we can query + // whether the connected master is actually snooping or not } void @@ -131,6 +133,7 @@ BaseCache::init() if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) fatal("Cache ports on %s are not connected\n", name()); cpuSidePort->sendRangeChange(); + forwardSnoops = cpuSidePort->isSnooping(); } BaseMasterPort & diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 8cd932f01..1f1f1469f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -302,7 +302,7 @@ class BaseCache : public MemObject const int numTarget; /** Do we forward snoops from mem side port through to cpu side port? */ - const bool forwardSnoops; + bool forwardSnoops; /** * Is this cache read only, for example the instruction cache, or |