diff options
62 files changed, 35844 insertions, 35764 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 30313ea26..40315f031 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901720 # Number of seconds simulated -sim_ticks 1901719660500 # Number of ticks simulated -final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.898811 # Number of seconds simulated +sim_ticks 1898811181000 # Number of ticks simulated +final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97307 # Simulator instruction rate (inst/s) -host_op_rate 97307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3261646555 # Simulator tick rate (ticks/s) -host_mem_usage 383552 # Number of bytes of host memory used -host_seconds 583.06 # Real time elapsed on the host -sim_insts 56735321 # Number of instructions simulated -sim_ops 56735321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory -system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory -system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449354 # Total number of read requests seen -system.physmem.writeReqs 120733 # Total number of write requests seen -system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28758656 # Total number of bytes read from memory -system.physmem.bytesWritten 7726912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis +host_inst_rate 163774 # Simulator instruction rate (inst/s) +host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5540525376 # Simulator tick rate (ticks/s) +host_mem_usage 339592 # Number of bytes of host memory used +host_seconds 342.71 # Real time elapsed on the host +sim_insts 56127436 # Number of instructions simulated +sim_ops 56127436 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory +system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory +system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450881 # Total number of read requests seen +system.physmem.writeReqs 122253 # Total number of write requests seen +system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28856384 # Total number of bytes read from memory +system.physmem.bytesWritten 7824192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry -system.physmem.totGap 1901668058000 # Total gap between requests +system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry +system.physmem.totGap 1898811160000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449354 # Categorize read packet sizes +system.physmem.readPktSize::6 450881 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121126 # categorize write packet sizes +system.physmem.writePktSize::6 124126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,33 +116,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # 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Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 8261632913 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 16092226663 # Sum of mem lat for all requests +system.physmem.totBusLat 2254075000 # Total cycles spent in databus access +system.physmem.totBankLat 5576518750 # Total cycles spent in bank access +system.physmem.avgQLat 18325.99 # Average queueing delay per request +system.physmem.avgBankLat 12369.86 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 35695.85 # Average memory access latency +system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # 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number of cycles access was blocked +system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +612,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372868 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits +system.cpu0.branchPred.lookups 10581841 # Number of BP lookups +system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8796431 # DTB read hits -system.cpu0.dtb.read_misses 31428 # DTB read misses -system.cpu0.dtb.read_acv 541 # DTB read access violations -system.cpu0.dtb.read_accesses 625134 # DTB read accesses -system.cpu0.dtb.write_hits 5759616 # DTB write hits -system.cpu0.dtb.write_misses 8293 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 208056 # DTB write accesses -system.cpu0.dtb.data_hits 14556047 # DTB hits -system.cpu0.dtb.data_misses 39721 # DTB misses -system.cpu0.dtb.data_acv 881 # DTB access violations -system.cpu0.dtb.data_accesses 833190 # DTB accesses -system.cpu0.itb.fetch_hits 984271 # ITB hits -system.cpu0.itb.fetch_misses 30098 # ITB misses -system.cpu0.itb.fetch_acv 957 # ITB acv -system.cpu0.itb.fetch_accesses 1014369 # ITB accesses +system.cpu0.dtb.read_hits 7560815 # DTB read hits +system.cpu0.dtb.read_misses 30461 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 623625 # DTB read accesses +system.cpu0.dtb.write_hits 5040625 # DTB write hits +system.cpu0.dtb.write_misses 7520 # DTB write misses +system.cpu0.dtb.write_acv 334 # DTB write access violations +system.cpu0.dtb.write_accesses 206551 # DTB write accesses +system.cpu0.dtb.data_hits 12601440 # DTB hits +system.cpu0.dtb.data_misses 37981 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 830176 # DTB accesses +system.cpu0.itb.fetch_hits 911527 # ITB hits +system.cpu0.itb.fetch_misses 30644 # ITB misses +system.cpu0.itb.fetch_acv 921 # ITB acv +system.cpu0.itb.fetch_accesses 942171 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +653,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101814962 # number of cpu cycles simulated +system.cpu0.numCycles 89753559 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued -system.cpu0.iq.rate 0.501619 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued +system.cpu0.iq.rate 0.488941 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3208712 # number of nop insts executed -system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8068479 # Number of branches executed -system.cpu0.iew.exec_stores 5781453 # Number of stores executed -system.cpu0.iew.exec_rate 0.497833 # Inst execution rate -system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25094352 # num instructions producing a value -system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value +system.cpu0.iew.exec_nop 2697587 # number of nop insts executed +system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6879787 # Number of branches executed +system.cpu0.iew.exec_stores 5059363 # Number of stores executed +system.cpu0.iew.exec_rate 0.485294 # Inst execution rate +system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21537449 # num instructions producing a value +system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50792559 # Number of instructions committed -system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 43662606 # Number of instructions committed +system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13661699 # Number of memory references committed -system.cpu0.commit.loads 8084046 # Number of loads committed -system.cpu0.commit.membars 197074 # Number of memory barriers committed -system.cpu0.commit.branches 7671683 # Number of branches committed -system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. -system.cpu0.commit.function_calls 648346 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11854981 # Number of memory references committed +system.cpu0.commit.loads 6964106 # Number of loads committed +system.cpu0.commit.membars 168172 # Number of memory barriers committed +system.cpu0.commit.branches 6551324 # Number of branches committed +system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. +system.cpu0.commit.function_calls 540020 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129398549 # The number of ROB reads -system.cpu0.rob.rob_writes 115399767 # The number of ROB writes -system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47867129 # Number of Instructions Simulated -system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated -system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads -system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads -system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes +system.cpu0.rob.rob_reads 110111593 # The number of ROB reads +system.cpu0.rob.rob_writes 98948174 # The number of ROB writes +system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41199881 # Number of Instructions Simulated +system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated +system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes +system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads +system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads +system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +947,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 867960 # number of replacements -system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use -system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits -system.cpu0.icache.overall_hits::total 6737923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses -system.cpu0.icache.overall_misses::total 912101 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.replacements 728874 # number of replacements +system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use +system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits +system.cpu0.icache.overall_hits::total 5890439 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses +system.cpu0.icache.overall_misses::total 766860 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # 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number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1274576 # number of replacements -system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits -system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses -system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # 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number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # 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Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits +system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses +system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks -system.cpu0.dcache.writebacks::total 749955 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks +system.cpu0.dcache.writebacks::total 554167 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1193,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2617746 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits +system.cpu1.branchPred.lookups 4327546 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1943067 # DTB read hits -system.cpu1.dtb.read_misses 10795 # DTB read misses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_accesses 324453 # DTB read accesses -system.cpu1.dtb.write_hits 1254400 # DTB write hits -system.cpu1.dtb.write_misses 2201 # DTB write misses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 132933 # DTB write accesses -system.cpu1.dtb.data_hits 3197467 # DTB hits -system.cpu1.dtb.data_misses 12996 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 457386 # DTB accesses -system.cpu1.itb.fetch_hits 434450 # ITB hits -system.cpu1.itb.fetch_misses 7705 # ITB misses -system.cpu1.itb.fetch_acv 232 # ITB acv -system.cpu1.itb.fetch_accesses 442155 # ITB accesses +system.cpu1.dtb.read_hits 3068448 # DTB read hits +system.cpu1.dtb.read_misses 13337 # DTB read misses +system.cpu1.dtb.read_acv 21 # DTB read access violations +system.cpu1.dtb.read_accesses 325420 # DTB read accesses +system.cpu1.dtb.write_hits 1915630 # DTB write hits +system.cpu1.dtb.write_misses 2521 # DTB write misses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_accesses 132592 # DTB write accesses +system.cpu1.dtb.data_hits 4984078 # DTB hits +system.cpu1.dtb.data_misses 15858 # DTB misses +system.cpu1.dtb.data_acv 89 # DTB access violations +system.cpu1.dtb.data_accesses 458012 # DTB accesses +system.cpu1.itb.fetch_hits 498592 # ITB hits +system.cpu1.itb.fetch_misses 6957 # ITB misses +system.cpu1.itb.fetch_acv 210 # ITB acv +system.cpu1.itb.fetch_accesses 505549 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1234,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16039611 # number of cpu cycles simulated +system.cpu1.numCycles 28341850 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued -system.cpu1.iq.rate 0.599231 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued +system.cpu1.iq.rate 0.572889 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 509280 # number of nop insts executed -system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1421889 # Number of branches executed -system.cpu1.iew.exec_stores 1262534 # Number of stores executed -system.cpu1.iew.exec_rate 0.593631 # Inst execution rate -system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4419848 # num instructions producing a value -system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value +system.cpu1.iew.exec_nop 989430 # number of nop insts executed +system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2535241 # Number of branches executed +system.cpu1.iew.exec_stores 1924592 # Number of stores executed +system.cpu1.iew.exec_rate 0.567378 # Inst execution rate +system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7724743 # num instructions producing a value +system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9315763 # Number of instructions committed -system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15801951 # Number of instructions committed +system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2968800 # Number of memory references committed -system.cpu1.commit.loads 1769624 # Number of loads committed -system.cpu1.commit.membars 44277 # Number of memory barriers committed -system.cpu1.commit.branches 1334383 # Number of branches committed -system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. -system.cpu1.commit.function_calls 148923 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4623326 # Number of memory references committed +system.cpu1.commit.loads 2789628 # Number of loads committed +system.cpu1.commit.membars 68640 # Number of memory barriers committed +system.cpu1.commit.branches 2366242 # Number of branches committed +system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. +system.cpu1.commit.function_calls 250839 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25106022 # The number of ROB reads -system.cpu1.rob.rob_writes 21862282 # The number of ROB writes -system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8868192 # Number of Instructions Simulated -system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated -system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads -system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes -system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes -system.cpu1.icache.replacements 223384 # number of replacements -system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use -system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits -system.cpu1.icache.overall_hits::total 1268764 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses -system.cpu1.icache.overall_misses::total 232532 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 42991260 # The number of ROB reads +system.cpu1.rob.rob_writes 37176651 # The number of ROB writes +system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14927555 # Number of Instructions Simulated +system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated +system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads +system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads +system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes +system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads +system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes +system.cpu1.icache.replacements 359909 # number of replacements +system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use +system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits +system.cpu1.icache.overall_hits::total 2054105 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses +system.cpu1.icache.overall_misses::total 376623 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 107089 # number of replacements -system.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits -system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses -system.cpu1.dcache.overall_misses::total 423319 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2307913 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2307913 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1365825 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1365825 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47088 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47088 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50932 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50932 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3673738 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3673738 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3673738 # number of overall hits +system.cpu1.dcache.overall_hits::total 3673738 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 542018 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses +system.cpu1.dcache.overall_misses::total 950793 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 21980337258 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 21980337258 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.205598 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.205598 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 393760 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks -system.cpu1.dcache.writebacks::total 70825 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks +system.cpu1.dcache.writebacks::total 289966 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1744,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1801,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167505 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches +system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed +system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 144957 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1255 -system.cpu0.kern.mode_good::user 1256 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3483 # number of times the context was actually changed +system.cpu0.kern.swap_context 2839 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1878,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed -system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed +system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50665 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches +system.cpu1.kern.callpal::total 71331 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 704 +system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 216 -system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1119 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1408 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 2f976aa78..0fbfca2a6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854344 # Number of seconds simulated -sim_ticks 1854344296500 # Number of ticks simulated -final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854310 # Number of seconds simulated +sim_ticks 1854309852000 # Number of ticks simulated +final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90928 # Simulator instruction rate (inst/s) -host_op_rate 90928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3182808238 # Simulator tick rate (ticks/s) -host_mem_usage 379332 # Number of bytes of host memory used -host_seconds 582.61 # Real time elapsed on the host -sim_insts 52976017 # Number of instructions simulated -sim_ops 52976017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879424 # Number of bytes read from this memory +host_inst_rate 117975 # Simulator instruction rate (inst/s) +host_op_rate 117975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4129044881 # Simulator tick rate (ticks/s) +host_mem_usage 335500 # Number of bytes of host memory used +host_seconds 449.09 # Real time elapsed on the host +sim_insts 52981417 # Number of instructions simulated +sim_ops 52981417 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964864 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15076 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13416831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13416831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19420877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445259 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445232 # Total number of read requests seen system.physmem.writeReqs 117444 # Total number of write requests seen -system.physmem.cpureqs 564803 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28496576 # Total number of bytes read from memory +system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28494848 # Total number of bytes read from memory system.physmem.bytesWritten 7516416 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28496576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27895 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7179 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7402 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7343 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7328 # Track writes on a per bank basis +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1365 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854338900000 # Total gap between requests +system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854304427000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445259 # Categorize read packet sizes +system.physmem.readPktSize::6 445232 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118809 # categorize write packet sizes +system.physmem.writePktSize::6 119231 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -106,32 +106,32 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 176 # categorize neither packet sizes +system.physmem.neitherpktsize::6 171 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,15 +142,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see @@ -165,46 +165,46 @@ system.physmem.wrQLenPdf::19 5106 # Wh system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6228802493 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13434068493 # Sum of mem lat for all requests -system.physmem.totBusLat 1780784000 # Total cycles spent in databus access -system.physmem.totBankLat 5424482000 # Total cycles spent in bank access -system.physmem.avgQLat 13991.15 # Average queueing delay per request -system.physmem.avgBankLat 12184.48 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30175.63 # Average memory access latency +system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests +system.physmem.totBusLat 2225860000 # Total cycles spent in databus access +system.physmem.totBankLat 5511935000 # Total cycles spent in bank access +system.physmem.avgQLat 17742.88 # Average queueing delay per request +system.physmem.avgBankLat 12381.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 35124.47 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 425317 # Number of row buffer hits during reads -system.physmem.writeRowHits 76610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.23 # Row buffer hit rate for writes -system.physmem.avgGap 3295413.21 # Average gap between requests +system.physmem.avgWrQLen 10.74 # Average write queue length over time +system.physmem.readRowHits 417598 # Number of row buffer hits during reads +system.physmem.writeRowHits 91555 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes +system.physmem.avgGap 3295510.08 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265367 # Cycle average of tags in use +system.iocache.tagsinuse 1.265033 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704469917000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265367 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079085 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079085 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9519862806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9519862806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9540790804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9540790804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9540790804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9540790804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229107.210387 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229107.210387 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228658.856896 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228658.856896 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189620 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22696 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.354776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7357096000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7357096000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7369027000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7369027000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7369027000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7369027000 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177057.566423 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177057.566423 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +300,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13851594 # Number of BP lookups -system.cpu.branchPred.condPredicted 11614390 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 401305 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9533712 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5819078 # Number of BTB hits +system.cpu.branchPred.lookups 13854519 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.036855 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 909714 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39020 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9948747 # DTB read hits -system.cpu.dtb.read_misses 41658 # DTB read misses -system.cpu.dtb.read_acv 544 # DTB read access violations -system.cpu.dtb.read_accesses 942034 # DTB read accesses -system.cpu.dtb.write_hits 6596243 # DTB write hits -system.cpu.dtb.write_misses 10259 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 337916 # DTB write accesses -system.cpu.dtb.data_hits 16544990 # DTB hits -system.cpu.dtb.data_misses 51917 # DTB misses -system.cpu.dtb.data_acv 949 # DTB access violations -system.cpu.dtb.data_accesses 1279950 # DTB accesses -system.cpu.itb.fetch_hits 1308175 # ITB hits -system.cpu.itb.fetch_misses 37074 # ITB misses -system.cpu.itb.fetch_acv 1064 # ITB acv -system.cpu.itb.fetch_accesses 1345249 # ITB accesses +system.cpu.dtb.read_hits 9921013 # DTB read hits +system.cpu.dtb.read_misses 41705 # DTB read misses +system.cpu.dtb.read_acv 547 # DTB read access violations +system.cpu.dtb.read_accesses 941529 # DTB read accesses +system.cpu.dtb.write_hits 6598119 # DTB write hits +system.cpu.dtb.write_misses 10489 # DTB write misses +system.cpu.dtb.write_acv 411 # DTB write access violations +system.cpu.dtb.write_accesses 338424 # DTB write accesses +system.cpu.dtb.data_hits 16519132 # DTB hits +system.cpu.dtb.data_misses 52194 # DTB misses +system.cpu.dtb.data_acv 958 # DTB access violations +system.cpu.dtb.data_accesses 1279953 # DTB accesses +system.cpu.itb.fetch_hits 1307587 # ITB hits +system.cpu.itb.fetch_misses 36909 # ITB misses +system.cpu.itb.fetch_acv 1032 # ITB acv +system.cpu.itb.fetch_accesses 1344496 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +341,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108725026 # number of cpu cycles simulated +system.cpu.numCycles 109625107 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13285208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2019522 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37381794 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254614 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 318469 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 142 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8594512 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267109 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80688804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.878389 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67403596 83.54% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 853020 1.06% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1704381 2.11% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825297 1.02% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2770281 3.43% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 565024 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 647860 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009692 1.25% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4909653 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80688804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127400 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.651884 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29267449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37052866 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12136986 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 973710 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1257792 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584936 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69563521 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129851 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1257792 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30404358 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13652369 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19747652 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11366309 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4260322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65705710 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6891 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503348 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1491459 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43870153 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79781182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79301924 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479258 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38177024 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5693121 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1683221 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184382 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10464940 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6914709 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1324795 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 859458 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58224316 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050276 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56824991 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6935340 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3625371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389407 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80688804 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704249 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364971 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56018871 69.43% 69.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10823549 13.41% 82.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5172467 6.41% 89.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3386571 4.20% 93.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2641337 3.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1466438 1.82% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753039 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331233 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95299 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80688804 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 89852 11.44% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373396 47.53% 58.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322395 41.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38724808 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10379587 18.27% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6673501 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948876 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56824991 # Type of FU issued -system.cpu.iq.rate 0.522649 # Inst issue rate -system.cpu.iq.fu_busy_cnt 785643 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013826 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194541335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66886966 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55559556 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692645 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336736 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327839 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57241937 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597577 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued +system.cpu.iq.rate 0.518346 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1373561 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3601 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 537300 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17953 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 206148 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1257792 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9964029 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 681966 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63803743 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 689880 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10464940 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6914709 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511141 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 204181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56359720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10018596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 465270 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3529151 # number of nop insts executed -system.cpu.iew.exec_refs 16640307 # number of memory reference insts executed -system.cpu.iew.exec_branches 8921025 # Number of branches executed -system.cpu.iew.exec_stores 6621711 # Number of stores executed -system.cpu.iew.exec_rate 0.518369 # Inst execution rate -system.cpu.iew.wb_sent 56002392 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55887395 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27763328 # num instructions producing a value -system.cpu.iew.wb_consumers 37600496 # num instructions consuming a value +system.cpu.iew.exec_nop 3527845 # number of nop insts executed +system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed +system.cpu.iew.exec_branches 8928138 # Number of branches executed +system.cpu.iew.exec_stores 6623837 # Number of stores executed +system.cpu.iew.exec_rate 0.514074 # Inst execution rate +system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27775021 # num instructions producing a value +system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738377 # average fanout of values written-back +system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7517612 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660869 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569940 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79431012 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.636757 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58662505 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8598581 10.83% 84.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4616252 5.81% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2527219 3.18% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1515396 1.91% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 608578 0.77% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 519366 0.65% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 531746 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851369 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79431012 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56166586 # Number of instructions committed -system.cpu.commit.committedOps 56166586 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172173 # Number of instructions committed +system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15468788 # Number of memory references committed -system.cpu.commit.loads 9091379 # Number of loads committed -system.cpu.commit.membars 226331 # Number of memory barriers committed -system.cpu.commit.branches 8439881 # Number of branches committed +system.cpu.commit.refs 15470144 # Number of memory references committed +system.cpu.commit.loads 9092271 # Number of loads committed +system.cpu.commit.membars 226349 # Number of memory barriers committed +system.cpu.commit.branches 8440686 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52016583 # Number of committed integer instructions. -system.cpu.commit.function_calls 740455 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851369 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52021801 # Number of committed integer instructions. +system.cpu.commit.function_calls 740555 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141014350 # The number of ROB reads -system.cpu.rob.rob_writes 128628080 # The number of ROB writes -system.cpu.timesIdled 1177475 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28036222 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599957129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52976017 # Number of Instructions Simulated -system.cpu.committedOps 52976017 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52976017 # Number of Instructions Simulated -system.cpu.cpi 2.052344 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.052344 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487248 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487248 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73894396 # number of integer regfile reads -system.cpu.int_regfile_writes 40308039 # number of integer regfile writes -system.cpu.fp_regfile_reads 165978 # number of floating regfile reads -system.cpu.fp_regfile_writes 167424 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987130 # number of misc regfile reads -system.cpu.misc_regfile_writes 938828 # number of misc regfile writes +system.cpu.rob.rob_reads 140883934 # The number of ROB reads +system.cpu.rob.rob_writes 128542305 # The number of ROB writes +system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981417 # Number of Instructions Simulated +system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated +system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads +system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73895852 # number of integer regfile reads +system.cpu.int_regfile_writes 40324169 # number of integer regfile writes +system.cpu.fp_regfile_reads 166027 # number of floating regfile reads +system.cpu.fp_regfile_writes 167433 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +635,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1010112 # number of replacements -system.cpu.icache.tagsinuse 510.299453 # Cycle average of tags in use -system.cpu.icache.total_refs 7527432 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1010620 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.448331 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20108875000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.299453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7527433 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7527433 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7527433 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7527433 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7527433 # number of overall hits -system.cpu.icache.overall_hits::total 7527433 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1067079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1067079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1067079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1067079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1067079 # number of overall misses -system.cpu.icache.overall_misses::total 1067079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14519095993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14519095993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14519095993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14519095993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14519095993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14519095993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8594512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8594512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8594512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8594512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8594512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8594512 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124158 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124158 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124158 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124158 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.392772 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13606.392772 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13606.392772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13606.392772 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4279 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 166 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.777108 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 616 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010840 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010840 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010840 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010840 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010840 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010840 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11925850497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11925850497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11925850497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11925850497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11925850497 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +899,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400546 # number of replacements -system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use -system.cpu.dcache.total_refs 11813976 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401058 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.432182 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1401345 # number of replacements +system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use +system.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27944.519378 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27944.519378 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2603227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95613 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.226706 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840422 # number of writebacks -system.cpu.dcache.writebacks::total 840422 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642682 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642682 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5172 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5172 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359876 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359876 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359876 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359876 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083393 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083393 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300315 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300315 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17494 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17494 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383708 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383708 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383708 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383708 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21171794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21171794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10766258774 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10766258774 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199318000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199318000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31938052774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31938052774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31938052774 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31938052774 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423872500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423872500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997246998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997246998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421119498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421119498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083806 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083806 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091299 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091299 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19542.118142 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19542.118142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35849.886865 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35849.886865 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11393.506345 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11393.506345 # average LoadLockedReq mshr miss latency +system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks +system.cpu.dcache.writebacks::total 840942 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1062,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74649 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105543 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182201 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73282 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73282 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148573 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818511438500 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63990000 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 557700000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35210339500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854343468000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694333 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,29 +1122,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175088 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191930 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 191983 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29685190500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2663206500 0.14% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821995063000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index a2c647b2a..97e7b92d5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841687 # Number of seconds simulated -sim_ticks 1841687115500 # Number of ticks simulated -final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841686 # Number of seconds simulated +sim_ticks 1841685645500 # Number of ticks simulated +final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216690 # Simulator instruction rate (inst/s) -host_op_rate 216690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5785819991 # Simulator tick rate (ticks/s) -host_mem_usage 360768 # Number of bytes of host memory used -host_seconds 318.31 # Real time elapsed on the host -sim_insts 68974794 # Number of instructions simulated -sim_ops 68974794 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19299136 # Number of bytes read from this memory +host_inst_rate 340884 # Simulator instruction rate (inst/s) +host_op_rate 340884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9045969324 # Simulator tick rate (ticks/s) +host_mem_usage 315876 # Number of bytes of host memory used +host_seconds 203.59 # Real time elapsed on the host +sim_insts 69401254 # Number of instructions simulated +sim_ops 69401254 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2831040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2739200 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7474752 # Number of bytes written to this memory -system.physmem.bytes_written::total 7474752 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 301549 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory +system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 44235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444387 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116793 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116793 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10479053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1537199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1487332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4058644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4058644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4058644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10479053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1537199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1487332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 111257 # Total number of read requests seen -system.physmem.writeReqs 46272 # Total number of write requests seen -system.physmem.cpureqs 157922 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7120448 # Total number of bytes read from memory -system.physmem.bytesWritten 2961408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7120448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2961408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 8 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109303 # Total number of read requests seen +system.physmem.writeReqs 45531 # Total number of write requests seen +system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6995392 # Total number of bytes read from memory +system.physmem.bytesWritten 2913984 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6539 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7093 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 7124 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6929 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7137 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6842 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 3003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2700 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2711 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 191 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840675056500 # Total gap between requests +system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673558000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 111257 # Categorize read packet sizes +system.physmem.readPktSize::6 109303 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -117,7 +117,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46463 # categorize write packet sizes +system.physmem.writePktSize::6 46533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,27 +129,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 41 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 82762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -162,243 +162,239 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1656369284 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3548083284 # Sum of mem lat for all requests -system.physmem.totBusLat 444996000 # Total cycles spent in databus access -system.physmem.totBankLat 1446718000 # Total cycles spent in bank access -system.physmem.avgQLat 14888.85 # Average queueing delay per request -system.physmem.avgBankLat 13004.32 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31893.17 # Average memory access latency -system.physmem.avgRdBW 3.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.61 # 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Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -525,14 +521,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # 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miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 95029.078961 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 95029.078961 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 94855.033841 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 94855.033841 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78872 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9708 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.124433 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,36 +565,36 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17349 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176461.156192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176461.156192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -616,22 +612,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4860289 # DTB read hits -system.cpu0.dtb.read_misses 5912 # DTB read misses -system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 426830 # DTB read accesses -system.cpu0.dtb.write_hits 3490049 # DTB write hits -system.cpu0.dtb.write_misses 657 # DTB write misses -system.cpu0.dtb.write_acv 81 # DTB write access violations -system.cpu0.dtb.write_accesses 163148 # DTB write accesses -system.cpu0.dtb.data_hits 8350338 # DTB hits -system.cpu0.dtb.data_misses 6569 # DTB misses -system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 589978 # DTB accesses -system.cpu0.itb.fetch_hits 2736650 # ITB hits -system.cpu0.itb.fetch_misses 2973 # ITB misses -system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2739623 # ITB accesses +system.cpu0.dtb.read_hits 4870224 # DTB read hits +system.cpu0.dtb.read_misses 6004 # DTB read misses +system.cpu0.dtb.read_acv 119 # DTB read access violations +system.cpu0.dtb.read_accesses 427226 # DTB read accesses +system.cpu0.dtb.write_hits 3495920 # DTB write hits +system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 162893 # DTB write accesses +system.cpu0.dtb.data_hits 8366144 # DTB hits +system.cpu0.dtb.data_misses 6666 # DTB misses +system.cpu0.dtb.data_acv 201 # DTB access violations +system.cpu0.dtb.data_accesses 590119 # DTB accesses +system.cpu0.itb.fetch_hits 2742252 # ITB hits +system.cpu0.itb.fetch_misses 2999 # ITB misses +system.cpu0.itb.fetch_acv 100 # ITB acv +system.cpu0.itb.fetch_accesses 2745251 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -644,51 +640,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928580994 # number of cpu cycles simulated +system.cpu0.numCycles 928524557 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32061485 # Number of instructions committed -system.cpu0.committedOps 32061485 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29946926 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167785 # Number of float alu accesses -system.cpu0.num_func_calls 806855 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4176537 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29946926 # number of integer instructions -system.cpu0.num_fp_insts 167785 # number of float instructions -system.cpu0.num_int_register_reads 41669823 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21912533 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86645 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88213 # number of times the floating registers were written -system.cpu0.num_mem_refs 8379762 # number of memory refs -system.cpu0.num_load_insts 4881104 # Number of load instructions -system.cpu0.num_store_insts 3498658 # Number of store instructions -system.cpu0.num_idle_cycles 214035268696.310638 # Number of idle cycles -system.cpu0.num_busy_cycles -213106687702.310638 # Number of busy cycles -system.cpu0.not_idle_fraction -229.497146 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.497146 # Percentage of idle cycles +system.cpu0.committedInsts 32346409 # Number of instructions committed +system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30227601 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses +system.cpu0.num_func_calls 807221 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30227601 # number of integer instructions +system.cpu0.num_fp_insts 167714 # number of float instructions +system.cpu0.num_int_register_reads 42120333 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22107858 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written +system.cpu0.num_mem_refs 8395831 # number of memory refs +system.cpu0.num_load_insts 4891260 # Number of load instructions +system.cpu0.num_store_insts 3504571 # Number of store instructions +system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles +system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles +system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211380 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74799 40.97% 40.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 205 0.11% 41.08% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73432 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 205 0.14% 49.44% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818622166500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39746000 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363817000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22660629500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841686359000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818585880000 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39023000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696630500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -724,33 +720,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.callpal::total 192218 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29768907500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2544697000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809372751000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_ticks::kernel 29741942000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2557109000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -782,372 +778,356 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953436 # number of replacements -system.cpu0.icache.tagsinuse 511.198067 # Cycle average of tags in use -system.cpu0.icache.total_refs 41560742 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953947 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.567139 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10234504000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 256.477356 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.519770 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.200941 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.500932 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155312 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.342189 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998434 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31547031 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7721485 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2292226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41560742 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31547031 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7721485 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2292226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41560742 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31547031 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7721485 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2292226 # number of overall hits -system.cpu0.icache.overall_hits::total 41560742 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521213 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129218 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320460 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970891 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521213 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129218 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320460 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970891 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521213 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129218 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320460 # number of overall misses -system.cpu0.icache.overall_misses::total 970891 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794259500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4426264489 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6220523989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1794259500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4426264489 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6220523989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1794259500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4426264489 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6220523989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32068244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7850703 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2612686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42531633 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32068244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7850703 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2612686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42531633 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32068244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7850703 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2612686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42531633 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016253 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016459 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122655 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022828 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016253 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016459 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122655 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022828 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016253 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016459 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122655 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022828 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13885.522915 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.221460 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6407.026112 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6407.026112 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6407.026112 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1940 # number of cycles access was blocked +system.cpu0.icache.replacements 952687 # number of replacements +system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use +system.cpu0.icache.total_refs 41854963 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 953198 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 43.910041 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 175.771256 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7734859 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2288176 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41854963 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7734859 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2288176 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41854963 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7734859 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2288176 # number of overall hits +system.cpu0.icache.overall_hits::total 41854963 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.681331 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645594000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 754135000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1399729000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088589 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041134 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053154 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045410 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021712 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101943 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101948 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038763 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000038 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033208 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033208 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18815.879750 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16354.540243 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17048.811169 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27397.157676 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26952.040582 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27112.738692 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.589837 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12738.099436 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12300.850686 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 836144 # number of writebacks +system.cpu0.dcache.writebacks::total 836144 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285747 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285747 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477794 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 477794 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1510 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1510 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 763541 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 763541 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 763541 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 763541 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103680 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261914 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 365594 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 498865 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314581000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280101000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297796000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263316000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465636620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9728952620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263316000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465636620 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9728952620 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342019500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760661500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.273670 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.801058 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.976572 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.485342 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1162,22 +1142,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220100 # DTB read hits -system.cpu1.dtb.read_misses 1488 # DTB read misses -system.cpu1.dtb.read_acv 40 # DTB read access violations -system.cpu1.dtb.read_accesses 143779 # DTB read accesses -system.cpu1.dtb.write_hits 928690 # DTB write hits -system.cpu1.dtb.write_misses 201 # DTB write misses +system.cpu1.dtb.read_hits 1220324 # DTB read hits +system.cpu1.dtb.read_misses 1556 # DTB read misses +system.cpu1.dtb.read_acv 46 # DTB read access violations +system.cpu1.dtb.read_accesses 144016 # DTB read accesses +system.cpu1.dtb.write_hits 928239 # DTB write hits +system.cpu1.dtb.write_misses 207 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 59743 # DTB write accesses -system.cpu1.dtb.data_hits 2148790 # DTB hits -system.cpu1.dtb.data_misses 1689 # DTB misses -system.cpu1.dtb.data_acv 64 # DTB access violations -system.cpu1.dtb.data_accesses 203522 # DTB accesses -system.cpu1.itb.fetch_hits 872643 # ITB hits -system.cpu1.itb.fetch_misses 756 # ITB misses -system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 873399 # ITB accesses +system.cpu1.dtb.write_accesses 60107 # DTB write accesses +system.cpu1.dtb.data_hits 2148563 # DTB hits +system.cpu1.dtb.data_misses 1763 # DTB misses +system.cpu1.dtb.data_acv 70 # DTB access violations +system.cpu1.dtb.data_accesses 204123 # DTB accesses +system.cpu1.itb.fetch_hits 875123 # ITB hits +system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.itb.fetch_acv 46 # ITB acv +system.cpu1.itb.fetch_accesses 875897 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1190,28 +1170,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953546573 # number of cpu cycles simulated +system.cpu1.numCycles 953544050 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7848949 # Number of instructions committed -system.cpu1.committedOps 7848949 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7301756 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45390 # Number of float alu accesses -system.cpu1.num_func_calls 212250 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 958041 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7301756 # number of integer instructions -system.cpu1.num_fp_insts 45390 # number of float instructions -system.cpu1.num_int_register_reads 10145726 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5312805 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24524 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24770 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156479 # number of memory refs -system.cpu1.num_load_insts 1225350 # Number of load instructions -system.cpu1.num_store_insts 931129 # Number of store instructions -system.cpu1.num_idle_cycles -1690648572.086683 # Number of idle cycles -system.cpu1.num_busy_cycles 2644195145.086683 # Number of busy cycles -system.cpu1.not_idle_fraction 2.773011 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.773011 # Percentage of idle cycles +system.cpu1.committedInsts 7861954 # Number of instructions committed +system.cpu1.committedOps 7861954 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7314134 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses +system.cpu1.num_func_calls 212083 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7314134 # number of integer instructions +system.cpu1.num_fp_insts 45433 # number of float instructions +system.cpu1.num_int_register_reads 10166177 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5323216 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written +system.cpu1.num_mem_refs 2156447 # number of memory refs +system.cpu1.num_load_insts 1225739 # Number of load instructions +system.cpu1.num_store_insts 930708 # Number of store instructions +system.cpu1.num_idle_cycles 195910529.325868 # Number of idle cycles +system.cpu1.num_busy_cycles 757633520.674132 # Number of busy cycles +system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1229,35 +1209,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8367198 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7675066 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129021 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6898028 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5713360 # Number of BTB hits +system.cpu2.branchPred.lookups 8412637 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5762098 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 82.825990 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 286292 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15213 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.529018 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 288280 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3233315 # DTB read hits -system.cpu2.dtb.read_misses 12189 # DTB read misses -system.cpu2.dtb.read_acv 135 # DTB read access violations -system.cpu2.dtb.read_accesses 219207 # DTB read accesses -system.cpu2.dtb.write_hits 2006633 # DTB write hits -system.cpu2.dtb.write_misses 2635 # DTB write misses -system.cpu2.dtb.write_acv 145 # DTB write access violations -system.cpu2.dtb.write_accesses 81760 # DTB write accesses -system.cpu2.dtb.data_hits 5239948 # DTB hits -system.cpu2.dtb.data_misses 14824 # DTB misses -system.cpu2.dtb.data_acv 280 # DTB access violations -system.cpu2.dtb.data_accesses 300967 # DTB accesses -system.cpu2.itb.fetch_hits 374893 # ITB hits -system.cpu2.itb.fetch_misses 5781 # ITB misses -system.cpu2.itb.fetch_acv 261 # ITB acv -system.cpu2.itb.fetch_accesses 380674 # ITB accesses +system.cpu2.dtb.read_hits 3230835 # DTB read hits +system.cpu2.dtb.read_misses 11458 # DTB read misses +system.cpu2.dtb.read_acv 112 # DTB read access violations +system.cpu2.dtb.read_accesses 217040 # DTB read accesses +system.cpu2.dtb.write_hits 2001660 # DTB write hits +system.cpu2.dtb.write_misses 2605 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 81606 # DTB write accesses +system.cpu2.dtb.data_hits 5232495 # DTB hits +system.cpu2.dtb.data_misses 14063 # DTB misses +system.cpu2.dtb.data_acv 255 # DTB access violations +system.cpu2.dtb.data_accesses 298646 # DTB accesses +system.cpu2.itb.fetch_hits 371714 # ITB hits +system.cpu2.itb.fetch_misses 5691 # ITB misses +system.cpu2.itb.fetch_acv 245 # ITB acv +system.cpu2.itb.fetch_accesses 377405 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1270,270 +1250,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30553382 # number of cpu cycles simulated +system.cpu2.numCycles 30535701 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5999652 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8085881 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 623525 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9702754 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 9910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1956 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78066 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 227 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2612689 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89635 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26899441 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.295181 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.310992 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8533986 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34964689 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8412637 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8133499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 621333 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9684422 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2608249 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90274 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26910354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.299302 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18813560 69.94% 69.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 273460 1.02% 70.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 442537 1.65% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4198605 15.61% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 738968 2.75% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167733 0.62% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196064 0.73% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433736 1.61% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1634778 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18776855 69.78% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4254201 15.81% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1630673 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26899441 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.273855 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.140288 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8679846 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9796545 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7488897 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294076 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 394122 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 169250 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12966 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34438242 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40605 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 394122 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9036155 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2833856 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5793548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7343930 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1251886 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33280862 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 235752 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410323 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22341851 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41449381 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41284168 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165213 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20505105 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1836746 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 509428 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60335 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3708993 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3395949 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2096293 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374269 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 256431 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30745321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 631973 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30290863 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 30934 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2196077 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1091992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 446408 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26899441 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.126078 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565187 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26910354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.145043 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8661365 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9779402 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7537150 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 392382 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168927 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12968 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34563094 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40757 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 392382 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9017323 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2819487 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5795757 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7393744 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1245786 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33400489 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 410991 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22419821 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41624595 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41459018 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20586998 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832823 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3692928 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2097985 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 374320 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30872998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30415497 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2194504 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1105046 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26910354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565604 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15349062 57.06% 57.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3113388 11.57% 68.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1556519 5.79% 74.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5024470 18.68% 93.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 916558 3.41% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 490691 1.82% 98.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 288280 1.07% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142124 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18349 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15319537 56.93% 56.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3107474 11.55% 68.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555934 5.78% 74.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5075643 18.86% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 913365 3.39% 96.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 492006 1.83% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286832 1.07% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 17803 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26899441 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26910354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 35139 13.92% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113314 44.90% 58.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103925 41.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24571272 81.12% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20288 0.07% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8510 0.03% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3364677 11.11% 92.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2029119 6.70% 99.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 293313 0.97% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24705605 81.23% 81.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3362289 11.05% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024695 6.66% 99.05% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30290863 # Type of FU issued -system.cpu2.iq.rate 0.991408 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 252378 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87527172 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33461701 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29889528 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237307 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 115799 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112442 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30417117 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123668 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 190380 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30415497 # Type of FU issued +system.cpu2.iq.rate 0.996063 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87793643 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33586183 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30009832 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30540939 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 417328 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 909 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4219 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 161835 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 420182 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 166078 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5028 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23504 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 394122 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2048539 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 212384 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32667767 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 225947 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3395949 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2096293 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 561038 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149803 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2446 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4219 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66256 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 130204 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196460 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30129770 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3254028 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 161093 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 392382 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32790346 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224393 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2097985 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 129830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196510 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30250738 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3250585 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 164759 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1290473 # number of nop insts executed -system.cpu2.iew.exec_refs 5267847 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6767321 # Number of branches executed -system.cpu2.iew.exec_stores 2013819 # Number of stores executed -system.cpu2.iew.exec_rate 0.986135 # Inst execution rate -system.cpu2.iew.wb_sent 30034994 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30001970 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17305763 # num instructions producing a value -system.cpu2.iew.wb_consumers 20552521 # num instructions consuming a value +system.cpu2.iew.exec_nop 1286377 # number of nop insts executed +system.cpu2.iew.exec_refs 5259361 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6817854 # Number of branches executed +system.cpu2.iew.exec_stores 2008776 # Number of stores executed +system.cpu2.iew.exec_rate 0.990668 # Inst execution rate +system.cpu2.iew.wb_sent 30155470 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30122461 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17393526 # num instructions producing a value +system.cpu2.iew.wb_consumers 20640191 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.981953 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842026 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.986467 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2377399 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185565 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182360 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26505319 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.141095 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851284 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182288 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26517972 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.145282 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.851176 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16405167 61.89% 61.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2334119 8.81% 70.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1221930 4.61% 75.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4753276 17.93% 93.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503631 1.90% 95.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 187421 0.71% 95.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 180293 0.68% 96.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 181960 0.69% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 737522 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16375650 61.75% 61.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2329506 8.78% 70.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218962 4.60% 75.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4807374 18.13% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186920 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179412 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 736841 2.78% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26505319 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30245090 # Number of instructions committed -system.cpu2.commit.committedOps 30245090 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26517972 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30370560 # Number of instructions committed +system.cpu2.commit.committedOps 30370560 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4913079 # Number of memory references committed -system.cpu2.commit.loads 2978621 # Number of loads committed -system.cpu2.commit.membars 65145 # Number of memory barriers committed -system.cpu2.commit.branches 6616794 # Number of branches committed -system.cpu2.commit.fp_insts 111215 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28779164 # Number of committed integer instructions. -system.cpu2.commit.function_calls 231926 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 737522 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4905588 # Number of memory references committed +system.cpu2.commit.loads 2973681 # Number of loads committed +system.cpu2.commit.membars 65235 # Number of memory barriers committed +system.cpu2.commit.branches 6667985 # Number of branches committed +system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28908362 # Number of committed integer instructions. +system.cpu2.commit.function_calls 232233 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 736841 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58315466 # The number of ROB reads -system.cpu2.rob.rob_writes 65639010 # The number of ROB writes -system.cpu2.timesIdled 244602 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3653941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745271968 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29064360 # Number of Instructions Simulated -system.cpu2.committedOps 29064360 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29064360 # Number of Instructions Simulated -system.cpu2.cpi 1.051232 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.051232 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.951265 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.951265 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39620111 # number of integer regfile reads -system.cpu2.int_regfile_writes 21211926 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68528 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68903 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4553685 # number of misc regfile reads -system.cpu2.misc_regfile_writes 261693 # number of misc regfile writes +system.cpu2.rob.rob_reads 58454827 # The number of ROB reads +system.cpu2.rob.rob_writes 65882898 # The number of ROB writes +system.cpu2.timesIdled 242873 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3625347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29192891 # Number of Instructions Simulated +system.cpu2.committedOps 29192891 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29192891 # Number of Instructions Simulated +system.cpu2.cpi 1.045998 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.045998 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39779581 # number of integer regfile reads +system.cpu2.int_regfile_writes 21289103 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads +system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 46a681edb..4d949983c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,126 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523205 # Number of seconds simulated -sim_ticks 2523204701000 # Number of ticks simulated -final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533245 # Number of seconds simulated +sim_ticks 2533245380500 # Number of ticks simulated +final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41110 # Simulator instruction rate (inst/s) -host_op_rate 52896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1720016966 # Simulator tick rate (ticks/s) -host_mem_usage 452892 # Number of bytes of host memory used -host_seconds 1466.97 # Real time elapsed on the host -sim_insts 60306320 # Number of instructions simulated -sim_ops 77597310 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 68339 # Simulator instruction rate (inst/s) +host_op_rate 87933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2870562080 # Simulator tick rate (ticks/s) +host_mem_usage 409768 # Number of bytes of host memory used +host_seconds 882.49 # Real time elapsed on the host +sim_insts 60308251 # Number of instructions simulated +sim_ops 77599937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096856 # Total number of read requests seen -system.physmem.writeReqs 813138 # Total number of write requests seen -system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198784 # Total number of bytes read from memory -system.physmem.bytesWritten 52040832 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis +system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096850 # Total number of read requests seen +system.physmem.writeReqs 813145 # Total number of write requests seen +system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198400 # Total number of bytes read from memory +system.physmem.bytesWritten 52041280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523203522000 # Total gap between requests +system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533244279000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154612 # Categorize read packet sizes +system.physmem.readPktSize::6 154606 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1943854 # categorize write packet sizes +system.physmem.writePktSize::2 2927056 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59120 # categorize write packet sizes +system.physmem.writePktSize::6 59127 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -184,61 +172,73 @@ system.physmem.wrQLenPdf::15 35354 # Wh system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests -system.physmem.totBusLat 60386192000 # Total cycles spent in databus access -system.physmem.totBankLat 16356620000 # Total cycles spent in bank access -system.physmem.avgQLat 21743.10 # Average queueing delay per request -system.physmem.avgBankLat 1083.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26826.57 # Average memory access latency -system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 10.68 # Average write queue length over time -system.physmem.readRowHits 15052450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784654 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes -system.physmem.avgGap 158592.36 # Average gap between requests +system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests +system.physmem.totBusLat 75482595000 # Total cycles spent in databus access +system.physmem.totBankLat 16916941250 # Total cycles spent in bank access +system.physmem.avgQLat 26034.38 # Average queueing delay per request +system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32154.97 # Average memory access latency +system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 15020214 # Number of row buffer hits during reads +system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159223.45 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14400111 # Number of BP lookups -system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits +system.cpu.branchPred.lookups 14667589 # Number of BP lookups +system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14986991 # DTB read hits +system.cpu.checker.dtb.read_hits 14987593 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227488 # DTB write hits +system.cpu.checker.dtb.write_hits 11227866 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -249,13 +249,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994298 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229677 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994900 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11230055 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26214479 # DTB hits +system.cpu.checker.dtb.hits 26215459 # DTB hits system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26223975 # DTB accesses -system.cpu.checker.itb.inst_hits 61480313 # ITB inst hits +system.cpu.checker.dtb.accesses 26224955 # DTB accesses +system.cpu.checker.itb.inst_hits 61482253 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -272,36 +272,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61484784 # ITB inst accesses -system.cpu.checker.itb.hits 61480313 # DTB hits +system.cpu.checker.itb.inst_accesses 61486724 # ITB inst accesses +system.cpu.checker.itb.hits 61482253 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61484784 # DTB accesses -system.cpu.checker.numCycles 77883110 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486724 # DTB accesses +system.cpu.checker.numCycles 77885746 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51212683 # DTB read hits -system.cpu.dtb.read_misses 73387 # DTB read misses -system.cpu.dtb.write_hits 11701466 # DTB write hits -system.cpu.dtb.write_misses 17011 # DTB write misses +system.cpu.dtb.read_hits 51389080 # DTB read hits +system.cpu.dtb.read_misses 73326 # DTB read misses +system.cpu.dtb.write_hits 11702658 # DTB write hits +system.cpu.dtb.write_misses 17128 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7759 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7749 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51286070 # DTB read accesses -system.cpu.dtb.write_accesses 11718477 # DTB write accesses +system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51462406 # DTB read accesses +system.cpu.dtb.write_accesses 11719786 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62914149 # DTB hits -system.cpu.dtb.misses 90398 # DTB misses -system.cpu.dtb.accesses 63004547 # DTB accesses -system.cpu.itb.inst_hits 11530598 # ITB inst hits -system.cpu.itb.inst_misses 11503 # ITB inst misses +system.cpu.dtb.hits 63091738 # DTB hits +system.cpu.dtb.misses 90454 # DTB misses +system.cpu.dtb.accesses 63182192 # DTB accesses +system.cpu.itb.inst_hits 12277036 # ITB inst hits +system.cpu.itb.inst_misses 11490 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -310,114 +310,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5166 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5150 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11542101 # ITB inst accesses -system.cpu.itb.hits 11530598 # DTB hits -system.cpu.itb.misses 11503 # DTB misses -system.cpu.itb.accesses 11542101 # DTB accesses -system.cpu.numCycles 469830472 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12288526 # ITB inst accesses +system.cpu.itb.hits 12277036 # DTB hits +system.cpu.itb.misses 11490 # DTB misses +system.cpu.itb.accesses 12288526 # DTB accesses +system.cpu.numCycles 472097236 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -445,383 +445,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued -system.cpu.iq.rate 0.261848 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued +system.cpu.iq.rate 0.263176 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221038 # number of nop insts executed -system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed -system.cpu.iew.exec_branches 11477980 # Number of branches executed -system.cpu.iew.exec_stores 12213052 # Number of stores executed -system.cpu.iew.exec_rate 0.257448 # Inst execution rate -system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47051195 # num instructions producing a value -system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value +system.cpu.iew.exec_nop 220577 # number of nop insts executed +system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed +system.cpu.iew.exec_branches 11563754 # Number of branches executed +system.cpu.iew.exec_stores 12214366 # Number of stores executed +system.cpu.iew.exec_rate 0.257379 # Inst execution rate +system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47207424 # num instructions producing a value +system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456701 # Number of instructions committed -system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458632 # Number of instructions committed +system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385892 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403583 # Number of memory barriers committed -system.cpu.commit.branches 9961154 # Number of branches committed +system.cpu.commit.refs 27386920 # Number of memory references committed +system.cpu.commit.loads 15654712 # Number of loads committed +system.cpu.commit.membars 403607 # Number of memory barriers committed +system.cpu.commit.branches 9961406 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. -system.cpu.commit.function_calls 991222 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. +system.cpu.commit.function_calls 991273 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 238273902 # The number of ROB reads -system.cpu.rob.rob_writes 196332947 # The number of ROB writes -system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306320 # Number of Instructions Simulated -system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated -system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547824488 # number of integer regfile reads -system.cpu.int_regfile_writes 87698032 # number of integer regfile writes -system.cpu.fp_regfile_reads 8340 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads -system.cpu.misc_regfile_writes 831851 # number of misc regfile writes -system.cpu.icache.replacements 979772 # number of replacements -system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use -system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits -system.cpu.icache.overall_hits::total 10466836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses -system.cpu.icache.overall_misses::total 1059904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.rob.rob_reads 242460133 # The number of ROB reads +system.cpu.rob.rob_writes 201635862 # The number of ROB writes +system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60308251 # Number of Instructions Simulated +system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated +system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550197997 # number of integer regfile reads +system.cpu.int_regfile_writes 88410648 # number of integer regfile writes +system.cpu.fp_regfile_reads 8198 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980802 # number of replacements +system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use +system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits +system.cpu.icache.overall_hits::total 11213050 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses +system.cpu.icache.overall_misses::total 1060138 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -942,161 +942,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21025205 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks -system.cpu.dcache.writebacks::total 607596 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks +system.cpu.dcache.writebacks::total 607265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1118,16 +1118,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 572fe69c1..c67fcab1e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.092969 # Number of seconds simulated -sim_ticks 1092968826500 # Number of ticks simulated -final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.103053 # Number of seconds simulated +sim_ticks 1103052934500 # Number of ticks simulated +final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49884 # Simulator instruction rate (inst/s) -host_op_rate 64220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 885142778 # Simulator tick rate (ticks/s) -host_mem_usage 458008 # Number of bytes of host memory used -host_seconds 1234.79 # Real time elapsed on the host -sim_insts 61595972 # Number of instructions simulated -sim_ops 79298956 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 59 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 351 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 410 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 59 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 351 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 410 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 59 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 351 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 410 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 84555 # Simulator instruction rate (inst/s) +host_op_rate 108843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1514437253 # Simulator tick rate (ticks/s) +host_mem_usage 415912 # Number of bytes of host memory used +host_seconds 728.36 # Real time elapsed on the host +sim_insts 61586372 # Number of instructions simulated +sim_ops 79276491 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4356148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 407360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5254000 # Number of bytes read from this memory -system.physmem.bytes_read::total 59186980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 407360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 816128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4265536 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory +system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7292880 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68137 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66649 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823485 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44611322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 373998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3985610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 372710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4807090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54152487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 373998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 372710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 746707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3902706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15554 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2754282 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6672542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3902706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44611322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 373998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 372710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7561372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60825028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257887 # Total number of read requests seen -system.physmem.writeReqs 823485 # Total number of write requests seen -system.physmem.cpureqs 281561 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400504768 # Total number of bytes read from memory -system.physmem.bytesWritten 52703040 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59186980 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7292880 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 99 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12576 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391078 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 390722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 391119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 391200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 390939 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51577 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51575 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51748 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51658 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51582 # Track writes on a per bank basis +system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257943 # Total number of read requests seen +system.physmem.writeReqs 823524 # Total number of write requests seen +system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508352 # Total number of bytes read from memory +system.physmem.bytesWritten 52705536 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1176096 # Number of times wr buffer was full causing retry -system.physmem.totGap 1092967540000 # Total gap between requests +system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry +system.physmem.totGap 1103051731500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162934 # Categorize read packet sizes +system.physmem.readPktSize::6 162990 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1932932 # categorize write packet sizes +system.physmem.writePktSize::2 2925445 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66649 # categorize write packet sizes +system.physmem.writePktSize::6 66688 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -152,31 +134,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12576 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 496879 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 431716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 387410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 401103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1104120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1111115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2162095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 27972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 13366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 13210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 31247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,291 +170,309 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 164150101325 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 197462743325 # Sum of mem lat for all requests -system.physmem.totBusLat 25031152000 # Total cycles spent in databus access -system.physmem.totBankLat 8281490000 # Total cycles spent in bank access -system.physmem.avgQLat 26231.33 # Average queueing delay per request -system.physmem.avgBankLat 1323.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31554.72 # Average memory access latency -system.physmem.avgRdBW 366.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 48.22 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 54.15 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.67 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 9.65 # Average write queue length over time -system.physmem.readRowHits 6229568 # Number of row buffer hits during reads -system.physmem.writeRowHits 789194 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.84 # Row buffer hit rate for writes -system.physmem.avgGap 154344.04 # Average gap between requests -system.l2c.replacements 72641 # number of replacements -system.l2c.tagsinuse 53795.283774 # Cycle average of tags in use -system.l2c.total_refs 1870380 # Total number of references to valid blocks. -system.l2c.sampled_refs 137779 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.575218 # Average number of references to valid blocks. +system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests +system.physmem.totBusLat 31289360000 # Total cycles spent in databus access +system.physmem.totBankLat 8541403750 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 267795677 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2632589947 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 294482820 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3488585424 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6685319684 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 703776 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 267795677 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2632589947 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294482820 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3488585424 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6685319684 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299167 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408113059 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2070313 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667167003 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082649542 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050139238 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25325633830 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26375773068 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458252297 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2070313 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 179992800833 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 193458422610 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036847 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017322 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837694 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821785 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769690 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.740072 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757902 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566946 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567998 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567522 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097132 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097132 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45607.808701 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49524.094644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46147.540349 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.041821 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10169.721546 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.776953 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10050.587597 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.573171 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10045.529858 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36996.983462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41317.080364 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39366.945281 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +663,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6012491 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4585363 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296577 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3765620 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2919015 # Number of BTB hits +system.cpu0.branchPred.lookups 6009414 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.517514 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 674578 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28863 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8918270 # DTB read hits -system.cpu0.dtb.read_misses 33761 # DTB read misses -system.cpu0.dtb.write_hits 5143475 # DTB write hits -system.cpu0.dtb.write_misses 6030 # DTB write misses +system.cpu0.dtb.read_hits 8911826 # DTB read hits +system.cpu0.dtb.read_misses 33481 # DTB read misses +system.cpu0.dtb.write_hits 5139826 # DTB write hits +system.cpu0.dtb.write_misses 6231 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2137 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1055 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 365 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 538 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8952031 # DTB read accesses -system.cpu0.dtb.write_accesses 5149505 # DTB write accesses +system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8945307 # DTB read accesses +system.cpu0.dtb.write_accesses 5146057 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14061745 # DTB hits -system.cpu0.dtb.misses 39791 # DTB misses -system.cpu0.dtb.accesses 14101536 # DTB accesses -system.cpu0.itb.inst_hits 4226389 # ITB inst hits -system.cpu0.itb.inst_misses 5148 # ITB inst misses +system.cpu0.dtb.hits 14051652 # DTB hits +system.cpu0.dtb.misses 39712 # DTB misses +system.cpu0.dtb.accesses 14091364 # DTB accesses +system.cpu0.itb.inst_hits 4224274 # ITB inst hits +system.cpu0.itb.inst_misses 5167 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,530 +703,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1370 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4231537 # ITB inst accesses -system.cpu0.itb.hits 4226389 # DTB hits -system.cpu0.itb.misses 5148 # DTB misses -system.cpu0.itb.accesses 4231537 # DTB accesses -system.cpu0.numCycles 67785734 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses +system.cpu0.itb.hits 4224274 # DTB hits +system.cpu0.itb.misses 5167 # DTB misses +system.cpu0.itb.accesses 4229441 # DTB accesses +system.cpu0.numCycles 67942321 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3593593 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7526717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460555 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 62547 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20715231 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 54522 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85492 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4224665 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 156872 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2292 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41263116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.003783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.384047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33743827 81.78% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 566856 1.37% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818944 1.98% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676218 1.64% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773991 1.88% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 560705 1.36% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670652 1.63% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352961 0.86% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098962 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41263116 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088698 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472813 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12272697 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20662299 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6831890 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510283 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 985947 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 936613 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64715 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40060631 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213244 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 985947 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12836550 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5831447 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12738222 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6726939 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2144011 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38954643 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2110 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 419770 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1235917 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39310777 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175935751 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175901847 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 33904 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30931608 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8379168 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411632 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370766 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5325827 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7663556 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5690026 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120184 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1252239 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36870649 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 896350 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37273811 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81085 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6313763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13211798 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257333 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41263116 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.903320 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.511259 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26116346 63.29% 63.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5727985 13.88% 77.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3164328 7.67% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471717 5.99% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2127646 5.16% 95.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 929575 2.25% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 487199 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 186194 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52126 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41263116 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25847 2.42% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842941 78.82% 81.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200262 18.72% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52409 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22347449 59.95% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46908 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9376305 25.16% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5450017 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37273811 # Type of FU issued -system.cpu0.iq.rate 0.549877 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069503 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028693 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116992528 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44088817 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34369527 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8360 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3860 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38286519 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307254 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued +system.cpu0.iq.rate 0.548322 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1385688 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2397 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13227 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 538655 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192760 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5477 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 985947 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4198442 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101973 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37885007 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 86572 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7663556 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5690026 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571892 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40888 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13227 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150955 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118096 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 269051 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36896358 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9233299 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377453 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118008 # number of nop insts executed -system.cpu0.iew.exec_refs 14636338 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4860481 # Number of branches executed -system.cpu0.iew.exec_stores 5403039 # Number of stores executed -system.cpu0.iew.exec_rate 0.544309 # Inst execution rate -system.cpu0.iew.wb_sent 36702505 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34373387 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18311880 # num instructions producing a value -system.cpu0.iew.wb_consumers 35235348 # num instructions consuming a value +system.cpu0.iew.exec_nop 118132 # number of nop insts executed +system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4859341 # Number of branches executed +system.cpu0.iew.exec_stores 5399659 # Number of stores executed +system.cpu0.iew.exec_rate 0.542775 # Inst execution rate +system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18308250 # num instructions producing a value +system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.507089 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519702 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6136748 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 639017 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232971 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40277169 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.776860 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.743491 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28628964 71.08% 71.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5718437 14.20% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1895078 4.71% 89.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 977858 2.43% 92.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 774389 1.92% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 507385 1.26% 95.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386799 0.96% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 213802 0.53% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1174457 2.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40277169 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23678178 # Number of instructions committed -system.cpu0.commit.committedOps 31289712 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23679897 # Number of instructions committed +system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11429239 # Number of memory references committed -system.cpu0.commit.loads 6277868 # Number of loads committed -system.cpu0.commit.membars 229666 # Number of memory barriers committed -system.cpu0.commit.branches 4244753 # Number of branches committed +system.cpu0.commit.refs 11426897 # Number of memory references committed +system.cpu0.commit.loads 6276438 # Number of loads committed +system.cpu0.commit.membars 229667 # Number of memory barriers committed +system.cpu0.commit.branches 4245099 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646281 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489273 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1174457 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489349 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75678018 # The number of ROB reads -system.cpu0.rob.rob_writes 75840987 # The number of ROB writes -system.cpu0.timesIdled 360810 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26522618 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2118110205 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23597436 # Number of Instructions Simulated -system.cpu0.committedOps 31208970 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23597436 # Number of Instructions Simulated -system.cpu0.cpi 2.872589 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.872589 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348118 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348118 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 172012852 # number of integer regfile reads -system.cpu0.int_regfile_writes 34120799 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3233 # number of floating regfile reads -system.cpu0.fp_regfile_writes 892 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13056447 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451188 # number of misc regfile writes -system.cpu0.icache.replacements 392549 # number of replacements -system.cpu0.icache.tagsinuse 511.079018 # Cycle average of tags in use -system.cpu0.icache.total_refs 3800627 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393061 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.669306 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6496390000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.079018 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998201 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998201 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3800627 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3800627 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3800627 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3800627 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3800627 # number of overall hits -system.cpu0.icache.overall_hits::total 3800627 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423907 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423907 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423907 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423907 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423907 # number of overall misses -system.cpu0.icache.overall_misses::total 423907 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5778558992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5778558992 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5778558992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5778558992 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5778558992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5778558992 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4224534 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4224534 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4224534 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4224534 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4224534 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4224534 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100344 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100344 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100344 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100344 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100344 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100344 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13631.666833 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13631.666833 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13631.666833 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13631.666833 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13631.666833 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3110 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75726635 # The number of ROB reads +system.cpu0.rob.rob_writes 75801988 # The number of ROB writes +system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23599155 # Number of Instructions Simulated +system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated +system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads +system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads +system.cpu0.fp_regfile_writes 966 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes +system.cpu0.icache.replacements 392744 # number of replacements +system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use +system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.016860 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998080 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998080 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3798516 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3798516 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3798516 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3798516 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3798516 # number of overall hits +system.cpu0.icache.overall_hits::total 3798516 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423935 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423935 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423935 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423935 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423935 # number of overall misses +system.cpu0.icache.overall_misses::total 423935 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803194996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5803194996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5803194996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5803194996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5803194996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.326797 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30826 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30826 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30826 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30826 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30826 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30826 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393081 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393081 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393081 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393081 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393081 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393081 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4722265492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4722265492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4722265492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4722265492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4722265492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4722265492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093047 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093047 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093047 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093047 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12013.466670 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12013.466670 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12013.466670 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276186 # number of replacements -system.cpu0.dcache.tagsinuse 460.207954 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9271152 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276698 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.506393 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.207954 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.898844 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.898844 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5791916 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5791916 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159128 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159128 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139197 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139197 # 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number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7503 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976708 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976708 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976708 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976708 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5419802000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5419802000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59847292371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59847292371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88405500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88405500 # 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miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059492 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051885 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051885 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180889 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180889 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180889 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180889 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13843.789352 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13843.789352 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37753.518220 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 37753.518220 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10040.374787 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10040.374787 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6229.241637 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6229.241637 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33018.075695 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33018.075695 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33018.075695 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8715 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3535 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 594 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.671717 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 42.590361 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275861 # number of replacements +system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8946853 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8946853 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8946853 # number of overall hits +system.cpu0.dcache.overall_hits::total 8946853 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 390976 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 390976 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582272 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582272 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1973248 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1973248 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1973248 # number of overall misses +system.cpu0.dcache.overall_misses::total 1973248 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5434487500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5434487500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60315071371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60315071371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88202500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88202500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46670000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46670000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65749558871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65749558871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65749558871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65749558871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176908 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176908 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147912 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147912 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144535 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144535 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920101 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920101 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920101 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920101 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063296 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063296 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333588 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333588 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059326 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059326 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051780 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6235.970069 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6235.970069 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33320.474097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33320.474097 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8364 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5666 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 593 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.104553 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256562 # number of writebacks -system.cpu0.dcache.writebacks::total 256562 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202833 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202833 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454685 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454685 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 458 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 458 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657518 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657518 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657518 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657518 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188664 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188664 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130526 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130526 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8347 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8347 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7503 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7503 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319190 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319190 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319190 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319190 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2355812500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2355812500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3979098490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3979098490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66495500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66495500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31732000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31732000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6334910990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6334910990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6334910990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6334910990 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128583377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128583377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14633094877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14633094877 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027512 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027512 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056398 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051885 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051885 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029209 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12486.815185 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12486.815185 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30485.102508 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30485.102508 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7966.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7966.395112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4229.241637 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4229.241637 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19846.834143 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19846.834143 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks +system.cpu0.dcache.writebacks::total 256398 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1234,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781590 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7165099 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 410272 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5784510 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4949628 # Number of BTB hits +system.cpu1.branchPred.lookups 9060826 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.566937 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 773605 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42847 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42721233 # DTB read hits -system.cpu1.dtb.read_misses 41267 # DTB read misses -system.cpu1.dtb.write_hits 6827437 # DTB write hits -system.cpu1.dtb.write_misses 11457 # DTB write misses +system.cpu1.dtb.read_hits 42893856 # DTB read hits +system.cpu1.dtb.read_misses 41286 # DTB read misses +system.cpu1.dtb.write_hits 6825448 # DTB write hits +system.cpu1.dtb.write_misses 11345 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2301 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2630 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42762500 # DTB read accesses -system.cpu1.dtb.write_accesses 6838894 # DTB write accesses +system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42935142 # DTB read accesses +system.cpu1.dtb.write_accesses 6836793 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49548670 # DTB hits -system.cpu1.dtb.misses 52724 # DTB misses -system.cpu1.dtb.accesses 49601394 # DTB accesses -system.cpu1.itb.inst_hits 7583980 # ITB inst hits -system.cpu1.itb.inst_misses 5601 # ITB inst misses +system.cpu1.dtb.hits 49719304 # DTB hits +system.cpu1.dtb.misses 52631 # DTB misses +system.cpu1.dtb.accesses 49771935 # DTB accesses +system.cpu1.itb.inst_hits 8340296 # ITB inst hits +system.cpu1.itb.inst_misses 5581 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1274,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1561 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1591 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7589581 # ITB inst accesses -system.cpu1.itb.hits 7583980 # DTB hits -system.cpu1.itb.misses 5601 # DTB misses -system.cpu1.itb.accesses 7589581 # DTB accesses -system.cpu1.numCycles 406854445 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses +system.cpu1.itb.hits 8340296 # DTB hits +system.cpu1.itb.misses 5581 # DTB misses +system.cpu1.itb.accesses 8345877 # DTB accesses +system.cpu1.numCycles 408908787 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5723233 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13164545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3370379 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 67214 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77426772 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4687 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46358 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129737 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 707 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7581976 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 531329 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3060 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 112134243 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.659620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.988948 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 98977030 88.27% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796888 0.71% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939707 0.84% 89.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1694875 1.51% 91.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1403619 1.25% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 573280 0.51% 93.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1928107 1.72% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410374 0.37% 95.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5410363 4.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 112134243 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021584 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.148737 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20329334 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77067438 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11999240 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 528326 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2209905 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105816 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98089 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69983071 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327113 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2209905 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21512186 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32033439 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40715711 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11249430 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4413572 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 66189803 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19593 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681290 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3157378 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32035 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69538015 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 303909752 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 303850528 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59224 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49060717 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20477298 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445152 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388313 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7961235 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12608499 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7947542 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1037744 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1535939 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60784720 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1155099 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87803920 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 97322 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13491429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36062520 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274254 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 112134243 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783025 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519999 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 82080142 73.20% 73.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8453890 7.54% 80.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4228870 3.77% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3673146 3.28% 87.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10396618 9.27% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1923791 1.72% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1051838 0.94% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 251187 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 74761 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 112134243 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29715 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,395 +1409,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547628 96.04% 96.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 280810 3.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36673483 41.77% 42.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59172 0.07% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1514 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43579800 49.63% 91.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7175925 8.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87803920 # Type of FU issued -system.cpu1.iq.rate 0.215812 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7859149 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089508 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 295735701 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75439999 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53226631 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15376 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8066 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6868 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95340871 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8201 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343143 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued +system.cpu1.iq.rate 0.217753 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2852269 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3976 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17384 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1106708 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919671 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 693087 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2209905 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24121244 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 365124 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 62044608 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111941 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12608499 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7947542 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865588 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 68372 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3578 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17384 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203207 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155936 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 359143 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86098386 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43091016 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1705534 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104789 # number of nop insts executed -system.cpu1.iew.exec_refs 50204478 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6908033 # Number of branches executed -system.cpu1.iew.exec_stores 7113462 # Number of stores executed -system.cpu1.iew.exec_rate 0.211620 # Inst execution rate -system.cpu1.iew.wb_sent 85323128 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53233499 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29734399 # num instructions producing a value -system.cpu1.iew.wb_consumers 53052149 # num instructions consuming a value +system.cpu1.iew.exec_nop 103808 # number of nop insts executed +system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6998395 # Number of branches executed +system.cpu1.iew.exec_stores 7111224 # Number of stores executed +system.cpu1.iew.exec_rate 0.211923 # Inst execution rate +system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29896757 # num instructions producing a value +system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130842 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560475 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13410332 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880845 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313641 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 109924338 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.438116 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.408415 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 93165965 84.75% 84.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8233685 7.49% 92.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2134554 1.94% 94.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255111 1.14% 95.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1238932 1.13% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 576271 0.52% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 972518 0.88% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 559108 0.51% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1788194 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 109924338 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38068175 # Number of instructions committed -system.cpu1.commit.committedOps 48159625 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38056856 # Number of instructions committed +system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16597064 # Number of memory references committed -system.cpu1.commit.loads 9756230 # Number of loads committed -system.cpu1.commit.membars 190160 # Number of memory barriers committed -system.cpu1.commit.branches 5968166 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42694155 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534687 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1788194 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16587832 # Number of memory references committed +system.cpu1.commit.loads 9751176 # Number of loads committed +system.cpu1.commit.membars 190071 # Number of memory barriers committed +system.cpu1.commit.branches 5966416 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534458 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 168661953 # The number of ROB reads -system.cpu1.rob.rob_writes 125442140 # The number of ROB writes -system.cpu1.timesIdled 1407356 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294720202 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1778443945 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37998536 # Number of Instructions Simulated -system.cpu1.committedOps 48089986 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37998536 # Number of Instructions Simulated -system.cpu1.cpi 10.707108 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.707108 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093396 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093396 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 385381686 # number of integer regfile reads -system.cpu1.int_regfile_writes 55406618 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18496665 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405533 # number of misc regfile writes -system.cpu1.icache.replacements 597187 # number of replacements -system.cpu1.icache.tagsinuse 480.515152 # Cycle average of tags in use -system.cpu1.icache.total_refs 6939274 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597699 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.609981 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74121232000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.515152 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938506 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938506 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6939274 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6939274 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6939274 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6939274 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6939274 # number of overall hits -system.cpu1.icache.overall_hits::total 6939274 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642651 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642651 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642651 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642651 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642651 # number of overall misses -system.cpu1.icache.overall_misses::total 642651 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8610286993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8610286993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8610286993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8610286993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8610286993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8610286993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7581925 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7581925 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7581925 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7581925 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7581925 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7581925 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084761 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084761 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13448.296562 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13448.296562 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.069767 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 753 # average number of cycles each access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078835 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078835 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078835 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078835 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11791.226375 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11791.226375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11791.226375 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44386 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44386 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44386 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44386 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44386 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44386 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597612 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597612 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597612 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597612 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597612 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597612 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # 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average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35730.322318 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35730.322318 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35730.322318 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 26431 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 15171 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 158 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.193118 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 96.018987 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360159 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324726 # number of writebacks -system.cpu1.dcache.writebacks::total 324726 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169327 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169327 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393847 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1393847 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1563174 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1563174 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1563174 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1563174 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228328 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228328 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161561 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161561 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12488 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12488 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389889 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389889 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389889 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389889 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2825835000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2825835000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5223945209 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5223945209 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87441500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87441500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32536500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32536500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8049780209 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8049780209 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8049780209 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8049780209 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168995979000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168995979000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27123329043 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27123329043 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196119308043 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196119308043 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026204 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026204 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111988 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111988 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100531 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100531 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027055 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027055 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027055 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.208787 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12376.208787 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32334.197046 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32334.197046 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7002.041960 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7002.041960 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3067.455454 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3067.455454 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20646.338340 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20646.338340 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks +system.cpu1.dcache.writebacks::total 324224 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100478 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100478 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027036 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027036 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.872831 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12480.872831 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31870.928453 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31870.928453 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1819,18 +1819,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 497798121418 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 497798121418 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 497798121418 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 497798121418 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41715 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 80b8abc3e..406114ee2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,126 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523205 # Number of seconds simulated -sim_ticks 2523204701000 # Number of ticks simulated -final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533245 # Number of seconds simulated +sim_ticks 2533245380500 # Number of ticks simulated +final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50114 # Simulator instruction rate (inst/s) -host_op_rate 64483 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2096764175 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 1203.38 # Real time elapsed on the host -sim_insts 60306320 # Number of instructions simulated -sim_ops 77597310 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 67317 # Simulator instruction rate (inst/s) +host_op_rate 86618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2827634962 # Simulator tick rate (ticks/s) +host_mem_usage 409784 # Number of bytes of host memory used +host_seconds 895.89 # Real time elapsed on the host +sim_insts 60308251 # Number of instructions simulated +sim_ops 77599937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096856 # Total number of read requests seen -system.physmem.writeReqs 813138 # Total number of write requests seen -system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198784 # Total number of bytes read from memory -system.physmem.bytesWritten 52040832 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis +system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096850 # Total number of read requests seen +system.physmem.writeReqs 813145 # Total number of write requests seen +system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198400 # Total number of bytes read from memory +system.physmem.bytesWritten 52041280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523203522000 # Total gap between requests +system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533244279000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154612 # Categorize read packet sizes +system.physmem.readPktSize::6 154606 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1943854 # categorize write packet sizes +system.physmem.writePktSize::2 2927056 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59120 # categorize write packet sizes +system.physmem.writePktSize::6 59127 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,30 +117,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -184,79 +172,91 @@ system.physmem.wrQLenPdf::15 35354 # Wh system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests -system.physmem.totBusLat 60386192000 # Total cycles spent in databus access -system.physmem.totBankLat 16356620000 # Total cycles spent in bank access -system.physmem.avgQLat 21743.10 # Average queueing delay per request -system.physmem.avgBankLat 1083.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26826.57 # Average memory access latency -system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 10.68 # Average write queue length over time -system.physmem.readRowHits 15052450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784654 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes -system.physmem.avgGap 158592.36 # Average gap between requests +system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests +system.physmem.totBusLat 75482595000 # Total cycles spent in databus access +system.physmem.totBankLat 16916941250 # Total cycles spent in bank access +system.physmem.avgQLat 26034.38 # Average queueing delay per request +system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32154.97 # Average memory access latency +system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 15020214 # Number of row buffer hits during reads +system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes +system.physmem.avgGap 159223.45 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14400111 # Number of BP lookups -system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits +system.cpu.branchPred.lookups 14667589 # Number of BP lookups +system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51212683 # DTB read hits -system.cpu.dtb.read_misses 73387 # DTB read misses -system.cpu.dtb.write_hits 11701466 # DTB write hits -system.cpu.dtb.write_misses 17011 # DTB write misses +system.cpu.dtb.read_hits 51389080 # DTB read hits +system.cpu.dtb.read_misses 73326 # DTB read misses +system.cpu.dtb.write_hits 11702658 # DTB write hits +system.cpu.dtb.write_misses 17128 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51286070 # DTB read accesses -system.cpu.dtb.write_accesses 11718477 # DTB write accesses +system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51462406 # DTB read accesses +system.cpu.dtb.write_accesses 11719786 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62914149 # DTB hits -system.cpu.dtb.misses 90398 # DTB misses -system.cpu.dtb.accesses 63004547 # DTB accesses -system.cpu.itb.inst_hits 11530598 # ITB inst hits -system.cpu.itb.inst_misses 11503 # ITB inst misses +system.cpu.dtb.hits 63091738 # DTB hits +system.cpu.dtb.misses 90454 # DTB misses +system.cpu.dtb.accesses 63182192 # DTB accesses +system.cpu.itb.inst_hits 12277036 # ITB inst hits +system.cpu.itb.inst_misses 11490 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -265,114 +265,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2585 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11542101 # ITB inst accesses -system.cpu.itb.hits 11530598 # DTB hits -system.cpu.itb.misses 11503 # DTB misses -system.cpu.itb.accesses 11542101 # DTB accesses -system.cpu.numCycles 469830472 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12288526 # ITB inst accesses +system.cpu.itb.hits 12277036 # DTB hits +system.cpu.itb.misses 11490 # DTB misses +system.cpu.itb.accesses 12288526 # DTB accesses +system.cpu.numCycles 472097236 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -400,383 +400,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued -system.cpu.iq.rate 0.261848 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued +system.cpu.iq.rate 0.263176 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221038 # number of nop insts executed -system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed -system.cpu.iew.exec_branches 11477980 # Number of branches executed -system.cpu.iew.exec_stores 12213052 # Number of stores executed -system.cpu.iew.exec_rate 0.257448 # Inst execution rate -system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47051195 # num instructions producing a value -system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value +system.cpu.iew.exec_nop 220577 # number of nop insts executed +system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed +system.cpu.iew.exec_branches 11563754 # Number of branches executed +system.cpu.iew.exec_stores 12214366 # Number of stores executed +system.cpu.iew.exec_rate 0.257379 # Inst execution rate +system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47207424 # num instructions producing a value +system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456701 # Number of instructions committed -system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458632 # Number of instructions committed +system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385892 # Number of memory references committed -system.cpu.commit.loads 15654083 # Number of loads committed -system.cpu.commit.membars 403583 # Number of memory barriers committed -system.cpu.commit.branches 9961154 # Number of branches committed +system.cpu.commit.refs 27386920 # Number of memory references committed +system.cpu.commit.loads 15654712 # Number of loads committed +system.cpu.commit.membars 403607 # Number of memory barriers committed +system.cpu.commit.branches 9961406 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. -system.cpu.commit.function_calls 991222 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. +system.cpu.commit.function_calls 991273 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 238273902 # The number of ROB reads -system.cpu.rob.rob_writes 196332947 # The number of ROB writes -system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60306320 # Number of Instructions Simulated -system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated -system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547824485 # number of integer regfile reads -system.cpu.int_regfile_writes 87698031 # number of integer regfile writes -system.cpu.fp_regfile_reads 8340 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads -system.cpu.misc_regfile_writes 831851 # number of misc regfile writes -system.cpu.icache.replacements 979772 # number of replacements -system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use -system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits -system.cpu.icache.overall_hits::total 10466836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses -system.cpu.icache.overall_misses::total 1059904 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.rob.rob_reads 242460133 # The number of ROB reads +system.cpu.rob.rob_writes 201635862 # The number of ROB writes +system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60308251 # Number of Instructions Simulated +system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated +system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550197994 # number of integer regfile reads +system.cpu.int_regfile_writes 88410647 # number of integer regfile writes +system.cpu.fp_regfile_reads 8198 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads +system.cpu.misc_regfile_writes 831902 # number of misc regfile writes +system.cpu.icache.replacements 980802 # number of replacements +system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use +system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits +system.cpu.icache.overall_hits::total 11213050 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses +system.cpu.icache.overall_misses::total 1060138 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # 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number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # 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mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -897,161 +897,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643386 # number of replacements -system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use -system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243031 # 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miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks -system.cpu.dcache.writebacks::total 607596 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks +system.cpu.dcache.writebacks::total 607265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,16 +1073,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8a66caa53..49d5a4463 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,148 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401290 # Number of seconds simulated -sim_ticks 2401290348000 # Number of ticks simulated -final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401347 # Number of seconds simulated +sim_ticks 2401347058000 # Number of ticks simulated +final_tick 2401347058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145439 # Simulator instruction rate (inst/s) -host_op_rate 186799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5788935854 # Simulator tick rate (ticks/s) -host_mem_usage 444568 # Number of bytes of host memory used -host_seconds 414.81 # Real time elapsed on the host -sim_insts 60329082 # Number of instructions simulated -sim_ops 77485321 # Number of ops (including micro ops) simulated +host_inst_rate 247220 # Simulator instruction rate (inst/s) +host_op_rate 317493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9839599535 # Simulator tick rate (ticks/s) +host_mem_usage 400552 # Number of bytes of host memory used +host_seconds 244.05 # Real time elapsed on the host +sim_insts 60333921 # Number of instructions simulated +sim_ops 77484019 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 486624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7022480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 501472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7131280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 77504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 723200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 203648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1332732 # Number of bytes read from this memory -system.physmem.bytes_read::total 124666476 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 486624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 77504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 203648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 767776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3747584 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1052224 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 85632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 677504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1269180 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 501472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746368 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1495356 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1764136 # Number of bytes written to this memory -system.physmem.bytes_written::total 6763400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1321004 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13806 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 109760 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111460 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11300 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20838 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512500 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58556 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 263056 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512426 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58537 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 373839 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 441034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812510 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47815572 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 330251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812491 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 202651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2924461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 208829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2969700 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 301171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 84808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 555007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51916452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 202651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 84808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560654 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 438191 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83062 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 734662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816569 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47815572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 528528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560111 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 622715 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 550110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814443 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 202651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3362652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3592415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 384233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 84808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1289668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54733021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12619459 # Total number of read requests seen -system.physmem.writeReqs 508288 # Total number of write requests seen -system.physmem.cpureqs 56279 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807645376 # Total number of bytes read from memory -system.physmem.bytesWritten 32530432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 103001404 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 3076552 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 788367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 788430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 788204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 789073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 789810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 789739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 789543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 789483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788174 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788123 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 30454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 30491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 30890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 31526 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 31443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 31484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 31752 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 32161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 32686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 32676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 32416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 32334 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 31816 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 31518 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 32440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 32201 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 35660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1078638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54729250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617453 # Total number of read requests seen +system.physmem.writeReqs 397526 # Total number of write requests seen +system.physmem.cpureqs 54288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807516992 # Total number of bytes read from memory +system.physmem.bytesWritten 25441664 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102873020 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2634764 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789011 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 787997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788698 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24781 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24852 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 25063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25236 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 24651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25132 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 316906 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400255112000 # Total gap between requests +system.physmem.numWrRetry 749984 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400311882000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 36532 # Categorize read packet sizes +system.physmem.readPktSize::6 34526 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 807804 # categorize write packet sizes +system.physmem.writePktSize::2 1130099 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 17390 # categorize write packet sizes +system.physmem.writePktSize::6 17411 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -151,26 +151,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2357 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2351 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 817349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 786840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 815906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2309875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2310166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4565473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24626 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 24600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 47884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 47866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 815640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 791627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -187,60 +187,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 22104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 22101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 22095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 22093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 22091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 22082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 22071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 22068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 22063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 22058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 22054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 22052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 13934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13913 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 234677385926 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 297433333926 # Sum of mem lat for all requests -system.physmem.totBusLat 50477836000 # Total cycles spent in databus access -system.physmem.totBankLat 12278112000 # Total cycles spent in bank access -system.physmem.avgQLat 18596.47 # Average queueing delay per request -system.physmem.avgBankLat 972.95 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23569.42 # Average memory access latency -system.physmem.avgRdBW 336.34 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 13.55 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.12 # Average read queue length over time +system.physmem.totQLat 277194471582 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353012127832 # Sum of mem lat for all requests +system.physmem.totBusLat 63087260000 # Total cycles spent in databus access +system.physmem.totBankLat 12730396250 # Total cycles spent in bank access +system.physmem.avgQLat 21969.13 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018136 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018242 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005957 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992079 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505786 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.335210 # 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average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -686,436 +683,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7853690 # DTB read hits -system.cpu0.dtb.read_misses 6243 # DTB read misses -system.cpu0.dtb.write_hits 6487171 # DTB write hits -system.cpu0.dtb.write_misses 1921 # DTB write misses +system.cpu0.dtb.read_hits 8069329 # DTB read hits +system.cpu0.dtb.read_misses 6237 # DTB read misses +system.cpu0.dtb.write_hits 6635324 # DTB write hits +system.cpu0.dtb.write_misses 2059 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5670 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5724 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7859933 # DTB read accesses -system.cpu0.dtb.write_accesses 6489092 # DTB write accesses +system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8075566 # DTB read accesses +system.cpu0.dtb.write_accesses 6637383 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14340861 # DTB hits -system.cpu0.dtb.misses 8164 # DTB misses -system.cpu0.dtb.accesses 14349025 # DTB accesses -system.cpu0.itb.inst_hits 31512097 # ITB inst hits -system.cpu0.itb.inst_misses 3518 # ITB inst misses +system.cpu0.dtb.hits 14704653 # DTB hits +system.cpu0.dtb.misses 8296 # DTB misses +system.cpu0.dtb.accesses 14712949 # DTB accesses +system.cpu0.itb.inst_hits 32681523 # ITB inst hits +system.cpu0.itb.inst_misses 3486 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 31515615 # ITB inst accesses -system.cpu0.itb.hits 31512097 # DTB hits -system.cpu0.itb.misses 3518 # DTB misses -system.cpu0.itb.accesses 31515615 # DTB accesses -system.cpu0.numCycles 112564012 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32685009 # ITB inst accesses +system.cpu0.itb.hits 32681523 # DTB hits +system.cpu0.itb.misses 3486 # DTB misses +system.cpu0.itb.accesses 32685009 # DTB accesses +system.cpu0.numCycles 114009309 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31022111 # Number of instructions committed -system.cpu0.committedOps 41078367 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 36251649 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses -system.cpu0.num_func_calls 1198861 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4217068 # number of instructions that are conditional controls -system.cpu0.num_int_insts 36251649 # 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Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37541413 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5201 # Number of float alu accesses +system.cpu0.num_func_calls 1186772 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4235639 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37541413 # number of integer instructions +system.cpu0.num_fp_insts 5201 # number of float instructions +system.cpu0.num_int_register_reads 191262498 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39620034 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3719 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1484 # number of times the floating registers were written +system.cpu0.num_mem_refs 15366811 # number of memory refs +system.cpu0.num_load_insts 8436504 # Number of load instructions +system.cpu0.num_store_insts 6930307 # Number of store instructions +system.cpu0.num_idle_cycles 13418269361.007845 # Number of idle cycles +system.cpu0.num_busy_cycles -13304260052.007845 # Number of busy cycles +system.cpu0.not_idle_fraction -116.694507 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.694507 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892592 # number of replacements -system.cpu0.icache.tagsinuse 511.602515 # Cycle average of tags in use -system.cpu0.icache.total_refs 43093947 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 893104 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 48.251880 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8108198000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 496.911233 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 7.172611 # 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number of replacements +system.cpu0.dcache.replacements 629918 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23260459 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630529 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.890387 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23229670 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630430 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.847342 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 497.365080 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 8.139667 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.492369 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.971416 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.015898 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012680 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.731477 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.808064 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.457575 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968226 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.019156 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012612 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6715363 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1862593 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4768116 # 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number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1294158 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 357078 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 87960 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 849120 # number of overall misses -system.cpu0.dcache.overall_misses::total 1294158 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 815877500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3620904500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4436782000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 748178500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18896011913 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19644190413 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 21031500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51388500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 72420000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 115000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 115000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1564056000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22516916413 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24080972413 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1564056000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22516916413 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24080972413 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6904705 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1920833 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5024130 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13849668 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6086016 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1392055 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2738280 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216351 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34552 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77940 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250178 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137686 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34552 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 75158 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12990721 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3312888 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7762410 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24066019 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12990721 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3312888 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7762410 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24066019 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027422 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030320 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.050957 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036362 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027561 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021350 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216598 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077382 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047536 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046539 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.049025 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047862 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027487 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026551 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.109389 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.053775 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027487 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026551 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.109389 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.053775 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14008.885646 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14143.384737 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8810.201034 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25174.242934 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31859.417900 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24848.386860 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13079.291045 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13448.966239 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6048.104226 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16428.571429 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16428.571429 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17781.446112 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26517.943769 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18607.443923 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17781.446112 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26517.943769 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18607.443923 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6254 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1492 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13243403 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3362131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7435697 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24041231 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13243403 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3362131 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7435697 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24041231 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023846 # 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average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 76.955556 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597807 # number of writebacks -system.cpu0.dcache.writebacks::total 597807 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 131637 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 131637 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 540605 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 540605 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 422 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 422 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 672242 # 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011005 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12008.885646 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12899.097100 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12615.191904 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23174.242934 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27664.072913 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26041.157271 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11079.291045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11643.865843 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11462.552427 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14428.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14428.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15781.446112 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17281.643234 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.386417 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597795 # number of writebacks +system.cpu0.dcache.writebacks::total 597795 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4615431991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27472084500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29005064000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56477148500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280597500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13851108534 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15131706034 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28752682000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42856172534 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71608854534 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032878 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014620 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021165 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019298 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044724 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020706 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11954.531478 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12995.622802 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12660.583617 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22682.982211 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26629.640793 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25212.557818 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.619572 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11591.486291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11424.884438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1128,388 +1125,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2135190 # DTB read hits -system.cpu1.dtb.read_misses 2107 # DTB read misses -system.cpu1.dtb.write_hits 1477401 # DTB write hits -system.cpu1.dtb.write_misses 382 # DTB write misses +system.cpu1.dtb.read_hits 2193182 # DTB read hits +system.cpu1.dtb.read_misses 2113 # DTB read misses +system.cpu1.dtb.write_hits 1470431 # DTB write hits +system.cpu1.dtb.write_misses 386 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1694 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1737 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2137297 # DTB read accesses -system.cpu1.dtb.write_accesses 1477783 # DTB write accesses +system.cpu1.dtb.perms_faults 73 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2195295 # DTB read accesses +system.cpu1.dtb.write_accesses 1470817 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3612591 # DTB hits -system.cpu1.dtb.misses 2489 # DTB misses -system.cpu1.dtb.accesses 3615080 # DTB accesses -system.cpu1.itb.inst_hits 8526904 # ITB inst hits -system.cpu1.itb.inst_misses 1128 # ITB inst misses +system.cpu1.dtb.hits 3663613 # DTB hits +system.cpu1.dtb.misses 2499 # DTB misses +system.cpu1.dtb.accesses 3666112 # DTB accesses +system.cpu1.itb.inst_hits 8542569 # ITB inst hits +system.cpu1.itb.inst_misses 1142 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 843 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8528032 # ITB inst accesses -system.cpu1.itb.hits 8526904 # DTB hits -system.cpu1.itb.misses 1128 # DTB misses -system.cpu1.itb.accesses 8528032 # DTB accesses -system.cpu1.numCycles 573624739 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8543711 # ITB inst accesses +system.cpu1.itb.hits 8542569 # DTB hits +system.cpu1.itb.misses 1142 # DTB misses +system.cpu1.itb.accesses 8543711 # DTB accesses +system.cpu1.numCycles 574622770 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8322298 # Number of instructions committed -system.cpu1.committedOps 10507258 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9429869 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 301953 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1117858 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9429869 # number of integer instructions -system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54131389 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10251114 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3780360 # number of memory refs -system.cpu1.num_load_insts 2226594 # Number of load instructions -system.cpu1.num_store_insts 1553766 # Number of store instructions -system.cpu1.num_idle_cycles -28509606.904042 # Number of idle cycles -system.cpu1.num_busy_cycles 602134345.904042 # Number of busy cycles -system.cpu1.not_idle_fraction 1.049701 # Percentage of non-idle cycles -system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles +system.cpu1.committedInsts 8323313 # Number of instructions committed +system.cpu1.committedOps 10568521 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9455667 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses +system.cpu1.num_func_calls 319891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1162179 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9455667 # number of integer instructions +system.cpu1.num_fp_insts 2078 # number of float instructions +system.cpu1.num_int_register_reads 54536858 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10267786 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3838385 # number of memory refs +system.cpu1.num_load_insts 2289184 # Number of load instructions +system.cpu1.num_store_insts 1549201 # Number of store instructions +system.cpu1.num_idle_cycles 539990839.742371 # Number of idle cycles +system.cpu1.num_busy_cycles 34631930.257629 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060269 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939731 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4714679 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3830081 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 228509 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3129435 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2502665 # Number of BTB hits +system.cpu2.branchPred.lookups 4693263 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3812182 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221977 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3118720 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2512857 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.971784 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 416919 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 22256 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.573344 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412180 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21663 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 11094758 # DTB read hits -system.cpu2.dtb.read_misses 26972 # DTB read misses -system.cpu2.dtb.write_hits 3400244 # DTB write hits -system.cpu2.dtb.write_misses 7099 # DTB write misses +system.cpu2.dtb.read_hits 10844301 # DTB read hits +system.cpu2.dtb.read_misses 26001 # DTB read misses +system.cpu2.dtb.write_hits 3253591 # DTB write hits +system.cpu2.dtb.write_misses 6154 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 3080 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 201 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 3046 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 424 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 11121730 # DTB read accesses -system.cpu2.dtb.write_accesses 3407343 # DTB write accesses +system.cpu2.dtb.perms_faults 434 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10870302 # DTB read accesses +system.cpu2.dtb.write_accesses 3259745 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14495002 # DTB hits -system.cpu2.dtb.misses 34071 # DTB misses -system.cpu2.dtb.accesses 14529073 # DTB accesses -system.cpu2.itb.inst_hits 3971406 # ITB inst hits -system.cpu2.itb.inst_misses 4850 # ITB inst misses +system.cpu2.dtb.hits 14097892 # DTB hits +system.cpu2.dtb.misses 32155 # DTB misses +system.cpu2.dtb.accesses 14130047 # DTB accesses +system.cpu2.itb.inst_hits 4034633 # ITB inst hits +system.cpu2.itb.inst_misses 4571 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1620 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1033 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 986 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3976256 # ITB inst accesses -system.cpu2.itb.hits 3971406 # DTB hits -system.cpu2.itb.misses 4850 # DTB misses -system.cpu2.itb.accesses 3976256 # DTB accesses -system.cpu2.numCycles 88220053 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4039204 # ITB inst accesses +system.cpu2.itb.hits 4034633 # DTB hits +system.cpu2.itb.misses 4571 # DTB misses +system.cpu2.itb.accesses 4039204 # DTB accesses +system.cpu2.numCycles 88320298 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2919584 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6810047 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1714054 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 54378 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19370743 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 384 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 766 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 36586 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 56559 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 314 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3969766 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 243007 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2358 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36954315 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.048838 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.435241 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9410725 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32093241 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4693263 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2925037 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6776745 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1793565 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51693 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19502883 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 35787 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57273 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4033217 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 303741 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2092 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37067906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.039760 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.425875 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30149445 81.59% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 388045 1.05% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515673 1.40% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 809442 2.19% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 613859 1.66% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342479 0.93% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1057115 2.86% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 225211 0.61% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2853046 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30296325 81.73% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382563 1.03% 82.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 507321 1.37% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 805393 2.17% 86.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 652342 1.76% 88.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 346651 0.94% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 996850 2.69% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 239087 0.64% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2841374 7.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36954315 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053442 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.364670 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9982984 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19336478 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6240183 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 267118 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1126648 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608561 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 54769 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36760882 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 185685 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1126648 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10483708 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6549966 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11350548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5986699 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1455863 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35043442 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2820 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 275900 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 915207 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 16681 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37480121 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160397903 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 160370485 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27418 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 27101892 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10378228 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 234776 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 210973 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3167835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6643625 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3930476 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 536055 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 848060 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32398169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511180 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35261741 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 57711 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6815727 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 17611211 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 150093 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36954315 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.954198 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.610437 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37067906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053139 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.363373 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10025306 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19435128 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6133360 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293839 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1179201 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610191 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53369 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36416807 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180085 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1179201 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10595473 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6672537 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11193536 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5837719 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1588398 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34213134 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2954 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 427229 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 898663 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 11044 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36672264 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 156364458 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 156337893 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26565 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25643428 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11028835 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232388 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208734 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3368643 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6480999 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3820565 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 539245 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 769553 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31495381 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 514788 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34101978 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55239 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7293710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19517466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 157489 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37067906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.919987 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.574944 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24234818 65.58% 65.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3845219 10.41% 75.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2339985 6.33% 82.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2011458 5.44% 87.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2820235 7.63% 95.39% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1010729 2.74% 98.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 509292 1.38% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 148791 0.40% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 33788 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24513061 66.13% 66.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3940276 10.63% 76.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2351629 6.34% 83.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1969211 5.31% 88.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2763009 7.45% 95.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 888704 2.40% 98.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 473497 1.28% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133879 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34640 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36954315 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37067906 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16803 1.09% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1412351 91.83% 92.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 108917 7.08% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16450 1.07% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1406460 91.72% 92.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110474 7.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 60938 0.17% 0.17% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20064817 56.90% 57.08% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28831 0.08% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 373 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11537749 32.72% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3569015 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61347 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19254237 56.46% 56.64% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25603 0.08% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 363 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.72% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11339596 33.25% 89.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3420808 10.03% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35261741 # Type of FU issued -system.cpu2.iq.rate 0.399702 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1538071 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043619 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 109100819 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39730950 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28646602 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6706 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3736 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3123 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36735375 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3499 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200241 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34101978 # Type of FU issued +system.cpu2.iq.rate 0.386117 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1533384 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044965 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106886012 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39309169 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27255453 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6518 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3637 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3015 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35570601 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3414 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207005 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1445664 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1895 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9919 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 541092 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1561439 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9237 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 573725 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5363616 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 332725 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5369512 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 345439 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1126648 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4836519 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87210 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32990358 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 63317 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6643625 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3930476 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 365793 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29718 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2499 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9919 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 109460 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 91793 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 201253 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 34488012 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11310897 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 773729 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1179201 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4914537 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 93208 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32084127 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61095 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6480999 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3820565 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 371831 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 32634 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9237 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106581 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88238 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194819 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33130261 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11055368 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 971717 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81009 # number of nop insts executed -system.cpu2.iew.exec_refs 14846360 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3721674 # Number of branches executed -system.cpu2.iew.exec_stores 3535463 # Number of stores executed -system.cpu2.iew.exec_rate 0.390932 # Inst execution rate -system.cpu2.iew.wb_sent 34107524 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28649725 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16504855 # num instructions producing a value -system.cpu2.iew.wb_consumers 29777909 # num instructions consuming a value +system.cpu2.iew.exec_nop 73958 # number of nop insts executed +system.cpu2.iew.exec_refs 14443007 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3675866 # Number of branches executed +system.cpu2.iew.exec_stores 3387639 # Number of stores executed +system.cpu2.iew.exec_rate 0.375115 # Inst execution rate +system.cpu2.iew.wb_sent 32719575 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27258468 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15578435 # num instructions producing a value +system.cpu2.iew.wb_consumers 28336805 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.324753 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.554265 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.308632 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549760 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 6780603 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 361087 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 174485 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35827443 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.724416 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.779563 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7236388 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357299 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169355 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35888560 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.684756 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.712853 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 26972703 75.29% 75.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4272213 11.92% 87.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1247843 3.48% 90.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 631329 1.76% 92.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 544091 1.52% 93.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 320362 0.89% 94.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 435465 1.22% 96.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 326356 0.91% 96.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1077081 3.01% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27290790 76.04% 76.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4165435 11.61% 87.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1253109 3.49% 91.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 644489 1.80% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 571851 1.59% 94.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 314297 0.88% 95.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 396110 1.10% 96.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 285595 0.80% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 966884 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35827443 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 21038967 # Number of instructions committed -system.cpu2.commit.committedOps 25953990 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35888560 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19876644 # Number of instructions committed +system.cpu2.commit.committedOps 24574906 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8587345 # Number of memory references committed -system.cpu2.commit.loads 5197961 # Number of loads committed -system.cpu2.commit.membars 96306 # Number of memory barriers committed -system.cpu2.commit.branches 3207336 # Number of branches committed -system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23136134 # Number of committed integer instructions. -system.cpu2.commit.function_calls 296648 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1077081 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8166400 # Number of memory references committed +system.cpu2.commit.loads 4919560 # Number of loads committed +system.cpu2.commit.membars 94646 # Number of memory barriers committed +system.cpu2.commit.branches 3146883 # Number of branches committed +system.cpu2.commit.fp_insts 2975 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21821277 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294032 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 966884 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66956650 # The number of ROB reads -system.cpu2.rob.rob_writes 66650908 # The number of ROB writes -system.cpu2.timesIdled 359376 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51265738 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3569532047 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20984673 # Number of Instructions Simulated -system.cpu2.committedOps 25899696 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20984673 # Number of Instructions Simulated -system.cpu2.cpi 4.204023 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.204023 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.237867 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.237867 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 160070437 # number of integer regfile reads -system.cpu2.int_regfile_writes 30477342 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22294 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20824 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9434068 # number of misc regfile reads -system.cpu2.misc_regfile_writes 244358 # number of misc regfile writes +system.cpu2.rob.rob_reads 66205278 # The number of ROB reads +system.cpu2.rob.rob_writes 64842405 # The number of ROB writes +system.cpu2.timesIdled 359398 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51252392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567238209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19827262 # Number of Instructions Simulated +system.cpu2.committedOps 24525524 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19827262 # Number of Instructions Simulated +system.cpu2.cpi 4.454488 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.454488 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.224493 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.224493 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153057849 # number of integer regfile reads +system.cpu2.int_regfile_writes 29069811 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22288 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20782 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9001591 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241415 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1524,10 +1521,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925532055074 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 925532055074 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925532055074 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 925532055074 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981127238281 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981127238281 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981127238281 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981127238281 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 0ccf41cf5..5746894a9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.540276 # Number of seconds simulated -sim_ticks 2540275734000 # Number of ticks simulated -final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542409 # Number of seconds simulated +sim_ticks 2542409356000 # Number of ticks simulated +final_tick 2542409356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50621 # Simulator instruction rate (inst/s) -host_op_rate 65136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2132095179 # Simulator tick rate (ticks/s) -host_mem_usage 455960 # Number of bytes of host memory used -host_seconds 1191.45 # Real time elapsed on the host -sim_insts 60312498 # Number of instructions simulated -sim_ops 77605759 # Number of ops (including micro ops) simulated +host_inst_rate 77322 # Simulator instruction rate (inst/s) +host_op_rate 99492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3259551931 # Simulator tick rate (ticks/s) +host_mem_usage 413868 # Number of bytes of host memory used +host_seconds 779.99 # Real time elapsed on the host +sim_insts 60310148 # Number of instructions simulated +sim_ops 77602492 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 405568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3860688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 506624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4283408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5229152 # Number of bytes read from this memory -system.physmem.bytes_read::total 131004144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 405568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1412956 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1603284 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 292928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4810268 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006892 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 506624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1340604 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1675508 # Number of bytes written to this memory +system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 60357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81713 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59112 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 353239 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 400821 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813172 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47676135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 605 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 4577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75167 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 335151 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 418877 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47636124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 629 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1519791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1684783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 529 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 155498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2058498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51570836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 155498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 556222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 631146 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47676135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1892012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51528638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115217 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314486 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 527297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 659024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675881 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47636124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 629 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2076012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 199269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2212080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 529 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 155498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2689643 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54247478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293445 # Total number of read requests seen -system.physmem.writeReqs 813172 # Total number of write requests seen -system.physmem.cpureqs 218384 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978780480 # Total number of bytes read from memory -system.physmem.bytesWritten 52043008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131004144 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu1.inst 115217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2551035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54204519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293487 # Total number of read requests seen +system.physmem.writeReqs 813201 # Total number of write requests seen +system.physmem.cpureqs 218488 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978783168 # Total number of bytes read from memory +system.physmem.bytesWritten 52044864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006892 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955910 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955410 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955922 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955918 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955719 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50035 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50823 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51295 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51031 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 956241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956495 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955557 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956091 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50805 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51195 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51230 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 693675 # Number of times wr buffer was full causing retry -system.physmem.totGap 2540274436500 # Total gap between requests +system.physmem.numWrRetry 1790732 # Number of times wr buffer was full causing retry +system.physmem.totGap 2542408198000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 44 # Categorize read packet sizes +system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154585 # Categorize read packet sizes +system.physmem.readPktSize::6 154628 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1447735 # categorize write packet sizes +system.physmem.writePktSize::2 2544760 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59112 # categorize write packet sizes +system.physmem.writePktSize::6 59173 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -141,28 +141,28 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1057043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 949780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 984222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2774561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2777593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5475568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1054866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -174,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 31872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 31663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 31190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 30972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 30644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 30396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 31858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31605 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 295222941913 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 372544627913 # Sum of mem lat for all requests -system.physmem.totBusLat 61173736000 # Total cycles spent in databus access -system.physmem.totBankLat 16147950000 # Total cycles spent in bank access -system.physmem.avgQLat 19303.90 # Average queueing delay per request -system.physmem.avgBankLat 1055.87 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24359.78 # Average memory access latency -system.physmem.avgRdBW 385.30 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.49 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.57 # Average consumed read bandwidth in MB/s +system.physmem.totQLat 346733530557 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439908911807 # Sum of mem lat for all requests +system.physmem.totBusLat 76467385000 # Total cycles spent in databus access +system.physmem.totBankLat 16707996250 # Total cycles spent in bank access +system.physmem.avgQLat 22671.99 # Average queueing delay per request +system.physmem.avgBankLat 1092.49 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28764.48 # Average memory access latency +system.physmem.avgRdBW 384.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.54 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15250779 # Number of row buffer hits during reads -system.physmem.writeRowHits 786181 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.68 # Row buffer hit rate for writes -system.physmem.avgGap 157716.20 # Average gap between requests +system.physmem.readRowHits 15218342 # Number of row buffer hits during reads +system.physmem.writeRowHits 794645 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes +system.physmem.avgGap 157847.98 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -240,245 +240,239 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.089778 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000291 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013405 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.198791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000440 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011863 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245611 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.089778 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41387.654116 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42592.949196 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40941.666580 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10046.393474 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.465517 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 38080.687217 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 38237.204887 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38172.367057 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62043.541667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39738.402315 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38403.909130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54197.478261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40338.480881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 38482.998923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38581.456039 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050907 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94280181421 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95790429550 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190075661878 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025275 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015434 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989355 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988113 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988787 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.523087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558292 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541393 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.089857 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.089857 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -685,680 +667,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6894641 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5490275 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 340467 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4496048 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3641169 # Number of BTB hits +system.cpu0.branchPred.lookups 7548901 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6013590 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 377467 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4898170 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4008296 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 80.985990 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672237 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 35025 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.832521 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 726547 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38944 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25321176 # DTB read hits -system.cpu0.dtb.read_misses 39544 # DTB read misses -system.cpu0.dtb.write_hits 5538222 # DTB write hits -system.cpu0.dtb.write_misses 9025 # DTB write misses -system.cpu0.dtb.flush_tlb 256 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25977003 # DTB read hits +system.cpu0.dtb.read_misses 44168 # DTB read misses +system.cpu0.dtb.write_hits 5905544 # DTB write hits +system.cpu0.dtb.write_misses 10435 # DTB write misses +system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 7899 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1433 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 8487 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1476 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25360720 # DTB read accesses -system.cpu0.dtb.write_accesses 5547247 # DTB write accesses +system.cpu0.dtb.perms_faults 629 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26021171 # DTB read accesses +system.cpu0.dtb.write_accesses 5915979 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30859398 # DTB hits -system.cpu0.dtb.misses 48569 # DTB misses -system.cpu0.dtb.accesses 30907967 # DTB accesses -system.cpu0.itb.inst_hits 5399990 # ITB inst hits -system.cpu0.itb.inst_misses 6797 # ITB inst misses +system.cpu0.dtb.hits 31882547 # DTB hits +system.cpu0.dtb.misses 54603 # DTB misses +system.cpu0.dtb.accesses 31937150 # DTB accesses +system.cpu0.itb.inst_hits 6053570 # ITB inst hits +system.cpu0.itb.inst_misses 7437 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 256 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2645 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2703 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1504 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5406787 # ITB inst accesses -system.cpu0.itb.hits 5399990 # DTB hits -system.cpu0.itb.misses 6797 # DTB misses -system.cpu0.itb.accesses 5406787 # DTB accesses -system.cpu0.numCycles 232916834 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6061007 # ITB inst accesses +system.cpu0.itb.hits 6053570 # DTB hits +system.cpu0.itb.misses 7437 # DTB misses +system.cpu0.itb.accesses 6061007 # DTB accesses +system.cpu0.numCycles 238938486 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4313406 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 9542116 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2097502 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81571 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47928082 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 983 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1918 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48764 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90424 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5397887 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 280481 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3116 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 73293713 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.724548 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.073228 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15394391 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47363199 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7548901 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4734843 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10514679 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2521350 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 88217 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49746520 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 54986 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 100350 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6051440 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 388609 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3416 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77647495 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.755624 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.112120 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63759289 86.99% 86.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 642563 0.88% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816896 1.11% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1076628 1.47% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1030388 1.41% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 525946 0.72% 92.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1160801 1.58% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 367124 0.50% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3914078 5.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67140338 86.47% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 685224 0.88% 87.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 881384 1.14% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1215413 1.57% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1119001 1.44% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577018 0.74% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1310230 1.69% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 395483 0.51% 94.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4323404 5.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 73293713 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.029601 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.183647 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15070134 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 47635747 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8687716 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522868 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1375117 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 927671 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 82962 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 50805033 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 279607 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1375117 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 15858431 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18747322 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25731690 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8353206 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3225899 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 48905504 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13838 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 630791 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2093496 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 12811 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 50688794 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 222549147 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 222507399 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 41748 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 38461100 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12227693 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 386484 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 344770 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6389877 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9452191 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6279292 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 988040 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1320602 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 45692134 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 977389 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 60037368 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 85152 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8499333 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20279389 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 254746 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 73293713 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.819134 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.521823 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77647495 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031593 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.198223 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16447301 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49466389 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9519649 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 555058 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1656976 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1018880 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89951 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 55851060 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301878 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1656976 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17376198 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19158247 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27017971 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9071618 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3364444 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53098048 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 14247 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 629745 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2187800 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 13035 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55196889 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241870306 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 241822297 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48009 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40273759 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14923130 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 426834 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 378971 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6800028 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10269000 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6780798 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1063277 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1318043 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49318736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1023913 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62924434 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96522 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10293246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26052938 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 249929 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77647495 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.810386 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515841 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51609317 70.41% 70.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6835660 9.33% 79.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3457344 4.72% 84.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2997093 4.09% 88.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6031042 8.23% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1346418 1.84% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 738853 1.01% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 217523 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60463 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54849449 70.64% 70.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7244024 9.33% 79.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3688560 4.75% 84.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3114192 4.01% 88.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6252852 8.05% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1400137 1.80% 98.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 804405 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 228817 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65059 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 73293713 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77647495 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26194 0.60% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4172771 94.90% 95.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 28907 0.65% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 5 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4221672 94.79% 95.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203228 4.56% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 194561 0.32% 0.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 28037950 46.70% 47.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 44753 0.07% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 838 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 25907736 43.15% 90.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5851514 9.75% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 196078 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29762339 47.30% 47.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47254 0.08% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1214 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26685508 42.41% 90.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6232016 9.90% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 60037368 # Type of FU issued -system.cpu0.iq.rate 0.257763 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4397050 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.073239 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 197888427 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 55177485 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 41654501 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10625 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5737 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4733 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64234192 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5665 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 298497 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62924434 # Type of FU issued +system.cpu0.iq.rate 0.263350 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4453812 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070780 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208088796 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60644934 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43952872 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12311 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6553 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67175656 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6512 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 321336 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1811405 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3010 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 725021 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2241404 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3447 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16174 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 877395 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17048224 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 266574 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17145295 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 358927 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1375117 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14032156 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 223286 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 46775692 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 94480 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9452191 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6279292 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 703336 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 50186 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4000 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14875 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 165277 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 131199 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 296476 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 59245437 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 25661722 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 791931 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1656976 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14313344 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 236698 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50458165 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105115 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10269000 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6780798 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 724480 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 58024 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3552 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16174 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184745 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145643 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 330388 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61778089 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26333265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1146345 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 106169 # number of nop insts executed -system.cpu0.iew.exec_refs 31462090 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5561458 # Number of branches executed -system.cpu0.iew.exec_stores 5800368 # Number of stores executed -system.cpu0.iew.exec_rate 0.254363 # Inst execution rate -system.cpu0.iew.wb_sent 58848296 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 41659234 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23213315 # num instructions producing a value -system.cpu0.iew.wb_consumers 42468919 # num instructions consuming a value +system.cpu0.iew.exec_nop 115516 # number of nop insts executed +system.cpu0.iew.exec_refs 32508411 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5980040 # Number of branches executed +system.cpu0.iew.exec_stores 6175146 # Number of stores executed +system.cpu0.iew.exec_rate 0.258552 # Inst execution rate +system.cpu0.iew.wb_sent 61260719 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43958394 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24186405 # num instructions producing a value +system.cpu0.iew.wb_consumers 44536826 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178859 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546595 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.183974 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.543065 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8329034 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 722643 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 258629 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 71918596 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.527800 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.514238 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10181243 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 773984 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 288739 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75990519 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.523900 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.505441 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 58433692 81.25% 81.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6549576 9.11% 90.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1938281 2.70% 93.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1064527 1.48% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 992329 1.38% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 495986 0.69% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 654165 0.91% 97.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 355670 0.49% 98.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1434370 1.99% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61812445 81.34% 81.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6884323 9.06% 90.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2031918 2.67% 93.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1127942 1.48% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1041381 1.37% 95.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 554423 0.73% 96.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 699295 0.92% 97.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 364332 0.48% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1474460 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 71918596 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29885048 # Number of instructions committed -system.cpu0.commit.committedOps 37958605 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75990519 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31157319 # Number of instructions committed +system.cpu0.commit.committedOps 39811398 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13195057 # Number of memory references committed -system.cpu0.commit.loads 7640786 # Number of loads committed -system.cpu0.commit.membars 194107 # Number of memory barriers committed -system.cpu0.commit.branches 4848128 # Number of branches committed -system.cpu0.commit.fp_insts 4699 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 33604858 # Number of committed integer instructions. -system.cpu0.commit.function_calls 476381 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1434370 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13930999 # Number of memory references committed +system.cpu0.commit.loads 8027596 # Number of loads committed +system.cpu0.commit.membars 211461 # Number of memory barriers committed +system.cpu0.commit.branches 5178005 # Number of branches committed +system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35182368 # Number of committed integer instructions. +system.cpu0.commit.function_calls 511213 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1474460 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 115883530 # The number of ROB reads -system.cpu0.rob.rob_writes 93994803 # The number of ROB writes -system.cpu0.timesIdled 855495 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 159623121 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2324012553 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29813564 # Number of Instructions Simulated -system.cpu0.committedOps 37887121 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29813564 # Number of Instructions Simulated -system.cpu0.cpi 7.812445 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.812445 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.128001 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.128001 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 268137987 # number of integer regfile reads -system.cpu0.int_regfile_writes 42752144 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22081 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19566 # number of floating regfile writes -system.cpu0.misc_regfile_reads 14602892 # number of misc regfile reads -system.cpu0.misc_regfile_writes 394034 # number of misc regfile writes -system.cpu0.icache.replacements 984960 # number of replacements -system.cpu0.icache.tagsinuse 511.605628 # Cycle average of tags in use -system.cpu0.icache.total_refs 10192469 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985472 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.342728 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6475146000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 192.391014 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 319.214614 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.375764 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.623466 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999230 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 4895846 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5296623 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10192469 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4895846 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5296623 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10192469 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4895846 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5296623 # number of overall hits -system.cpu0.icache.overall_hits::total 10192469 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 501920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 563999 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065919 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 501920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 563999 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065919 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 501920 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 563999 # number of overall misses -system.cpu0.icache.overall_misses::total 1065919 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6726188495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7525770495 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14251958990 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6726188495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7525770495 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14251958990 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6726188495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7525770495 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14251958990 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5397766 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5860622 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11258388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5397766 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5860622 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11258388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5397766 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5860622 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11258388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092987 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.193555 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11765.095131 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11789.180744 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40608 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39535 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80143 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40608 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39535 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80143 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40608 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39535 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643643 # number of replacements -system.cpu0.dcache.tagsinuse 511.994132 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21553843 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644155 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.460647 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36157000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 257.044618 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 254.949514 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.502040 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.497948 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6668355 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 7127763 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13796118 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3513738 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3750110 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7263848 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119013 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 124173 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243186 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120748 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 126887 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10182093 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10877873 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21059966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10182093 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10877873 # number of overall hits -system.cpu0.dcache.overall_hits::total 21059966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 347013 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 745885 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1308679 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1650694 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2959373 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5990 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 7586 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1707551 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1997707 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3705258 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1707551 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1997707 # number of overall misses -system.cpu0.dcache.overall_misses::total 3705258 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5845680000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5302488500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11148168500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46981626335 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 67357897820 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114339524155 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81001000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 104468000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 185469000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 103000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 193000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52827306335 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 72660386320 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125487692655 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52827306335 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 72660386320 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125487692655 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7067227 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7474776 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14542003 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4822417 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5400804 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223221 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125003 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131759 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256762 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120754 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 126894 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11889644 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12875580 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24765224 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11889644 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12875580 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24765224 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056440 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.046425 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051292 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.271374 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.305639 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289476 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047919 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.057575 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052874 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155155 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149615 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143617 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155155 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149615 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14655.528591 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15280.374222 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14946.229647 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35900.038386 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40805.805207 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38636.401750 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13522.704508 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13771.157395 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13661.535062 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14714.285714 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14846.153846 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33867.464197 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30937.469121 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36371.893536 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33867.464197 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 37449 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 14136 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3410 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 266 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.982111 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.142857 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 643493 # number of replacements +system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21548288 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644005 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.459815 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43208000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 318.069743 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.922971 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.621230 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.378756 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7070467 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6719560 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13790027 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3778333 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3485501 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7263834 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125105 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 118624 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243729 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127190 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120429 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10848800 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10205061 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21053861 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10848800 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10205061 # number of overall hits +system.cpu0.dcache.overall_hits::total 21053861 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 426518 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 319237 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 745755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1396624 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1562374 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2958998 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6770 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6794 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13564 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1823142 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1881611 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3704753 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1823142 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1881611 # number of overall misses +system.cpu0.dcache.overall_misses::total 3704753 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6341434500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4955315500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11296750000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54124528351 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 59881914802 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114006443153 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91205000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94667500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 185872500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 60465962851 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 64837230302 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125303193153 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 60465962851 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 64837230302 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125303193153 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7496985 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7038797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14535782 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5174957 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5047875 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222832 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 131875 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125418 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257293 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127193 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120434 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12671942 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12086672 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24758614 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12671942 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12086672 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24758614 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056892 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045354 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051305 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269881 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.309511 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289450 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051336 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054171 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052718 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000024 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143872 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155677 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33822.279961 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35965 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14941 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3389 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 263 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.612275 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 56.809886 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608285 # number of writebacks -system.cpu0.dcache.writebacks::total 608285 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 207823 # 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number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101860769156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104755092045 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 206615861201 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027033 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026070 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026538 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023340 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025264 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.042559 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052019 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047414 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025637 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025732 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025637 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13553.062303 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13309.243275 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13429.947009 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31858.540118 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35387.300124 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33792.214211 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11734.680451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11935.658010 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.831444 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12846.153846 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20339.445406 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22401.807173 # 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mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023127 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046279 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048510 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047366 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000024 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026102 # 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average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1373,324 +1355,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7461261 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5924878 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 387688 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4864845 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3916001 # Number of BTB hits +system.cpu1.branchPred.lookups 7102253 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5695769 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 349355 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4570648 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3841672 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.495905 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 732677 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 39651 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.050927 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 676938 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35276 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25842433 # DTB read hits -system.cpu1.dtb.read_misses 46174 # DTB read misses -system.cpu1.dtb.write_hits 6180963 # DTB write hits -system.cpu1.dtb.write_misses 11315 # DTB write misses +system.cpu1.dtb.read_hits 25380131 # DTB read hits +system.cpu1.dtb.read_misses 40834 # DTB read misses +system.cpu1.dtb.write_hits 5811015 # DTB write hits +system.cpu1.dtb.write_misses 9771 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 8574 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1449 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1494 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 622 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25888607 # DTB read accesses -system.cpu1.dtb.write_accesses 6192278 # DTB write accesses +system.cpu1.dtb.perms_faults 637 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25420965 # DTB read accesses +system.cpu1.dtb.write_accesses 5820786 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 32023396 # DTB hits -system.cpu1.dtb.misses 57489 # DTB misses -system.cpu1.dtb.accesses 32080885 # DTB accesses -system.cpu1.itb.inst_hits 5862958 # ITB inst hits -system.cpu1.itb.inst_misses 7630 # ITB inst misses +system.cpu1.dtb.hits 31191146 # DTB hits +system.cpu1.dtb.misses 50605 # DTB misses +system.cpu1.dtb.accesses 31241751 # DTB accesses +system.cpu1.itb.inst_hits 6010554 # ITB inst hits +system.cpu1.itb.inst_misses 6924 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2762 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2690 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1655 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5870588 # ITB inst accesses -system.cpu1.itb.hits 5862958 # DTB hits -system.cpu1.itb.misses 7630 # DTB misses -system.cpu1.itb.accesses 5870588 # DTB accesses -system.cpu1.numCycles 238328292 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6017478 # ITB inst accesses +system.cpu1.itb.hits 6010554 # DTB hits +system.cpu1.itb.misses 6924 # DTB misses +system.cpu1.itb.accesses 6017478 # DTB accesses +system.cpu1.numCycles 234669310 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4648678 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10301295 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2449187 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 90048 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49530341 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2013 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 58322 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 105488 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5860623 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 343915 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3550 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 77436496 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.743507 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.098927 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15209580 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46712783 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7102253 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4518610 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10317375 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2619576 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83943 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47843149 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2062 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 49108 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 95676 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 6008408 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 439180 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3193 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 75397416 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.769986 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.133362 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 67142740 86.71% 86.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 670388 0.87% 87.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 904116 1.17% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1146258 1.48% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1035072 1.34% 91.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 585216 0.76% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1324002 1.71% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 382858 0.49% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4245846 5.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65087895 86.33% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 627947 0.83% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 837408 1.11% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205044 1.60% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1066340 1.41% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 537838 0.71% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1370888 1.82% 93.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 355288 0.47% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4308768 5.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 77436496 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031307 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191852 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16603606 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49335429 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9407116 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 490405 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1597859 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1045633 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 93792 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54840588 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 310696 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1597859 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17482170 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19064051 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27065673 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8938575 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3286155 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 52466184 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7798 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 497565 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2245284 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 18515 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 54189093 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 239808372 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 239759506 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48866 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39935280 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14253813 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 446450 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 393915 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6702948 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10122887 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6990261 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 974914 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1217289 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 48733638 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1005144 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62551860 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 96432 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9690546 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24103101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 245099 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 77436496 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.807783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.518787 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 75397416 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030265 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199058 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16234163 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47629419 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9365333 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 455355 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1710994 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 954633 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86850 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54991941 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 289065 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1710994 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17174187 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18737860 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25818505 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8802452 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3151356 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51852963 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7784 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 495819 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2156102 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 16790 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53921236 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237794819 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237752758 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42061 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38119457 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15801778 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 406275 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 360043 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6312412 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9898501 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6682455 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 887681 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1092966 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47793867 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 962748 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60992947 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 83561 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10588710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27790687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 254225 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 75397416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.808953 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.518534 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54919142 70.92% 70.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7063904 9.12% 80.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3691282 4.77% 84.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2953327 3.81% 88.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6235094 8.05% 96.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1492250 1.93% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 791283 1.02% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 225625 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64589 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53544512 71.02% 71.02% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6720979 8.91% 79.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3575565 4.74% 84.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2884458 3.83% 88.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6227948 8.26% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1437657 1.91% 98.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 736271 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210447 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59579 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 77436496 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 75397416 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 27571 0.62% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4198494 94.58% 95.20% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 213042 4.80% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24253 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4149284 94.86% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200652 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 169105 0.27% 0.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 29343777 46.91% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 48983 0.08% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1277 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26498919 42.36% 89.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6489779 10.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167588 0.27% 0.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28559163 46.82% 47.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46488 0.08% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 897 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26112884 42.81% 89.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6105909 10.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62551860 # Type of FU issued -system.cpu1.iq.rate 0.262461 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4439108 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.070967 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 207120715 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59438377 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 43832825 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12343 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6735 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5565 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 66815352 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6511 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 325479 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60992947 # Type of FU issued +system.cpu1.iq.rate 0.259910 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4374192 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071716 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201880877 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59353845 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41952881 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10603 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5821 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4743 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65193949 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5602 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306044 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2107508 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3797 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16351 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 811464 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2270775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14837 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 853246 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17060218 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 341441 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16957357 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 451019 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1597859 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14264833 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 247482 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 49856426 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 107204 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10122887 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6990261 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 704284 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 59901 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3604 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16351 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 190247 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 149600 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 339847 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 61552998 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26188496 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 998862 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1710994 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14077639 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 237686 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48863462 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 99358 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9898501 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6682455 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 687943 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 54116 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4064 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14837 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 169399 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 135230 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 304629 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59633634 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25710347 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1359313 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 117644 # number of nop insts executed -system.cpu1.iew.exec_refs 32619530 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5900270 # Number of branches executed -system.cpu1.iew.exec_stores 6431034 # Number of stores executed -system.cpu1.iew.exec_rate 0.258270 # Inst execution rate -system.cpu1.iew.wb_sent 61059596 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 43838390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23681235 # num instructions producing a value -system.cpu1.iew.wb_consumers 43694541 # num instructions consuming a value +system.cpu1.iew.exec_nop 106847 # number of nop insts executed +system.cpu1.iew.exec_refs 31763994 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5570991 # Number of branches executed +system.cpu1.iew.exec_stores 6053647 # Number of stores executed +system.cpu1.iew.exec_rate 0.254118 # Inst execution rate +system.cpu1.iew.wb_sent 59059835 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41957624 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22877560 # num instructions producing a value +system.cpu1.iew.wb_consumers 41856848 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.183941 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541972 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178795 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.546567 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9661212 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 760045 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 295282 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75838637 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.524766 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.504226 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10488461 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 708523 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 263786 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73686422 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.514905 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496046 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61579117 81.20% 81.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7021291 9.26% 90.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2015124 2.66% 93.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1085811 1.43% 94.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1003078 1.32% 95.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 577963 0.76% 96.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 742657 0.98% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378274 0.50% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1435322 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60141742 81.62% 81.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6665026 9.05% 90.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1916982 2.60% 93.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1022287 1.39% 94.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 952512 1.29% 95.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 518669 0.70% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 704589 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372223 0.51% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1392392 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75838637 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30577831 # Number of instructions committed -system.cpu1.commit.committedOps 39797535 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73686422 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29303210 # Number of instructions committed +system.cpu1.commit.committedOps 37941475 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 14194176 # Number of memory references committed -system.cpu1.commit.loads 8015379 # Number of loads committed -system.cpu1.commit.membars 209589 # Number of memory barriers committed -system.cpu1.commit.branches 5113967 # Number of branches committed -system.cpu1.commit.fp_insts 5513 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 35255841 # Number of committed integer instructions. -system.cpu1.commit.function_calls 515004 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1435322 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13456935 # Number of memory references committed +system.cpu1.commit.loads 7627726 # Number of loads committed +system.cpu1.commit.membars 192181 # Number of memory barriers committed +system.cpu1.commit.branches 4783662 # Number of branches committed +system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33675461 # Number of committed integer instructions. +system.cpu1.commit.function_calls 480108 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1392392 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 122900984 # The number of ROB reads -system.cpu1.rob.rob_writes 100566633 # The number of ROB writes -system.cpu1.timesIdled 901138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160891796 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2255172449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30498934 # Number of Instructions Simulated -system.cpu1.committedOps 39718638 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30498934 # Number of Instructions Simulated -system.cpu1.cpi 7.814315 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.814315 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127970 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127970 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 279110946 # number of integer regfile reads -system.cpu1.int_regfile_writes 44685160 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22658 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19886 # number of floating regfile writes -system.cpu1.misc_regfile_reads 15820673 # number of misc regfile reads -system.cpu1.misc_regfile_writes 438571 # number of misc regfile writes +system.cpu1.rob.rob_reads 119835622 # The number of ROB reads +system.cpu1.rob.rob_writes 98622587 # The number of ROB writes +system.cpu1.timesIdled 873829 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159271894 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285541005 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29230871 # Number of Instructions Simulated +system.cpu1.committedOps 37869136 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29230871 # Number of Instructions Simulated +system.cpu1.cpi 8.028133 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.028133 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124562 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124562 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 270257014 # number of integer regfile reads +system.cpu1.int_regfile_writes 43086162 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22099 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19636 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14849439 # number of misc regfile reads +system.cpu1.misc_regfile_writes 404495 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1705,17 +1687,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1125362728944 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1125362728944 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1125362728944 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192737213912 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83058 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83053 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 133b16bb8..cc1497460 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.609477 # Number of seconds simulated -sim_ticks 2609476867000 # Number of ticks simulated -final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.608779 # Number of seconds simulated +sim_ticks 2608778789000 # Number of ticks simulated +final_tick 2608778789000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 397155 # Simulator instruction rate (inst/s) -host_op_rate 505377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17213891867 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 151.59 # Real time elapsed on the host -sim_insts 60205243 # Number of instructions simulated -sim_ops 76610733 # Number of ops (including micro ops) simulated +host_inst_rate 458042 # Simulator instruction rate (inst/s) +host_op_rate 582855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19847185908 # Simulator tick rate (ticks/s) +host_mem_usage 403628 # Number of bytes of host memory used +host_seconds 131.44 # Real time elapsed on the host +sim_insts 60206536 # Number of instructions simulated +sim_ops 76612339 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 349152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4456460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 356032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4588440 # Number of bytes read from this memory -system.physmem.bytes_read::total 132433668 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 349152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 356032 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 419296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4486284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 285888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4557412 # Number of bytes read from this memory +system.physmem.bytes_read::total 132432464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 419296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 285888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522768 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1493500 # Number of bytes written to this memory -system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3671168 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1520308 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1495832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6687308 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71715 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380692 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373375 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47014554 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 12754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380077 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373958 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811397 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47027135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 133802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1707798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 136438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1758375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50751041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 133802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 136438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1407424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 572337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2563314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1407424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47014554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 160725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1719687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 109587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1746952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50764160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 160725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 109587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1407236 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 582766 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 573384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2563386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1407236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47027135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 133802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2291351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 136438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2330712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53314355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494028 # Total number of read requests seen -system.physmem.writeReqs 811452 # Total number of write requests seen -system.physmem.cpureqs 213833 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991617792 # Total number of bytes read from memory -system.physmem.bytesWritten 51932928 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132433668 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu0.inst 160725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2302454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 109587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2320336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53327546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494012 # Total number of read requests seen +system.physmem.writeReqs 811397 # Total number of write requests seen +system.physmem.cpureqs 213789 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991616768 # Total number of bytes read from memory +system.physmem.bytesWritten 51929408 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132432464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6687308 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4517 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967970 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967933 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967538 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974536 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967963 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50348 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49920 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50745 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51015 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51209 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 974838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967895 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968388 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967512 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50747 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2609472479500 # Total gap between requests +system.physmem.totGap 2608774377500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 6673 # Categorize read packet sizes +system.physmem.readPktSize::2 6676 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 151931 # Categorize read packet sizes +system.physmem.readPktSize::6 151912 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754067 # categorize write packet sizes +system.physmem.writePktSize::2 754035 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57385 # categorize write packet sizes +system.physmem.writePktSize::6 57362 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -130,26 +130,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4517 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4515 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1117981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 962159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 962420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 998543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2811240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5545406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 36112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 58787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 30559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 58397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1116413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3651904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2754719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2759720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2733933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 61766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 60421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 162702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -166,30 +166,30 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -199,27 +199,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 286738639625 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 365542479625 # Sum of mem lat for all requests -system.physmem.totBusLat 61976008000 # Total cycles spent in databus access -system.physmem.totBankLat 16827832000 # Total cycles spent in bank access -system.physmem.avgQLat 18506.43 # Average queueing delay per request -system.physmem.avgBankLat 1086.09 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23592.52 # Average memory access latency -system.physmem.avgRdBW 380.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.75 # Average consumed read bandwidth in MB/s +system.physmem.totQLat 338341857800 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 433208122800 # Sum of mem lat for all requests +system.physmem.totBusLat 77469930000 # Total cycles spent in databus access +system.physmem.totBankLat 17396335000 # Total cycles spent in bank access +system.physmem.avgQLat 21836.98 # Average queueing delay per request +system.physmem.avgBankLat 1122.78 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27959.76 # Average memory access latency +system.physmem.avgRdBW 380.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.91 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.76 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.50 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 1.25 # Average write queue length over time -system.physmem.readRowHits 15452119 # Number of row buffer hits during reads -system.physmem.writeRowHits 785190 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 160036.53 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 1.24 # Average write queue length over time +system.physmem.readRowHits 15419486 # Number of row buffer hits during reads +system.physmem.writeRowHits 793977 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159994.42 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -232,205 +232,205 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 61820 # number of replacements -system.l2c.tagsinuse 50921.903557 # Cycle average of tags in use -system.l2c.total_refs 1697937 # Total number of references to valid blocks. -system.l2c.sampled_refs 127204 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.348142 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2557805301500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.972595 # Average occupied blocks per requestor +system.l2c.replacements 61800 # number of replacements +system.l2c.tagsinuse 50918.253702 # Cycle average of tags in use +system.l2c.total_refs 1698591 # Total number of references to valid blocks. +system.l2c.sampled_refs 127185 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.355278 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2557152484500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37907.717848 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000639 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3578.783807 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2862.372936 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3416.906879 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3151.866517 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.578491 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.000642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4327.115126 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3096.490855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2668.881351 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2918.047697 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.578426 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.054608 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043676 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.052138 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.048094 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.777007 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9713 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 390514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 186540 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9847 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 453502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 184024 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241218 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596393 # number of Writeback hits -system.l2c.Writeback_hits::total 596393 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.066027 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.047249 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.040724 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044526 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.776951 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 10142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3715 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 409497 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188260 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9560 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3405 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 434855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182318 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241752 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596435 # number of Writeback hits +system.l2c.Writeback_hits::total 596435 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114563 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9713 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 390514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 242441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9847 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 453502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 242686 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355781 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9713 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3454 # number of overall hits -system.l2c.overall_hits::cpu0.inst 390514 # number of overall hits -system.l2c.overall_hits::cpu0.data 242441 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9847 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3624 # number of overall hits -system.l2c.overall_hits::cpu1.inst 453502 # number of overall hits -system.l2c.overall_hits::cpu1.data 242686 # number of overall hits -system.l2c.overall_hits::total 1355781 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36625.253868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32501.786804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 37003.784828 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33751.068593 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 33390.158918 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209122550 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 88446498738 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 87416214232 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176071835520 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028446 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016208 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992171 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989946 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.531754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.542983 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537407 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101701 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000538 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014768 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.223868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010168 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.231377 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101701 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 39576.914187 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 43258.955970 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40924.497507 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.401490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.096830 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32569.105197 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 33566.811232 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33076.563652 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39289.297165 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33113.815520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42569.197672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 34150.479225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34122.130291 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -588,135 +588,135 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7346324 # DTB read hits -system.cpu0.dtb.read_misses 6876 # DTB read misses -system.cpu0.dtb.write_hits 5393725 # DTB write hits -system.cpu0.dtb.write_misses 1788 # DTB write misses -system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7507423 # DTB read hits +system.cpu0.dtb.read_misses 6880 # DTB read misses +system.cpu0.dtb.write_hits 5552288 # DTB write hits +system.cpu0.dtb.write_misses 1844 # DTB write misses +system.cpu0.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6380 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6531 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 236 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7353200 # DTB read accesses -system.cpu0.dtb.write_accesses 5395513 # DTB write accesses +system.cpu0.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7514303 # DTB read accesses +system.cpu0.dtb.write_accesses 5554132 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12740049 # DTB hits -system.cpu0.dtb.misses 8664 # DTB misses -system.cpu0.dtb.accesses 12748713 # DTB accesses -system.cpu0.itb.inst_hits 30077314 # ITB inst hits -system.cpu0.itb.inst_misses 3618 # ITB inst misses +system.cpu0.dtb.hits 13059711 # DTB hits +system.cpu0.dtb.misses 8724 # DTB misses +system.cpu0.dtb.accesses 13068435 # DTB accesses +system.cpu0.itb.inst_hits 30766737 # ITB inst hits +system.cpu0.itb.inst_misses 3610 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 739 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2643 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 721 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2714 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30080932 # ITB inst accesses -system.cpu0.itb.hits 30077314 # DTB hits -system.cpu0.itb.misses 3618 # DTB misses -system.cpu0.itb.accesses 30080932 # DTB accesses -system.cpu0.numCycles 2667978103 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30770347 # ITB inst accesses +system.cpu0.itb.hits 30766737 # DTB hits +system.cpu0.itb.misses 3610 # DTB misses +system.cpu0.itb.accesses 30770347 # DTB accesses +system.cpu0.numCycles 2552892042 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29443364 # Number of instructions committed -system.cpu0.committedOps 37313873 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33552683 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4308 # Number of float alu accesses -system.cpu0.num_func_calls 997498 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3872350 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33552683 # number of integer instructions -system.cpu0.num_fp_insts 4308 # number of float instructions -system.cpu0.num_int_register_reads 192457043 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36187608 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3214 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1096 # number of times the floating registers were written -system.cpu0.num_mem_refs 13317945 # number of memory refs -system.cpu0.num_load_insts 7675788 # Number of load instructions -system.cpu0.num_store_insts 5642157 # Number of store instructions -system.cpu0.num_idle_cycles 1511306252.685236 # Number of idle cycles -system.cpu0.num_busy_cycles 1156671850.314764 # Number of busy cycles -system.cpu0.not_idle_fraction 0.433539 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.566461 # Percentage of idle cycles +system.cpu0.committedInsts 30144083 # Number of instructions committed +system.cpu0.committedOps 38293118 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34424567 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5276 # Number of float alu accesses +system.cpu0.num_func_calls 1041312 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4017319 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34424567 # number of integer instructions +system.cpu0.num_fp_insts 5276 # number of float instructions +system.cpu0.num_int_register_reads 197342497 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37147622 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3922 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1356 # number of times the floating registers were written +system.cpu0.num_mem_refs 13659512 # number of memory refs +system.cpu0.num_load_insts 7847120 # Number of load instructions +system.cpu0.num_store_insts 5812392 # Number of store instructions +system.cpu0.num_idle_cycles 3486759367.777020 # Number of idle cycles +system.cpu0.num_busy_cycles -933867325.777020 # Number of busy cycles +system.cpu0.not_idle_fraction -0.365808 # Percentage of non-idle cycles +system.cpu0.idle_fraction 1.365808 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83014 # number of quiesce instructions executed -system.cpu0.icache.replacements 855749 # number of replacements -system.cpu0.icache.tagsinuse 510.984146 # Cycle average of tags in use -system.cpu0.icache.total_refs 60643040 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 856261 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 70.823078 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 18731806000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 165.100321 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 345.883825 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.322462 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.675554 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29681003 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30962037 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60643040 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29681003 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30962037 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60643040 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29681003 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30962037 # number of overall hits -system.cpu0.icache.overall_hits::total 60643040 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 396311 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 459950 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856261 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 396311 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 459950 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856261 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 396311 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 459950 # number of overall misses -system.cpu0.icache.overall_misses::total 856261 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5359552000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6210691500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11570243500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5359552000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6210691500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11570243500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5359552000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6210691500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11570243500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30077314 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31421987 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61499301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30077314 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31421987 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61499301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30077314 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31421987 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61499301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013176 # 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average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13512.519547 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13523.601414 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13502.970975 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13512.519547 # average overall miss latency +system.cpu0.kern.inst.quiesce 83016 # number of quiesce instructions executed +system.cpu0.icache.replacements 856082 # number of replacements +system.cpu0.icache.tagsinuse 510.977353 # Cycle average of tags in use +system.cpu0.icache.total_refs 60644038 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 856594 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 70.796711 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13479.071923 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13557.954527 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,158 +725,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 396311 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 459950 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856261 # 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number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4506635000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3684595000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3854585000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7539180000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66669000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65974000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 132643000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5992861500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6052953500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12045815000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5992861500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6052953500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12045815000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91377449500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90718593500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182096043000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 9611433000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 9088267500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18699700500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 101776422000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99014996000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200791418000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027999 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026436 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027201 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025039 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.052674 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040614 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025385 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12145.021237 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12180.475746 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12162.627911 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29674.236004 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30197.305033 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29941.154052 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11924.025864 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11294.755877 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11618.962041 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.201505 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19585.329635 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19352.763781 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100988882500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 99806861000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200795743500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024605 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048841 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046074 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026042 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026367 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025719 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026042 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12267.246831 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12155.890582 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12212.672724 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29619.883276 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30551.209498 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30088.839578 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11890.315677 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11359.159780 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11620.061323 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19173.414150 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19715.433398 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19441.998331 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -976,68 +976,68 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7651718 # DTB read hits -system.cpu1.dtb.read_misses 6996 # DTB read misses -system.cpu1.dtb.write_hits 5838563 # DTB write hits -system.cpu1.dtb.write_misses 1808 # DTB write misses -system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7490923 # DTB read hits +system.cpu1.dtb.read_misses 7080 # DTB read misses +system.cpu1.dtb.write_hits 5680189 # DTB write hits +system.cpu1.dtb.write_misses 1780 # DTB write misses +system.cpu1.dtb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6464 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6451 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 130 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 157 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7658714 # DTB read accesses -system.cpu1.dtb.write_accesses 5840371 # DTB write accesses +system.cpu1.dtb.perms_faults 207 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7498003 # DTB read accesses +system.cpu1.dtb.write_accesses 5681969 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13490281 # DTB hits -system.cpu1.dtb.misses 8804 # DTB misses -system.cpu1.dtb.accesses 13499085 # DTB accesses -system.cpu1.itb.inst_hits 31421987 # ITB inst hits -system.cpu1.itb.inst_misses 3616 # ITB inst misses +system.cpu1.dtb.hits 13171112 # DTB hits +system.cpu1.dtb.misses 8860 # DTB misses +system.cpu1.dtb.accesses 13179972 # DTB accesses +system.cpu1.itb.inst_hits 30733895 # ITB inst hits +system.cpu1.itb.inst_misses 3661 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1275 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 700 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2808 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2756 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31425603 # ITB inst accesses -system.cpu1.itb.hits 31421987 # DTB hits -system.cpu1.itb.misses 3616 # DTB misses -system.cpu1.itb.accesses 31425603 # DTB accesses -system.cpu1.numCycles 2550975631 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30737556 # ITB inst accesses +system.cpu1.itb.hits 30733895 # DTB hits +system.cpu1.itb.misses 3661 # DTB misses +system.cpu1.itb.accesses 30737556 # DTB accesses +system.cpu1.numCycles 2664665536 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30761879 # Number of instructions committed -system.cpu1.committedOps 39296860 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35324832 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5961 # Number of float alu accesses -system.cpu1.num_func_calls 1142639 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4076383 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35324832 # number of integer instructions -system.cpu1.num_fp_insts 5961 # number of float instructions -system.cpu1.num_int_register_reads 202353181 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37998347 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4279 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1684 # number of times the floating registers were written -system.cpu1.num_mem_refs 14079956 # number of memory refs -system.cpu1.num_load_insts 7986446 # Number of load instructions -system.cpu1.num_store_insts 6093510 # Number of store instructions -system.cpu1.num_idle_cycles 3341647478.137703 # Number of idle cycles -system.cpu1.num_busy_cycles -790671847.137703 # Number of busy cycles -system.cpu1.not_idle_fraction -0.309949 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.309949 # Percentage of idle cycles +system.cpu1.committedInsts 30062453 # Number of instructions committed +system.cpu1.committedOps 38319221 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34454483 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4993 # Number of float alu accesses +system.cpu1.num_func_calls 1098871 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3931518 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34454483 # number of integer instructions +system.cpu1.num_fp_insts 4993 # number of float instructions +system.cpu1.num_int_register_reads 197476279 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37039984 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3571 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1424 # number of times the floating registers were written +system.cpu1.num_mem_refs 13738954 # number of memory refs +system.cpu1.num_load_insts 7815473 # Number of load instructions +system.cpu1.num_store_insts 5923481 # Number of store instructions +system.cpu1.num_idle_cycles 1359992851.787481 # Number of idle cycles +system.cpu1.num_busy_cycles 1304672684.212520 # Number of busy cycles +system.cpu1.not_idle_fraction 0.489620 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.510380 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.replacements 0 # number of replacements @@ -1054,10 +1054,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1128670778319 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1128670778319 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1128670778319 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1196180344448 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1196180344448 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1196180344448 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 5af891b0b..dd60f3acd 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.136818 # Number of seconds simulated -sim_ticks 5136817990000 # Number of ticks simulated -final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136862 # Number of seconds simulated +sim_ticks 5136862311000 # Number of ticks simulated +final_tick 5136862311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121455 # Simulator instruction rate (inst/s) -host_op_rate 240079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1529355788 # Simulator tick rate (ticks/s) -host_mem_usage 804152 # Number of bytes of host memory used -host_seconds 3358.81 # Real time elapsed on the host -sim_insts 407944006 # Number of instructions simulated -sim_ops 806380994 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1073088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10819392 # Number of bytes read from this memory -system.physmem.bytes_read::total 14368384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1073088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1073088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9566592 # Number of bytes written to this memory -system.physmem.bytes_written::total 9566592 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38633 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224506 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149478 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 481331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 208901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2106244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2797137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1862358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1862358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1862358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 481331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2106244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4659495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224506 # Total number of read requests seen -system.physmem.writeReqs 149478 # Total number of write requests seen -system.physmem.cpureqs 388421 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14368384 # Total number of bytes read from memory -system.physmem.bytesWritten 9566592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14368384 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9566592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 103 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4169 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13472 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 14632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13510 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 15204 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 14943 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 10024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8415 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9887 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9822 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 10163 # Track writes on a per bank basis +host_inst_rate 202420 # Simulator instruction rate (inst/s) +host_op_rate 400133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2548945395 # Simulator tick rate (ticks/s) +host_mem_usage 760276 # Number of bytes of host memory used +host_seconds 2015.29 # Real time elapsed on the host +sim_insts 407935752 # Number of instructions simulated +sim_ops 806383618 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2490880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1078272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10788032 # Number of bytes read from this memory +system.physmem.bytes_read::total 14361024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1078272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1078272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9547840 # Number of bytes written to this memory +system.physmem.bytes_written::total 9547840 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168563 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149185 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149185 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 484903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2100121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2795680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1858691 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1858691 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1858691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 484903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 209909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2100121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4654371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224391 # Total number of read requests seen +system.physmem.writeReqs 149185 # Total number of write requests seen +system.physmem.cpureqs 388105 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14361024 # Total number of bytes read from memory +system.physmem.bytesWritten 9547840 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14361024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9547840 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3903 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14157 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16342 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13760 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13186 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15501 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8570 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8914 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11741 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8779 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 10975 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 10995 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 164 # Number of times wr buffer was full causing retry -system.physmem.totGap 5136817938000 # Total gap between requests +system.physmem.numWrRetry 794 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136862258500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224506 # Categorize read packet sizes +system.physmem.readPktSize::6 224391 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 149642 # categorize write packet sizes +system.physmem.writePktSize::6 149979 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,32 +114,32 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4169 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3903 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 176041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 173046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -150,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3338682949 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7589868949 # Sum of mem lat for all requests -system.physmem.totBusLat 897612000 # Total cycles spent in databus access -system.physmem.totBankLat 3353574000 # Total cycles spent in bank access -system.physmem.avgQLat 14878.07 # Average queueing delay per request -system.physmem.avgBankLat 14944.43 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33822.49 # Average memory access latency +system.physmem.totQLat 4730288859 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9241012609 # Sum of mem lat for all requests +system.physmem.totBusLat 1121280000 # Total cycles spent in databus access +system.physmem.totBankLat 3389443750 # Total cycles spent in bank access +system.physmem.avgQLat 21093.25 # Average queueing delay per request +system.physmem.avgBankLat 15114.17 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 41207.43 # Average memory access latency system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.19 # Average write queue length over time -system.physmem.readRowHits 197567 # Number of row buffer hits during reads -system.physmem.writeRowHits 87961 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes -system.physmem.avgGap 13735394.93 # Average gap between requests -system.iocache.replacements 47579 # number of replacements -system.iocache.tagsinuse 0.116428 # Cycle average of tags in use +system.physmem.avgWrQLen 12.83 # Average write queue length over time +system.physmem.readRowHits 193267 # Number of row buffer hits during reads +system.physmem.writeRowHits 105785 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.91 # Row buffer hit rate for writes +system.physmem.avgGap 13750514.64 # Average gap between requests +system.iocache.replacements 47583 # number of replacements +system.iocache.tagsinuse 0.137403 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47599 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991841370000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.116428 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007277 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007277 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses -system.iocache.ReadReq_misses::total 914 # number of ReadReq misses +system.iocache.warmup_cycle 4991910569000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.137403 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.008588 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.008588 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 912 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses -system.iocache.demand_misses::total 47634 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses -system.iocache.overall_misses::total 47634 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143641932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143641932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8950549160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 8950549160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9094191092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9094191092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9094191092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9094191092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses +system.iocache.demand_misses::total 47632 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses +system.iocache.overall_misses::total 47632 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144324932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144324932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10020383160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10020383160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10164708092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10164708092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10164708092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10164708092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157157.474836 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157157.474836 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191578.535103 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 191578.535103 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190918.064660 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190918.064660 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 54662 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158251.021930 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158251.021930 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214477.379281 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 214477.379281 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 213400.824908 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 213400.824908 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 133472 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7510 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12161 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.278562 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.975413 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46673 # number of writebacks +system.iocache.writebacks::total 46673 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47634 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47634 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47634 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47634 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96083990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96083990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6518807893 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6518807893 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6614891883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6614891883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96878242 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96878242 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7589579568 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7589579568 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7686457810 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7686457810 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,18 +287,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105124.715536 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105124.715536 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139529.278532 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 139529.278532 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106226.142544 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 106226.142544 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162448.192808 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 162448.192808 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -308,142 +308,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86252881 # Number of BP lookups -system.cpu.branchPred.condPredicted 86252881 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1115345 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81384938 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79240101 # Number of BTB hits +system.cpu.branchPred.lookups 86190273 # Number of BP lookups +system.cpu.branchPred.condPredicted 86190273 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1107531 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81286866 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79207834 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.364577 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.442352 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 447901761 # number of cpu cycles simulated +system.cpu.numCycles 448143159 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79240101 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163642808 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4755358 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 112288 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62866127 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 52962 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9042653 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 488997 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3194 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257883656 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.262433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27503051 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425930482 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86190273 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79207834 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163575255 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4699027 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 119359 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63002200 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36275 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 56191 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 501 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9012986 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 485449 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3601 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257845073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418049 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94667319 36.71% 36.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1563412 0.61% 37.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71921029 27.89% 65.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936098 0.36% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1601572 0.62% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2435088 0.94% 67.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1080780 0.42% 67.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1378788 0.53% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82299570 31.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94696195 36.73% 36.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1566516 0.61% 37.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71918479 27.89% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 936665 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1597376 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2419164 0.94% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1071712 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1371295 0.53% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82267671 31.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257883656 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192571 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.951525 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31254353 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60335803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159451505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3240373 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3601622 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838158125 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3601622 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34003643 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37352024 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10890553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159616474 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12419340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834485567 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19816 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5811427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4758263 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7797 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 996045264 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811616758 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811616222 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964358369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31686888 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460019 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 467360 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28800044 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17105540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10151316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1164746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 891886 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828333374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1249979 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823307593 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 149787 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22280168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33846252 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 197115 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257883656 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.192554 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.383898 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257845073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192328 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950434 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31188651 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60472166 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159373926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3258089 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3552241 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837743575 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 790 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3552241 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33924496 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37350938 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11010617 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159571112 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12435669 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834099694 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18960 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5861549 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4743149 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8341 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995593221 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810589255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810588751 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964361742 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31231472 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459351 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 467339 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28773559 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17056832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10125853 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1239786 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 991765 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827988990 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1249374 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823075347 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 149433 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21943198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33340930 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 196529 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257845073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.192131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383978 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71395205 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15462696 6.00% 33.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10317630 4.00% 37.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7483312 2.90% 40.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75909298 29.44% 70.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3861835 1.50% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72513968 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 788170 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151542 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71377289 27.68% 27.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15522092 6.02% 33.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10290654 3.99% 37.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7462079 2.89% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75909573 29.44% 70.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3836908 1.49% 71.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72514603 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 779740 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152135 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257883656 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257845073 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 365240 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553441 51.78% 85.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150145 14.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 361447 33.94% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553013 51.93% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150537 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 311438 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795721586 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 311265 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795546265 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -472,246 +472,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17876340 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9398229 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17838711 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9379106 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823307593 # Type of FU issued -system.cpu.iq.rate 1.838143 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1068826 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001298 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905849140 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851873423 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818806890 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824064883 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1642369 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823075347 # Type of FU issued +system.cpu.iq.rate 1.836635 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1064997 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001294 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905340193 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851191548 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818612199 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 185 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823828994 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 85 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1638396 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3123872 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22910 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1729878 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3078783 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22684 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11490 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1711608 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932382 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12176 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932396 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11890 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3601622 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26144135 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2117005 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829583353 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 307079 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17105540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10151316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719112 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1614713 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12810 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 656230 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 596856 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1253086 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821409782 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17457108 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1897810 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3552241 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26088999 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2114690 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829238364 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 319607 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17056832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10125853 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718701 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615260 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11047 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11490 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 650165 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 594804 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1244969 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821209157 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17428424 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1866189 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26622226 # number of memory reference insts executed -system.cpu.iew.exec_branches 83220659 # Number of branches executed -system.cpu.iew.exec_stores 9165118 # Number of stores executed -system.cpu.iew.exec_rate 1.833906 # Inst execution rate -system.cpu.iew.wb_sent 820945177 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818806944 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639956313 # num instructions producing a value -system.cpu.iew.wb_consumers 1045834424 # num instructions consuming a value +system.cpu.iew.exec_refs 26576192 # number of memory reference insts executed +system.cpu.iew.exec_branches 83198528 # Number of branches executed +system.cpu.iew.exec_stores 9147768 # Number of stores executed +system.cpu.iew.exec_rate 1.832471 # Inst execution rate +system.cpu.iew.wb_sent 820748086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818612249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639805768 # num instructions producing a value +system.cpu.iew.wb_consumers 1045573656 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.828095 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611910 # average fanout of values written-back +system.cpu.iew.wb_rate 1.826676 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611918 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23092364 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052862 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1120067 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254282034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.171207 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.854640 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22746956 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052843 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1113134 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254292832 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82542979 32.46% 32.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11813450 4.65% 37.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3859102 1.52% 38.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74953678 29.48% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2443754 0.96% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1483333 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 886403 0.35% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70916473 27.89% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5382862 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82512721 32.45% 32.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11810250 4.64% 37.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3911409 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74946899 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2433458 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1482000 0.58% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 941049 0.37% 70.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70920641 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334405 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254282034 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407944006 # Number of instructions committed -system.cpu.commit.committedOps 806380994 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254292832 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407935752 # Number of instructions committed +system.cpu.commit.committedOps 806383618 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22403103 # Number of memory references committed -system.cpu.commit.loads 13981665 # Number of loads committed -system.cpu.commit.membars 473467 # Number of memory barriers committed -system.cpu.commit.branches 82194070 # Number of branches committed +system.cpu.commit.refs 22392291 # Number of memory references committed +system.cpu.commit.loads 13978046 # Number of loads committed +system.cpu.commit.membars 473511 # Number of memory barriers committed +system.cpu.commit.branches 82192705 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735324556 # Number of committed integer instructions. +system.cpu.commit.int_insts 735323034 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5382862 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078294199 # The number of ROB reads -system.cpu.rob.rob_writes 1662567045 # The number of ROB writes -system.cpu.timesIdled 1221565 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190018105 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9825731637 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407944006 # Number of Instructions Simulated -system.cpu.committedOps 806380994 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407944006 # Number of Instructions Simulated -system.cpu.cpi 1.097949 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.097949 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910789 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910789 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1507043995 # number of integer regfile reads -system.cpu.int_regfile_writes 976998949 # number of integer regfile writes -system.cpu.fp_regfile_reads 54 # number of floating regfile reads -system.cpu.misc_regfile_reads 264734619 # number of misc regfile reads -system.cpu.misc_regfile_writes 402509 # number of misc regfile writes -system.cpu.icache.replacements 1054256 # number of replacements -system.cpu.icache.tagsinuse 510.988943 # Cycle average of tags in use -system.cpu.icache.total_refs 7923866 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1054768 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.512425 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56004276000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.988943 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998025 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998025 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7923866 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7923866 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7923866 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7923866 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7923866 # number of overall hits -system.cpu.icache.overall_hits::total 7923866 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1118784 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1118784 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1118784 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1118784 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1118784 # number of overall misses -system.cpu.icache.overall_misses::total 1118784 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15167301487 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15167301487 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15167301487 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15167301487 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15167301487 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15167301487 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9042650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9042650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9042650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9042650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9042650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9042650 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13556.952447 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13556.952447 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13556.952447 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13556.952447 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 9830 # number of cycles access was blocked +system.cpu.rob.rob_reads 1078010714 # The number of ROB reads +system.cpu.rob.rob_writes 1661832245 # The number of ROB writes +system.cpu.timesIdled 1221118 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190298086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825578883 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407935752 # Number of Instructions Simulated +system.cpu.committedOps 806383618 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407935752 # Number of Instructions Simulated +system.cpu.cpi 1.098563 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098563 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910280 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910280 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506729750 # number of integer regfile reads +system.cpu.int_regfile_writes 976791944 # number of integer regfile writes +system.cpu.fp_regfile_reads 50 # number of floating regfile reads +system.cpu.misc_regfile_reads 264623965 # number of misc regfile reads +system.cpu.misc_regfile_writes 402412 # number of misc regfile writes +system.cpu.icache.replacements 1049766 # number of replacements +system.cpu.icache.tagsinuse 510.907265 # Cycle average of tags in use +system.cpu.icache.total_refs 7899601 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1050278 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.521438 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.907265 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997866 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997866 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7899601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7899601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7899601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7899601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7899601 # number of overall hits +system.cpu.icache.overall_hits::total 7899601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1113380 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1113380 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1113380 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1113380 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1113380 # number of overall misses +system.cpu.icache.overall_misses::total 1113380 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15333448488 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15333448488 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15333448488 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15333448488 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15333448488 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15333448488 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9012981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9012981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9012981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9012981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9012981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9012981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.981253 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13771.981253 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13771.981253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13771.981253 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13782 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.664384 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.485149 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61527 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61527 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61527 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61527 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61527 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61527 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1057257 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1057257 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1057257 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1057257 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1057257 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1057257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12498307487 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12498307487 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12498307487 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12498307487 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12498307487 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12498307487 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11821.446902 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11821.446902 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60842 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60842 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60842 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60842 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60842 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60842 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052538 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1052538 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1052538 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1052538 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1052538 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1052538 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12613347488 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12613347488 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12613347488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12613347488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12613347488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12613347488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.745469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.745469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9287 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.016215 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 26989 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9300 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.902043 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102704183500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016215 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376013 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376013 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27015 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27015 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9783 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.014217 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 28141 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9798 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.872117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5106728958500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.014217 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375889 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375889 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28140 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 28140 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27017 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27017 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27017 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27017 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10179 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10179 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10179 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10179 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10179 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10179 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 111301500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 111301500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 111301500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 111301500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 111301500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 111301500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37194 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 37194 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28142 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 28142 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28142 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 28142 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10689 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10689 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10689 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10689 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10689 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10689 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118046500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118046500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118046500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 118046500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118046500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 118046500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38829 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38829 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37196 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 37196 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37196 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 37196 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.273673 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.273673 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.273658 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.273658 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.273658 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.273658 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10934.423814 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10934.423814 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10934.423814 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10934.423814 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38831 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38831 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38831 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38831 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275284 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275284 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275270 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.275270 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275270 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.275270 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11043.736552 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11043.736552 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11043.736552 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11043.736552 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,78 +720,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10179 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10179 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10179 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10179 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10179 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10179 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90943500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90943500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90943500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90943500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90943500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90943500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273673 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273673 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273658 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273658 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8934.423814 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10689 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10689 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10689 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10689 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10689 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10689 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96668500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96668500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96668500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96668500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96668500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96668500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275284 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275284 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275270 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275270 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9043.736552 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 108224 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.929654 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137412 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 108239 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.269524 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100455706500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.929654 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808103 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.808103 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137417 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137417 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137417 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137417 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137417 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137417 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109249 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 109249 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109249 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 109249 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109249 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 109249 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1361810000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1361810000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1361810000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1361810000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1361810000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1361810000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 246666 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 246666 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 246666 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 246666 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 246666 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 246666 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442903 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442903 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442903 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442903 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442903 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442903 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.194189 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.194189 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.194189 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.194189 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 108113 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.301181 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 134692 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 108129 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.245660 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100502305500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.301181 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.831324 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.831324 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134692 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 134692 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134692 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 134692 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134692 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 134692 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109183 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 109183 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109183 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 109183 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109183 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 109183 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1366356000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1366356000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1366356000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1366356000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1366356000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1366356000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243875 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 243875 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243875 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 243875 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243875 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 243875 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447701 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447701 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447701 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447701 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447701 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447701 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12514.365790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12514.365790 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12514.365790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12514.365790 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -800,146 +800,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 34685 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 34685 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109249 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109249 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109249 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 109249 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109249 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 109249 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1143312000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1143312000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1143312000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442903 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442903 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442903 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.194189 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35577 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35577 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109183 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109183 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109183 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 109183 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109183 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 109183 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1147990000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1147990000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1147990000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447701 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447701 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447701 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10514.365790 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1662857 # number of replacements -system.cpu.dcache.tagsinuse 511.994597 # Cycle average of tags in use -system.cpu.dcache.total_refs 19099158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1663369 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.482214 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994597 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11001158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11001158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8092803 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8092803 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19093961 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19093961 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19093961 # number of overall hits -system.cpu.dcache.overall_hits::total 19093961 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2250786 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2250786 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 319407 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 319407 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2570193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2570193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2570193 # number of overall misses -system.cpu.dcache.overall_misses::total 2570193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32047872500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32047872500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644777995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9644777995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41692650495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41692650495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41692650495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41692650495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13251944 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13251944 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8412210 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8412210 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21664154 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21664154 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21664154 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21664154 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169846 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169846 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037969 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037969 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118638 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118638 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118638 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118638 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14238.524898 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14238.524898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30195.887989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30195.887989 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16221.603006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16221.603006 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397855 # number of cycles access was blocked +system.cpu.dcache.replacements 1659590 # number of replacements +system.cpu.dcache.tagsinuse 511.997640 # Cycle average of tags in use +system.cpu.dcache.total_refs 19085008 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1660102 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.496286 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997640 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10993134 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10993134 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8086930 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8086930 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19080064 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9628285992 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9628285992 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41750993992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41750993992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41750993992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41750993992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13228208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13228208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8404998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8404998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21633206 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21633206 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21633206 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21633206 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.168963 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037843 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118020 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118020 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118020 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118020 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14372.100432 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14372.100432 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30271.155828 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30271.155828 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16352.789618 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16352.789618 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 398716 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42426 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.325965 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397916 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1564276 # number of writebacks -system.cpu.dcache.writebacks::total 1564276 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 877119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 877119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25009 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25009 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 902128 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 902128 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 902128 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 902128 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1373667 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1373667 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294398 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294398 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1668065 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1668065 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1668065 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1668065 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17358648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17358648500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800545995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800545995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26159194495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26159194495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26159194495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26159194495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296699500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296699500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470652500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470652500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103658 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103658 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034997 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034997 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076997 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076997 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26244195992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26244195992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26244195992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97297948500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97297948500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473076000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473076000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771024500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771024500 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 7601 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1054724 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1662694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2826137 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000465 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000789 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015898 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026763 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021117 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.921494 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.921494 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 105752 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47411.764478 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52710.068613 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51060.040674 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10273.896844 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10273.896844 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38410.144154 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38410.144154 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16848 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36690 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 53598 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3625 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3625 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132809 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132809 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16848 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169499 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 186407 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16848 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169499 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186407 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4003602 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 370512 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964285581 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2065462567 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3034122262 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37079107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37079107 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200762570 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200762570 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4003602 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 370512 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964285581 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7266225137 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8234884832 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4003602 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 370512 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964285581 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7266225137 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8234884832 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188560000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188560000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310705000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310705000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499265000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499265000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026775 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915404 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915404 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066117 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066117 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57234.424323 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56294.973208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56608.870891 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10228.719172 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10228.719172 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39159.714854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39159.714854 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 3f5c092bf..e72c9ec7f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.204982 # Number of seconds simulated -sim_ticks 5204982293000 # Number of ticks simulated -final_tick 5204982293000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.204983 # Number of seconds simulated +sim_ticks 5204982530500 # Number of ticks simulated +final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233342 # Simulator instruction rate (inst/s) -host_op_rate 447673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11247967547 # Simulator tick rate (ticks/s) -host_mem_usage 849540 # Number of bytes of host memory used -host_seconds 462.75 # Real time elapsed on the host -sim_insts 107978732 # Number of instructions simulated -sim_ops 207159910 # Number of ops (including micro ops) simulated +host_inst_rate 181134 # Simulator instruction rate (inst/s) +host_op_rate 347511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8731335326 # Simulator tick rate (ticks/s) +host_mem_usage 804468 # Number of bytes of host memory used +host_seconds 596.13 # Real time elapsed on the host +sim_insts 107979054 # Number of instructions simulated +sim_ops 207160582 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 864448872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 69078677 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 864449224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 69078733 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 160958728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27339153 # Number of bytes read from this memory -system.physmem.bytes_read::total 1122193510 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 864448872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 160958728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1025407600 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 160961632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27339818 # Number of bytes read from this memory +system.physmem.bytes_read::total 1122197487 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 864449224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 160961632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1025410856 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 21309608 # Number of bytes written to this memory -system.physmem.bytes_written::total 72643471 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 21309908 # Number of bytes written to this memory +system.physmem.bytes_written::total 72643771 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 108056109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 12053051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 108056153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 12053065 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 20119841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4057514 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144328941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 20120204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4057615 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144329463 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2934421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 10106666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2934464 # Number of write requests responded to by this memory +system.physmem.num_writes::total 10106709 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 166081040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13271645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 166081100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13271655 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30923972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5252497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 215599871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 166081040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30923972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197005012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30924529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5252624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 215600625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 166081100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30924529 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197005629 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 4094079 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13956526 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 4094136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13956583 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 166081040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 22559427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 166081100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 22559437 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30923972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 9346576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 229556397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30924529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 229557208 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 810 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47248 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 48918 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 51840 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize() @@ -82,40 +82,40 @@ system.physmem.bytesConsumedWr 2991104 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 298 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 96 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 144 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 3168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 3232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 3120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 3096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 2640 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2992 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 96 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2848 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 3008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 3056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2848 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 63181906000 # Total gap between requests +system.physmem.numWrRetry 1670 # Number of times wr buffer was full causing retry +system.physmem.totGap 63182142000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -131,7 +131,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46736 # categorize write packet sizes +system.physmem.writePktSize::6 48406 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -176,15 +176,15 @@ system.physmem.rdQLenPdf::29 2 # Wh system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see @@ -199,37 +199,37 @@ system.physmem.wrQLenPdf::19 2032 # Wh system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 34586744 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 44980744 # Sum of mem lat for all requests -system.physmem.totBusLat 3240000 # Total cycles spent in databus access -system.physmem.totBankLat 7154000 # Total cycles spent in bank access -system.physmem.avgQLat 42699.68 # Average queueing delay per request -system.physmem.avgBankLat 8832.10 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55531.78 # Average memory access latency +system.physmem.totQLat 40946729 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests +system.physmem.totBusLat 4050000 # Total cycles spent in databus access +system.physmem.totBankLat 7548750 # Total cycles spent in bank access +system.physmem.avgQLat 50551.52 # Average queueing delay per request +system.physmem.avgBankLat 9319.44 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 64870.96 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.15 # Average write queue length over time -system.physmem.readRowHits 716 # Number of row buffer hits during reads -system.physmem.writeRowHits 45919 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.25 # Row buffer hit rate for writes -system.physmem.avgGap 1328858.49 # Average gap between requests +system.physmem.readRowHits 696 # Number of row buffer hits during reads +system.physmem.writeRowHits 45224 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes +system.physmem.avgGap 1328863.46 # Average gap between requests system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -290,50 +290,50 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.numCycles 10407785201 # number of cpu cycles simulated +system.cpu0.numCycles 10407785676 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 92551705 # Number of instructions committed -system.cpu0.committedOps 178518504 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 168457719 # Number of integer alu accesses +system.cpu0.committedInsts 92551747 # Number of instructions committed +system.cpu0.committedOps 178518572 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 168457773 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16414006 # number of instructions that are conditional controls -system.cpu0.num_int_insts 168457719 # number of integer instructions +system.cpu0.num_conditional_control_insts 16414014 # number of instructions that are conditional controls +system.cpu0.num_int_insts 168457773 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 415888508 # number of times the integer registers were read -system.cpu0.num_int_register_writes 210334532 # number of times the integer registers were written +system.cpu0.num_int_register_reads 415888554 # number of times the integer registers were read +system.cpu0.num_int_register_writes 210334552 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 20039545 # number of memory refs -system.cpu0.num_load_insts 12899818 # Number of load instructions +system.cpu0.num_mem_refs 20039559 # number of memory refs +system.cpu0.num_load_insts 12899832 # Number of load instructions system.cpu0.num_store_insts 7139727 # Number of store instructions -system.cpu0.num_idle_cycles 9669886063.125444 # Number of idle cycles -system.cpu0.num_busy_cycles 737899137.874556 # Number of busy cycles +system.cpu0.num_idle_cycles 9669887298.959074 # Number of idle cycles +system.cpu0.num_busy_cycles 737898377.040926 # Number of busy cycles system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10409964586 # number of cpu cycles simulated +system.cpu1.numCycles 10409965061 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15427027 # Number of instructions committed -system.cpu1.committedOps 28641406 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 28123113 # Number of integer alu accesses +system.cpu1.committedInsts 15427307 # Number of instructions committed +system.cpu1.committedOps 28642010 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 28123688 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1978272 # number of instructions that are conditional controls -system.cpu1.num_int_insts 28123113 # number of integer instructions +system.cpu1.num_conditional_control_insts 1978312 # number of instructions that are conditional controls +system.cpu1.num_int_insts 28123688 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 73027794 # number of times the integer registers were read -system.cpu1.num_int_register_writes 31865306 # number of times the integer registers were written +system.cpu1.num_int_register_reads 73029248 # number of times the integer registers were read +system.cpu1.num_int_register_writes 31865943 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 7025055 # number of memory refs -system.cpu1.num_load_insts 4066664 # Number of load instructions -system.cpu1.num_store_insts 2958391 # Number of store instructions -system.cpu1.num_idle_cycles 10280021112.934025 # Number of idle cycles -system.cpu1.num_busy_cycles 129943473.065975 # Number of busy cycles +system.cpu1.num_mem_refs 7025199 # number of memory refs +system.cpu1.num_load_insts 4066765 # Number of load instructions +system.cpu1.num_store_insts 2958434 # Number of store instructions +system.cpu1.num_idle_cycles 10280018133.934025 # Number of idle cycles +system.cpu1.num_busy_cycles 129946927.065975 # Number of busy cycles system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 722ef4fea..7484e6ff9 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269661 # Number of seconds simulated -sim_ticks 269661304500 # Number of ticks simulated -final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269672 # Number of seconds simulated +sim_ticks 269671683500 # Number of ticks simulated +final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98682 # Simulator instruction rate (inst/s) -host_op_rate 98682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44214559 # Simulator tick rate (ticks/s) -host_mem_usage 273520 # Number of bytes of host memory used -host_seconds 6098.93 # Real time elapsed on the host +host_inst_rate 125294 # Simulator instruction rate (inst/s) +host_op_rate 125294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56139844 # Simulator tick rate (ticks/s) +host_mem_usage 224468 # Number of bytes of host memory used +host_seconds 4803.57 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6481138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1581 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1675 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 76 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 52 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 81 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269661252500 # Total gap between requests +system.physmem.totGap 269671631500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 17608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 364261179 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1024159179 # Sum of mem lat for all requests -system.physmem.totBusLat 105120000 # Total cycles spent in databus access -system.physmem.totBankLat 554778000 # Total cycles spent in bank access -system.physmem.avgQLat 13860.78 # Average queueing delay per request -system.physmem.avgBankLat 21110.27 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38971.05 # Average memory access latency +system.physmem.totQLat 384531397 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests +system.physmem.totBusLat 131400000 # Total cycles spent in databus access +system.physmem.totBankLat 580703750 # Total cycles spent in bank access +system.physmem.avgQLat 14632.09 # Average queueing delay per request +system.physmem.avgBankLat 22096.79 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 41728.89 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 17406 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes -system.physmem.avgGap 9874807.84 # Average gap between requests -system.cpu.branchPred.lookups 86405274 # Number of BP lookups -system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted +system.physmem.readRowHits 16315 # Number of row buffer hits during reads +system.physmem.writeRowHits 296 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes +system.physmem.avgGap 9875187.91 # Average gap between requests +system.cpu.branchPred.lookups 86405403 # Number of BP lookups +system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517568 # DTB read hits +system.cpu.dtb.read_hits 114517881 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520199 # DTB read accesses -system.cpu.dtb.write_hits 39453362 # DTB write hits +system.cpu.dtb.read_accesses 114520512 # DTB read accesses +system.cpu.dtb.write_hits 39453501 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455664 # DTB write accesses -system.cpu.dtb.data_hits 153970930 # DTB hits +system.cpu.dtb.write_accesses 39455803 # DTB write accesses +system.cpu.dtb.data_hits 153971382 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153975863 # DTB accesses -system.cpu.itb.fetch_hits 24997854 # ITB hits +system.cpu.dtb.data_accesses 153976315 # DTB accesses +system.cpu.itb.fetch_hits 24997849 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 24997876 # ITB accesses +system.cpu.itb.fetch_accesses 24997871 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,18 +234,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539322610 # number of cpu cycles simulated +system.cpu.numCycles 539343368 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004918560 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160193 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 154928367 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken). @@ -256,12 +256,12 @@ system.cpu.execution_unit.executions 412128439 # Nu system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535759910 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 295987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50789311 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488533299 # Number of cycles cpu stages are processed. -system.cpu.activity 90.582759 # Percentage of cycles cpu is active +system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed. +system.cpu.activity 90.579328 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -273,77 +273,77 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896098 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896098 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115950 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115950 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200593326 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338729284 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.806431 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228903212 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310419398 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.557275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197757745 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564865 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.332198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427944093 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378517 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.651557 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192521650 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346800960 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.303063 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.842734 # Cycle average of tags in use -system.cpu.icache.total_refs 24996820 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use +system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29236.046784 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.842734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356369 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356369 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24996820 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24996820 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24996820 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24996820 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24996820 # number of overall hits -system.cpu.icache.overall_hits::total 24996820 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits +system.cpu.icache.overall_hits::total 24996815 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses system.cpu.icache.overall_misses::total 1034 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 53126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 53126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 53126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 53126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 53126500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24997854 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24997854 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24997854 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24997854 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24997854 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51379.593810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51379.593810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51379.593810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51379.593810 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 187 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -359,38 +359,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 855 system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43645500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43645500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43645500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43645500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51047.368421 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51047.368421 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51047.368421 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.132168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.623478 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.963213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.545477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014512 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -415,17 +415,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42639500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 472401500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515041000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1150527000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1622928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1665568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42639500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1622928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1665568000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -450,17 +450,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50700.951249 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114521.575758 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103713.451470 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53944.439235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63344.032859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50700.951249 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63761.776608 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63344.032859 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,17 +482,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32024355 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418973423 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 450997778 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 880714009 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32024355 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1299687432 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1331711787 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32024355 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1299687432 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1331711787 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -504,51 +504,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38078.900119 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101569.314667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 90817.111961 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41293.792620 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38078.900119 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51062.249322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50646.983608 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.419207 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786016 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use +system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306286 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 334129000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.419207 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120628 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120628 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665388 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665388 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786016 # number of overall hits -system.cpu.dcache.overall_hits::total 151786016 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785933 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785933 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179347 # number of overall misses -system.cpu.dcache.overall_misses::total 2179347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5991137000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22893915500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28885052500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28885052500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28885052500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits +system.cpu.dcache.overall_hits::total 151786159 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses +system.cpu.dcache.overall_misses::total 2179204 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -557,40 +557,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014155 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014155 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014155 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014155 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15228.581088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15228.581088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12819.022606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12819.022606 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13253.994201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13253.994201 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167214 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 552 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5590 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.913059 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192182 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192182 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531770 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2645576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3734758000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6380334500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6380334500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6380334500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.897611 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14694.341820 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14010.550182 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14010.550182 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 393ed8f87..fd6611525 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133779 # Number of seconds simulated -sim_ticks 133778696500 # Number of ticks simulated -final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133806 # Number of seconds simulated +sim_ticks 133806308500 # Number of ticks simulated +final_tick 133806308500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160169 # Simulator instruction rate (inst/s) -host_op_rate 160169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37887208 # Simulator tick rate (ticks/s) -host_mem_usage 273648 # Number of bytes of host memory used -host_seconds 3530.97 # Real time elapsed on the host +host_inst_rate 271409 # Simulator instruction rate (inst/s) +host_op_rate 271409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64213833 # Simulator tick rate (ticks/s) +host_mem_usage 226532 # Number of bytes of host memory used +host_seconds 2083.76 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636416 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67008 # Number of bytes written to this memory -system.physmem.bytes_written::total 67008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26520 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1047 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 454960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12232262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12687222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 500887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 500887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 454960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12232262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13188109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26520 # Total number of read requests seen -system.physmem.writeReqs 1047 # Total number of write requests seen -system.physmem.cpureqs 27567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697280 # Total number of bytes read from memory -system.physmem.bytesWritten 67008 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697280 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67008 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636352 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67200 # Number of bytes written to this memory +system.physmem.bytes_written::total 67200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25568 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26529 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 459649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12229259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12688908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 459649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 502218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 502218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 459649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12229259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13191127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26529 # Total number of read requests seen +system.physmem.writeReqs 1050 # Total number of write requests seen +system.physmem.cpureqs 27579 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697856 # Total number of bytes read from memory +system.physmem.bytesWritten 67200 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 67200 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1681 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1568 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1555 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1678 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 55 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 75 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 79 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 84 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 54 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 57 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 48 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 62 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 78 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 69 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1679 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133778628000 # Total gap between requests +system.physmem.totGap 133806263000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26520 # Categorize read packet sizes +system.physmem.readPktSize::6 26529 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1047 # categorize write packet sizes +system.physmem.writePktSize::6 1050 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10502 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 8850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 46 # What write queue length does an incoming req see @@ -150,9 +150,9 @@ system.physmem.wrQLenPdf::8 46 # Wh system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 650833420 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1266537420 # Sum of mem lat for all requests -system.physmem.totBusLat 106020000 # Total cycles spent in databus access -system.physmem.totBankLat 509684000 # Total cycles spent in bank access -system.physmem.avgQLat 24555.12 # Average queueing delay per request -system.physmem.avgBankLat 19229.73 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 47784.85 # Average memory access latency +system.physmem.totQLat 648232398 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1339932398 # Sum of mem lat for all requests +system.physmem.totBusLat 132570000 # Total cycles spent in databus access +system.physmem.totBankLat 559130000 # Total cycles spent in bank access +system.physmem.avgQLat 24448.68 # Average queueing delay per request +system.physmem.avgBankLat 21088.10 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 50536.79 # Average memory access latency system.physmem.avgRdBW 12.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 12.69 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.37 # Average write queue length over time -system.physmem.readRowHits 18044 # Number of row buffer hits during reads -system.physmem.writeRowHits 53 # Number of row buffer hits during writes -system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes -system.physmem.avgGap 4852854.06 # Average gap between requests -system.cpu.branchPred.lookups 76440222 # Number of BP lookups -system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits +system.physmem.avgWrQLen 10.03 # Average write queue length over time +system.physmem.readRowHits 16972 # Number of row buffer hits during reads +system.physmem.writeRowHits 273 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.00 # Row buffer hit rate for writes +system.physmem.avgGap 4851744.55 # Average gap between requests +system.cpu.branchPred.lookups 76500721 # Number of BP lookups +system.cpu.branchPred.condPredicted 70919742 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2718676 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43116993 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41952631 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.299529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1606312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122603551 # DTB read hits -system.cpu.dtb.read_misses 28565 # DTB read misses +system.cpu.dtb.read_hits 122623794 # DTB read hits +system.cpu.dtb.read_misses 28860 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122632116 # DTB read accesses -system.cpu.dtb.write_hits 40753368 # DTB write hits -system.cpu.dtb.write_misses 25574 # DTB write misses +system.cpu.dtb.read_accesses 122652654 # DTB read accesses +system.cpu.dtb.write_hits 40761180 # DTB write hits +system.cpu.dtb.write_misses 25673 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40778942 # DTB write accesses -system.cpu.dtb.data_hits 163356919 # DTB hits -system.cpu.dtb.data_misses 54139 # DTB misses +system.cpu.dtb.write_accesses 40786853 # DTB write accesses +system.cpu.dtb.data_hits 163384974 # DTB hits +system.cpu.dtb.data_misses 54533 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163411058 # DTB accesses -system.cpu.itb.fetch_hits 65475592 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 163439507 # DTB accesses +system.cpu.itb.fetch_hits 65534932 # ITB hits +system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65475634 # ITB accesses +system.cpu.itb.fetch_accesses 65534973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267557394 # number of cpu cycles simulated +system.cpu.numCycles 267612618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43537428 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117782486 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11617306 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73490715 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 67186400 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699453099 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76500721 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43558943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117852914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11666249 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73358963 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65475592 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 928038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.615488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.444547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65534932 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 934826 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.616594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444810 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149491842 55.93% 55.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10342090 3.87% 59.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847639 4.43% 64.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10563390 3.95% 68.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7011808 2.62% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2869024 1.07% 71.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3576964 1.34% 73.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3101400 1.16% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68470171 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149461419 55.91% 55.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10349982 3.87% 59.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11850266 4.43% 64.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10577716 3.96% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7012506 2.62% 70.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2870690 1.07% 71.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3579816 1.34% 73.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3108437 1.16% 74.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68503501 25.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267274328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285697 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.612721 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84240613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57793701 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102635866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13724657 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8879491 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3873839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 920 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691093913 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3105 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8879491 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92211740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12790279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103054645 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50336932 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 680961604 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 408 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38688874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5430085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520709674 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 896990234 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 896987596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2638 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267314333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285864 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.613678 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84322022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57655855 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102751859 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13670665 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8913932 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3876852 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 942 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691462372 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8913932 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92304341 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12773232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103106270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50215212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681285072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 434 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38522944 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5472741 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520920645 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897379043 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897376453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2590 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 56854785 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 64 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 69 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112289485 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 126970724 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42377686 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14852387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10147583 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621083354 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604563100 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299815 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 54897951 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29938787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267274328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.261957 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.823661 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57065756 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 66 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 71 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112077327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127005785 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42387861 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14833107 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10089887 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621266103 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604722021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299730 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55073821 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 30009810 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267314333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.262213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.825151 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52499760 19.64% 19.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55875325 20.91% 40.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53442699 20.00% 60.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36269586 13.57% 74.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31423380 11.76% 85.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23799839 8.90% 94.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9996979 3.74% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3415050 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 551710 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52513972 19.65% 19.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55954300 20.93% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53424383 19.99% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36299246 13.58% 74.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31212895 11.68% 85.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23807225 8.91% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10138155 3.79% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3408674 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 555483 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267274328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267314333 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2734710 70.93% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 35 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729519 18.92% 89.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 391400 10.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2798552 71.38% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 727516 18.56% 89.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394572 10.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439055623 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7072 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124323040 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41177317 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439175234 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7035 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124352577 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41187127 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604563100 # Type of FU issued -system.cpu.iq.rate 2.259564 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3855664 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006378 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480552206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 675984537 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596489873 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3801 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2284 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1738 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608416848 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1916 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12282855 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604722021 # Type of FU issued +system.cpu.iq.rate 2.259692 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3920679 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006483 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480975025 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676343136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596595322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3759 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1723 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608640802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1898 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12279325 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12456682 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5518 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926365 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12491743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36092 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5478 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2936540 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 52889 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6432 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 54776 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8879491 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1456554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 192142 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 663913486 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1691538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 126970724 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42377686 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 144242 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7408 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5518 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1333964 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1804152 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3138116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599464075 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122632263 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5099025 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8913932 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1438086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 192048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664143136 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1694587 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127005785 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42387861 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 59 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 143884 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7497 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5478 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342912 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1811100 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3154012 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599591446 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122652830 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5130575 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42830076 # number of nop insts executed -system.cpu.iew.exec_refs 163429760 # number of memory reference insts executed -system.cpu.iew.exec_branches 66623337 # Number of branches executed -system.cpu.iew.exec_stores 40797497 # Number of stores executed -system.cpu.iew.exec_rate 2.240506 # Inst execution rate -system.cpu.iew.wb_sent 597426155 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596491611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415927297 # num instructions producing a value -system.cpu.iew.wb_consumers 530215795 # num instructions consuming a value +system.cpu.iew.exec_nop 42876974 # number of nop insts executed +system.cpu.iew.exec_refs 163458157 # number of memory reference insts executed +system.cpu.iew.exec_branches 66641389 # Number of branches executed +system.cpu.iew.exec_stores 40805327 # Number of stores executed +system.cpu.iew.exec_rate 2.240520 # Inst execution rate +system.cpu.iew.wb_sent 597536756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596597045 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415962909 # num instructions producing a value +system.cpu.iew.wb_consumers 530370743 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.229397 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784449 # average fanout of values written-back +system.cpu.iew.wb_rate 2.229331 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784287 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 61932723 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62162261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2705240 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258394837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.329214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.691172 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2717793 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258400401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.329164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.692856 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79550578 30.79% 30.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72525012 28.07% 58.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25515345 9.87% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9289171 3.59% 72.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10288497 3.98% 76.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21029047 8.14% 84.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6874256 2.66% 87.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3694459 1.43% 88.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29628472 11.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79574518 30.80% 30.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72566023 28.08% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25599330 9.91% 68.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9197400 3.56% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10258446 3.97% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20921268 8.10% 84.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6836400 2.65% 87.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3734572 1.45% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29712444 11.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258394837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258400401 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29628472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29712444 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892491662 # The number of ROB reads -system.cpu.rob.rob_writes 1336472901 # The number of ROB writes -system.cpu.timesIdled 34286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 283066 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892642792 # The number of ROB reads +system.cpu.rob.rob_writes 1336966756 # The number of ROB writes +system.cpu.timesIdled 34291 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298285 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.473090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.473090 # CPI: Total CPI of All Threads -system.cpu.ipc 2.113761 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.113761 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844970192 # number of integer regfile reads -system.cpu.int_regfile_writes 490533624 # number of integer regfile writes -system.cpu.fp_regfile_reads 397 # number of floating regfile reads +system.cpu.cpi 0.473188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473188 # CPI: Total CPI of All Threads +system.cpu.ipc 2.113325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.113325 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845166386 # number of integer regfile reads +system.cpu.int_regfile_writes 490617161 # number of integer regfile writes +system.cpu.fp_regfile_reads 389 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 36 # number of replacements -system.cpu.icache.tagsinuse 825.012562 # Cycle average of tags in use -system.cpu.icache.total_refs 65474211 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67848.923316 # Average number of references to valid blocks. +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 825.582407 # Cycle average of tags in use +system.cpu.icache.total_refs 65533545 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 979 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 66939.269663 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.012562 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.402838 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.402838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65474211 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65474211 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65474211 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65474211 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65474211 # number of overall hits -system.cpu.icache.overall_hits::total 65474211 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses -system.cpu.icache.overall_misses::total 1381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68875500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68875500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68875500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68875500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68875500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65475592 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65475592 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65475592 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65475592 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65475592 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 825.582407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.403116 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.403116 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65533545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65533545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65533545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65533545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65533545 # number of overall hits +system.cpu.icache.overall_hits::total 65533545 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1386 # number of overall misses +system.cpu.icache.overall_misses::total 1386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 74542000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 74542000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 74542000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 74542000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 74542000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65534931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65534931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65534931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65534931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65534931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.642288 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49873.642288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.642288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49873.642288 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53782.106782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53782.106782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53782.106782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53782.106782 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 416 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 416 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 416 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 416 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 416 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 416 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50216500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50216500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50216500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50216500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 407 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 407 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 407 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 407 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 407 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 407 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 979 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 979 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 979 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 979 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54570500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54570500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54570500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54570500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54570500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54570500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52037.823834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52037.823834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52037.823834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52037.823834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55741.062308 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55741.062308 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55741.062308 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55741.062308 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1079 # number of replacements -system.cpu.l2cache.tagsinuse 22916.104559 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547186 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23511 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.273617 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1082 # number of replacements +system.cpu.l2cache.tagsinuse 22917.401709 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547365 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23522 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.270343 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21469.480813 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 814.509586 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 632.114161 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655197 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024857 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019291 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699344 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 206252 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 206266 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 445099 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 445099 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43129.569199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62608.067702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61902.468657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 461041 # number of replacements -system.cpu.dcache.tagsinuse 4090.869171 # Cycle average of tags in use -system.cpu.dcache.total_refs 146891319 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465137 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.802267 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 305775000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.869171 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998747 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109242892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109242892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37648409 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37648409 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 18 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 18 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146891301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146891301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146891301 # number of overall hits -system.cpu.dcache.overall_hits::total 146891301 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1026587 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1026587 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1802912 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1802912 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2829499 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2829499 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2829499 # number of overall misses -system.cpu.dcache.overall_misses::total 2829499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15441177000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25867331616 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 28500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41308508616 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41308508616 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41308508616 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110269479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110269479 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 460939 # number of replacements +system.cpu.dcache.tagsinuse 4090.899850 # Cycle average of tags in use +system.cpu.dcache.total_refs 146914514 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 465035 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.921412 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 301771000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.899850 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998755 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109265934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109265934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146914497 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146914497 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146914497 # number of overall hits +system.cpu.dcache.overall_hits::total 146914497 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1025246 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1025246 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802758 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802758 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828004 # number of overall misses +system.cpu.dcache.overall_misses::total 2828004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15342477500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26169777829 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 37000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41512255329 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41512255329 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41512255329 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110291180 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110291180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 21 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 21 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149720800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149720800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149720800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149720800 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.142857 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018899 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15041.274631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15041.274631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14347.528674 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14347.528674 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14599.230682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14599.230682 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 277266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 17305 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 149742501 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149742501 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149742501 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149742501 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009296 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045696 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.190476 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018886 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018886 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018886 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018886 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14964.679209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14964.679209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14516.522922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14516.522922 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14678.994559 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14678.994559 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 301355 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2673 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17784 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.022306 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.945288 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 243 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 445099 # number of writebacks -system.cpu.dcache.writebacks::total 445099 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 816026 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 816026 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1548336 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2364362 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2364362 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2364362 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210561 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210561 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 465137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 465137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 465137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2703972000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4046409990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6750381990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6750381990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 445006 # number of writebacks +system.cpu.dcache.writebacks::total 445006 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 814778 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 814778 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548191 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362969 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362969 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362969 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210468 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210468 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254567 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254567 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 465035 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 465035 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 465035 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697344500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097543997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6794888497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6794888497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003107 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003107 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12841.751321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15894.703311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14512.674739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14512.674739 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12815.936389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16096.131851 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14611.563639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14611.563639 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 08bc3f5b4..e289c0e8e 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164543 # Number of seconds simulated -sim_ticks 164543008000 # Number of ticks simulated -final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164572 # Number of seconds simulated +sim_ticks 164572262000 # Number of ticks simulated +final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116480 # Simulator instruction rate (inst/s) -host_op_rate 123082 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33621508 # Simulator tick rate (ticks/s) -host_mem_usage 289348 # Number of bytes of host memory used -host_seconds 4893.98 # Real time elapsed on the host +host_inst_rate 164809 # Simulator instruction rate (inst/s) +host_op_rate 174150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47579904 # Simulator tick rate (ticks/s) +host_mem_usage 241928 # Number of bytes of host memory used +host_seconds 3458.86 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1700992 # Number of bytes read from this memory -system.physmem.bytes_read::total 1747904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162560 # Number of bytes written to this memory -system.physmem.bytes_written::total 162560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26578 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2540 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 285105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10337674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10622779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 285105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 987948 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 987948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 285105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10337674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11610727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27312 # Total number of read requests seen -system.physmem.writeReqs 2540 # Total number of write requests seen -system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1747904 # Total number of bytes read from memory -system.physmem.bytesWritten 162560 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1747904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162560 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701952 # Number of bytes read from this memory +system.physmem.bytes_read::total 1749376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162432 # Number of bytes written to this memory +system.physmem.bytes_written::total 162432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26593 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27334 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2538 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2538 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 288165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10341670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10629835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 288165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 986995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 986995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 288165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10341670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11616830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27336 # Total number of read requests seen +system.physmem.writeReqs 2538 # Total number of write requests seen +system.physmem.cpureqs 29874 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1749376 # Total number of bytes read from memory +system.physmem.bytesWritten 162432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1749376 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162432 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1673 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis +system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1724 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1686 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164542992000 # Total gap between requests +system.physmem.totGap 164572246000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27312 # Categorize read packet sizes +system.physmem.readPktSize::6 27336 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 2540 # categorize write packet sizes +system.physmem.writePktSize::6 2538 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,16 +138,16 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 954202972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1658730972 # Sum of mem lat for all requests -system.physmem.totBusLat 109248000 # Total cycles spent in databus access -system.physmem.totBankLat 595280000 # Total cycles spent in bank access -system.physmem.avgQLat 34937.13 # Average queueing delay per request -system.physmem.avgBankLat 21795.55 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 60732.68 # Average memory access latency -system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 921366434 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests +system.physmem.totBusLat 136675000 # Total cycles spent in databus access +system.physmem.totBankLat 614033750 # Total cycles spent in bank access +system.physmem.avgQLat 33705.24 # Average queueing delay per request +system.physmem.avgBankLat 22462.46 # Average bank access latency per request +system.physmem.avgBusLat 4999.82 # Average bus latency per request +system.physmem.avgMemAccLat 61167.51 # Average memory access latency +system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.99 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 7.51 # Average write queue length over time -system.physmem.readRowHits 17750 # Number of row buffer hits during reads -system.physmem.writeRowHits 1096 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes -system.physmem.avgGap 5511958.73 # Average gap between requests -system.cpu.branchPred.lookups 85130885 # Number of BP lookups -system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits +system.physmem.avgWrQLen 7.98 # Average write queue length over time +system.physmem.readRowHits 16887 # Number of row buffer hits during reads +system.physmem.writeRowHits 1046 # Number of row buffer hits during writes +system.physmem.readRowHitRate 61.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes +system.physmem.avgGap 5508878.82 # Average gap between requests +system.cpu.branchPred.lookups 85156760 # Number of BP lookups +system.cpu.branchPred.condPredicted 79937555 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2342179 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47221599 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46882126 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.281107 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1427254 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1090 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,134 +244,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329086017 # number of cpu cycles simulated +system.cpu.numCycles 329144525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48288239 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129602885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13082707 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119327277 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67069040 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754631 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165288 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 68500133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666893560 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85156760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48309380 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129633878 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13101459 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119325440 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 311 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67084243 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755399 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.165364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193928 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198528126 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20911347 6.37% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4965496 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14342607 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8889042 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9432606 2.87% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4398382 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5787527 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60875647 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198557643 60.50% 60.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20911639 6.37% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4968720 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14346044 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8890886 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9446619 2.88% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4399795 1.34% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788532 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60881414 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328130780 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258689 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92913811 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96211222 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107901766 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20387668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10716313 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1507 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703148359 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5732 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10716313 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107108772 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14420824 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39598 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114018818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81826455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694730633 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59350869 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20332423 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 690 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721206841 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230143140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230143012 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328191292 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258721 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.026142 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92969239 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96174869 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107931491 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20385682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10730011 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4738020 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1580 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703286632 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5586 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10730011 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107159029 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14373843 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114052351 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81836170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694854437 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59359193 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20344162 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721334030 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230715755 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230715627 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93789468 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1631 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1577 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170614097 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172186244 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80451329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21497797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28523197 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679922328 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2842 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645571900 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1371428 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77382290 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193030922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 138 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328130780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967423 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726248 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93916657 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1707 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1652 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170570480 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172204690 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80467392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21722432 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29158581 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 680011931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645607270 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1367531 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77472778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193408701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 215 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328191292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68155781 20.77% 20.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85368264 26.02% 46.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75828661 23.11% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40814489 12.44% 82.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28806063 8.78% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14910916 4.54% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5593541 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6461751 1.97% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2191314 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328130780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328191292 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 217275 5.77% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690091 71.47% 77.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 856746 22.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 216791 5.75% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2693843 71.39% 77.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 862775 22.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403353378 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6568 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403382320 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6572 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165552451 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76659500 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165566556 25.65% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76651819 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645571900 # Type of FU issued -system.cpu.iq.rate 1.961712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3764112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005831 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624410084 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757319559 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637543970 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645607270 # Type of FU issued +system.cpu.iq.rate 1.961470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3773409 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005845 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624546736 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757499752 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637553210 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649335992 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649380659 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30371258 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30362769 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23233651 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 124604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10230316 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23252097 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12371 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10246379 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12884 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32539 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12896 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10716313 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 798788 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679928215 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 686727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172186244 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80451329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1514 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33028 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15856 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1355593 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1460304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2815897 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641504035 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163487420 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4067865 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10730011 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 795888 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 91006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 680017934 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 687807 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172204690 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80467392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32670 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15237 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12371 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1357657 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460843 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2818500 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641514820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163491606 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4092450 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3045 # number of nop insts executed -system.cpu.iew.exec_refs 239375677 # number of memory reference insts executed -system.cpu.iew.exec_branches 74669000 # Number of branches executed -system.cpu.iew.exec_stores 75888257 # Number of stores executed -system.cpu.iew.exec_rate 1.949351 # Inst execution rate -system.cpu.iew.wb_sent 638951120 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637543986 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418515101 # num instructions producing a value -system.cpu.iew.wb_consumers 649819096 # num instructions consuming a value +system.cpu.iew.exec_nop 3084 # number of nop insts executed +system.cpu.iew.exec_refs 239364786 # number of memory reference insts executed +system.cpu.iew.exec_branches 74674061 # Number of branches executed +system.cpu.iew.exec_stores 75873180 # Number of stores executed +system.cpu.iew.exec_rate 1.949037 # Inst execution rate +system.cpu.iew.wb_sent 638961643 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637553226 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418732313 # num instructions producing a value +system.cpu.iew.wb_consumers 650059572 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937317 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644049 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937001 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644145 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77576557 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77666777 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2337624 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317414467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897708 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237617 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2340669 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317461281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897428 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237399 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93227454 29.37% 29.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104339541 32.87% 62.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42982023 13.54% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8785495 2.77% 78.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25936003 8.17% 86.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12920810 4.07% 90.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7630828 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1171764 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20420549 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93255759 29.38% 29.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104348924 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42985847 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8791848 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25959048 8.18% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12901404 4.06% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7629324 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1168492 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20420635 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317414467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317461281 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,195 +487,195 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20420549 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20420635 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 976929705 # The number of ROB reads -system.cpu.rob.rob_writes 1370620821 # The number of ROB writes -system.cpu.timesIdled 41180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 955237 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977066653 # The number of ROB reads +system.cpu.rob.rob_writes 1370815087 # The number of ROB writes +system.cpu.timesIdled 44013 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 953233 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577292 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577292 # CPI: Total CPI of All Threads -system.cpu.ipc 1.732227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.732227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204271897 # number of integer regfile reads -system.cpu.int_regfile_writes 663022837 # number of integer regfile writes +system.cpu.cpi 0.577394 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577394 # CPI: Total CPI of All Threads +system.cpu.ipc 1.731919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.731919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204307958 # number of integer regfile reads +system.cpu.int_regfile_writes 663049374 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234769906 # number of misc regfile reads +system.cpu.misc_regfile_reads 234758339 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 58 # number of replacements -system.cpu.icache.tagsinuse 683.079303 # Cycle average of tags in use -system.cpu.icache.total_refs 67067899 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 817 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82090.451652 # Average number of references to valid blocks. +system.cpu.icache.replacements 66 # number of replacements +system.cpu.icache.tagsinuse 690.513263 # Cycle average of tags in use +system.cpu.icache.total_refs 67083102 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 830 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 80823.014458 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 683.079303 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.333535 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.333535 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67067899 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67067899 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67067899 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67067899 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67067899 # number of overall hits -system.cpu.icache.overall_hits::total 67067899 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 690.513263 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337165 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337165 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67083102 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67083102 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67083102 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67083102 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67083102 # number of overall hits +system.cpu.icache.overall_hits::total 67083102 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51270999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51270999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51270999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51270999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51270999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67069040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67069040 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67069040 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67069040 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67069040 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54478999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54478999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54478999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54478999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54478999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67084243 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67084243 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67084243 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67084243 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67084243 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44935.143734 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44935.143734 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44935.143734 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44935.143734 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47746.712533 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47746.712533 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47746.712533 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47746.712533 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.555556 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 322 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 322 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 322 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 322 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39128499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39128499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39128499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39128499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39128499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39128499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 309 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42177999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47775.945055 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47775.945055 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47775.945055 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47775.945055 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38041.822647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73057.202829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72117.459359 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 741 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4804 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5545 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21791 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26595 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27336 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149679 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627911476 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659061155 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310031171 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.088162 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440572 # number of replacements -system.cpu.dcache.tagsinuse 4091.500520 # Cycle average of tags in use -system.cpu.dcache.total_refs 197561073 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444668 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 444.288937 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 320822000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4091.500520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998901 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 131514845 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 131514845 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 66043576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 66043576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440669 # number of replacements +system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use +system.cpu.dcache.total_refs 197567614 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444765 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.206747 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314058000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.484070 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998897 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131523721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131523721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66041240 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66041240 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1324 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1324 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197558421 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197558421 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197558421 # number of overall hits -system.cpu.dcache.overall_hits::total 197558421 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3373955 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3373955 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 20 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 20 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3715753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3715753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3715753 # number of overall misses -system.cpu.dcache.overall_misses::total 3715753 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5154955000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40277017700 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 312000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45431972700 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45431972700 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45431972700 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131856643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131856643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 197564961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197564961 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197564961 # number of overall hits +system.cpu.dcache.overall_hits::total 197564961 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341919 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341919 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3376291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3376291 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3718210 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses +system.cpu.dcache.overall_misses::total 3718210 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1343 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1343 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201274174 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201274174 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201274174 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201274174 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048604 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.014892 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018461 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018461 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018461 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018461 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15081.875845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15081.875845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 11937.627414 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 11937.627414 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15600 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15600 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12226.854880 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12226.854880 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132982 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4828 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.543911 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201283171 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201283171 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201283171 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201283171 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002593 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048637 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016345 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018473 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.930261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421606 # number of writebacks -system.cpu.dcache.writebacks::total 421606 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144292 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3126791 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 20 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3271083 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3271083 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3271083 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247164 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444670 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2876994000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4061058256 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6938052256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6938052256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6938052256 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 421643 # number of writebacks +system.cpu.dcache.writebacks::total 421643 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144320 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144320 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3129122 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3273442 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3273442 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3273442 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197599 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197599 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247169 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247169 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003561 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14566.615698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16430.622000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15602.699206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15602.699206 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 6eebaa49a..a9ed274c0 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387280 # Number of seconds simulated -sim_ticks 387279743500 # Number of ticks simulated -final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387316 # Number of seconds simulated +sim_ticks 387315507500 # Number of ticks simulated +final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131929 # Simulator instruction rate (inst/s) -host_op_rate 132344 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36464205 # Simulator tick rate (ticks/s) -host_mem_usage 283820 # Number of bytes of host memory used -host_seconds 10620.82 # Real time elapsed on the host +host_inst_rate 205717 # Simulator instruction rate (inst/s) +host_op_rate 206366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56864239 # Simulator tick rate (ticks/s) +host_mem_usage 235456 # Number of bytes of host memory used +host_seconds 6811.23 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678400 # Number of bytes read from this memory -system.physmem.bytes_read::total 1754816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678528 # Number of bytes read from this memory +system.physmem.bytes_read::total 1755072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26227 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27423 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4333818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4531133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4333818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4949724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27420 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 197627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4333749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4531375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4333749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4949928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27424 # Total number of read requests seen system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1754816 # Total number of bytes read from memory +system.physmem.cpureqs 29957 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1755072 # Total number of bytes read from memory system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1754816 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1755072 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1698 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1769 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1746 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1685 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1621 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1744 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1697 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387279715500 # Total gap between requests +system.physmem.totGap 387315479500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27420 # Categorize read packet sizes +system.physmem.readPktSize::6 27424 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 8259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 7981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see @@ -161,8 +161,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,267 +171,267 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 724473296 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1405549296 # Sum of mem lat for all requests -system.physmem.totBusLat 109680000 # Total cycles spent in databus access -system.physmem.totBankLat 571396000 # Total cycles spent in bank access -system.physmem.avgQLat 26421.35 # Average queueing delay per request -system.physmem.avgBankLat 20838.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 51260.00 # Average memory access latency +system.physmem.totQLat 713274952 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1439334952 # Sum of mem lat for all requests +system.physmem.totBusLat 137120000 # Total cycles spent in databus access +system.physmem.totBankLat 588940000 # Total cycles spent in bank access +system.physmem.avgQLat 26009.15 # Average queueing delay per request +system.physmem.avgBankLat 21475.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52484.50 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.42 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.06 # Average write queue length over time -system.physmem.readRowHits 18324 # Number of row buffer hits during reads -system.physmem.writeRowHits 1098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes -system.physmem.avgGap 12929580.19 # Average gap between requests -system.cpu.branchPred.lookups 97757265 # Number of BP lookups -system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits +system.physmem.avgWrQLen 16.51 # Average write queue length over time +system.physmem.readRowHits 17585 # Number of row buffer hits during reads +system.physmem.writeRowHits 1048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.37 # Row buffer hit rate for writes +system.physmem.avgGap 12929047.62 # Average gap between requests +system.cpu.branchPred.lookups 97759655 # Number of BP lookups +system.cpu.branchPred.condPredicted 88050231 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3614520 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65786552 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65492883 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.553603 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1341 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774559488 # number of cpu cycles simulated +system.cpu.numCycles 774631016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65494758 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329201347 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20830567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263300608 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2484 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 164855721 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642251558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97759655 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65494224 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329204399 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20834739 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263342259 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2502 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161939590 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736919 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126792 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146705 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 161937023 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 736247 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126696 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445149348 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74062635 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37899346 4.89% 71.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9077460 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28106060 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18772938 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11486101 1.48% 80.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3791039 0.49% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146005768 18.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445193785 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062525 9.56% 67.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37899229 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9077552 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28106227 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772117 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485912 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3791430 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146009407 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774350695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120227 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 215923264 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214411776 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284212483 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42813992 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 16989180 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636523306 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 16989180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239767996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36725834 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52426044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302047092 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126394549 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625641256 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 163 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927570 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73422293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3124815 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356325471 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746325758 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712253189 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34072569 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774398184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126202 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.120044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 215922553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214452390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284209898 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42820116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16993227 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636550752 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16993227 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239771948 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36701097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52424917 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302039391 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126467604 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625687860 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30927407 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73464560 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3152152 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356365192 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746429093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712307786 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111555032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2644888 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2664020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271706062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436927389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179744218 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254493315 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83217297 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512489363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2610612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459355655 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53704 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109193723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130058810 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 366941 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774350695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884619 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431536 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2643942 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179754378 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254555015 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 82904621 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512542697 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2609193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459339312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53583 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109245499 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130204517 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 365522 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774398184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884482 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145647727 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184570267 23.84% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209695290 27.08% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131219118 16.95% 86.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70710319 9.13% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20417492 2.64% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8005951 1.03% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3903236 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181295 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145558409 18.80% 18.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184658706 23.85% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209828049 27.10% 69.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131187469 16.94% 86.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70686123 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20416273 2.64% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7987184 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3894628 0.50% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181343 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774350695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774398184 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 116724 6.93% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95410 5.66% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1152580 68.43% 81.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 319525 18.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 118946 7.04% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 95273 5.64% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1158517 68.57% 81.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 316903 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866464141 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866474644 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644770 0.18% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419120072 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171126672 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644797 0.18% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419098125 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171121746 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459355655 # Type of FU issued -system.cpu.iq.rate 1.884110 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1684239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001154 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3676971209 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615339802 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443231270 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17828739 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9193054 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8547507 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451917046 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9122848 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215321036 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459339312 # Type of FU issued +system.cpu.iq.rate 1.883915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1689639 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3676979008 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615425319 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443226704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17841022 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9210458 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8545776 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451900530 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9128421 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215265115 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34414546 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58846 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 246003 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12896076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34428392 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58884 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 245184 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12906236 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3349 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91624 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3305 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 101102 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 16989180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3081240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246114 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608786135 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4123964 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436927389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179744218 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2527628 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148187 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1651 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 246003 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2270880 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473539 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3744419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454037467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416573795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5318188 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16993227 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3018866 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 247688 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608835504 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4126277 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436941235 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179754378 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2526244 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 149012 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1899 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 245184 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2269311 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3742374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454021381 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416550474 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5317931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93686160 # number of nop insts executed -system.cpu.iew.exec_refs 587024674 # number of memory reference insts executed -system.cpu.iew.exec_branches 89036390 # Number of branches executed -system.cpu.iew.exec_stores 170450879 # Number of stores executed -system.cpu.iew.exec_rate 1.877244 # Inst execution rate -system.cpu.iew.wb_sent 1452666848 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451778777 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153445523 # num instructions producing a value -system.cpu.iew.wb_consumers 1204705379 # num instructions consuming a value +system.cpu.iew.exec_nop 93683614 # number of nop insts executed +system.cpu.iew.exec_refs 586997386 # number of memory reference insts executed +system.cpu.iew.exec_branches 89036634 # Number of branches executed +system.cpu.iew.exec_stores 170446912 # Number of stores executed +system.cpu.iew.exec_rate 1.877050 # Inst execution rate +system.cpu.iew.wb_sent 1452648479 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451772480 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153427719 # num instructions producing a value +system.cpu.iew.wb_consumers 1204682131 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874328 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957450 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957454 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119167265 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119216890 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615880 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757361515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509795 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3614520 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757404957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509691 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240009654 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275743732 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42570119 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54687779 7.22% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19671272 2.60% 83.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13286277 1.75% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30573058 4.04% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10535838 1.39% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70283786 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 239974569 31.68% 31.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275852046 36.42% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42571811 5.62% 73.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54691782 7.22% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19624283 2.59% 83.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13282059 1.75% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30580381 4.04% 89.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10561653 1.39% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70266373 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757361515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757404957 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,192 +442,192 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70283786 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70266373 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295703406 # The number of ROB reads -system.cpu.rob.rob_writes 3234392884 # The number of ROB writes -system.cpu.timesIdled 26078 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208793 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295813886 # The number of ROB reads +system.cpu.rob.rob_writes 3234496299 # The number of ROB writes +system.cpu.timesIdled 25967 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 232832 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552787 # CPI: Total CPI of All Threads -system.cpu.ipc 1.809014 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.809014 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979140277 # number of integer regfile reads -system.cpu.int_regfile_writes 1275189089 # number of integer regfile writes -system.cpu.fp_regfile_reads 16965348 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491584 # number of floating regfile writes -system.cpu.misc_regfile_reads 592679771 # number of misc regfile reads +system.cpu.cpi 0.552838 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552838 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808847 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808847 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979103244 # number of integer regfile reads +system.cpu.int_regfile_writes 1275174788 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962430 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491706 # number of floating regfile writes +system.cpu.misc_regfile_reads 592650972 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 200 # number of replacements -system.cpu.icache.tagsinuse 1035.695786 # Cycle average of tags in use -system.cpu.icache.total_refs 161937647 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121029.631540 # Average number of references to valid blocks. +system.cpu.icache.replacements 197 # number of replacements +system.cpu.icache.tagsinuse 1035.237714 # Cycle average of tags in use +system.cpu.icache.total_refs 161935084 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1336 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121208.895210 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.695786 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505711 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505711 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161937647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161937647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161937647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161937647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161937647 # number of overall hits -system.cpu.icache.overall_hits::total 161937647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses -system.cpu.icache.overall_misses::total 1943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81333500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81333500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81333500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81333500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81333500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161939590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161939590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161939590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161939590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161939590 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1035.237714 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505487 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161935084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161935084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161935084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161935084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161935084 # number of overall hits +system.cpu.icache.overall_hits::total 161935084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1939 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1939 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 100129.050405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 89418.099628 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72934.880411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72934.880411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76325.408401 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49652.464495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77542.761277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76325.408401 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,160 +638,160 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2533 # number of writebacks system.cpu.l2cache.writebacks::total 2533 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1195 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 5633 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21787 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 21787 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1195 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 26225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 27420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1195 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 26225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 27420 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41471942 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413076738 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 454548680 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1277066596 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1277066596 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41471942 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1690143334 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1731615276 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41471942 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1690143334 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1731615276 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022095 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027859 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083018 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059014 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.892457 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056605 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059014 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34704.553975 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 93077.228031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80693.889579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58615.991004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58615.991004 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34704.553975 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64447.791573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63151.541794 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1197 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4444 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 5641 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21783 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 21783 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1197 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 26227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 27424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1197 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 26227 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 27424 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44575992 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389548209 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 434124201 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319276658 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319276658 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44575992 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1708824867 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1753400859 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44575992 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1708824867 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1753400859 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027900 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083003 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083003 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059024 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.895288 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056611 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059024 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37239.759398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87657.112736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76958.730899 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60564.507093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60564.507093 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37239.759398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65155.178518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63936.729106 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459203 # number of replacements -system.cpu.dcache.tagsinuse 4093.828957 # Cycle average of tags in use -system.cpu.dcache.total_refs 365170885 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463299 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 788.197007 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 342772000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.828957 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999470 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999470 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 200214093 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200214093 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955473 # number of WriteReq hits +system.cpu.dcache.replacements 459190 # number of replacements +system.cpu.dcache.tagsinuse 4093.797590 # Cycle average of tags in use +system.cpu.dcache.total_refs 365198263 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463286 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 788.278219 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 340173000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.797590 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999462 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999462 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200241495 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200241495 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955449 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955449 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 923055 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 923055 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891367 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891367 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2819034 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2819034 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2819034 # number of overall misses -system.cpu.dcache.overall_misses::total 2819034 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14988091500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14988091500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31927965942 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31927965942 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 122000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 122000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46916057442 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46916057442 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46916057442 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201141784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201141784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2814422 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2814422 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2814422 # number of overall misses +system.cpu.dcache.overall_misses::total 2814422 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14739603500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31907348686 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46646952186 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46646952186 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46646952186 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201164550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201164550 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 367988600 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 367988600 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 367988600 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 367988600 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004612 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 368011366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 368011366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 368011366 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 368011366 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004589 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007661 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007661 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16156.340312 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16156.340312 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16881.108261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16881.108261 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 17428.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 17428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16642.600778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16642.600778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573681 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35664 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.085717 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007648 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007648 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007648 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007648 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15968.283038 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15968.283038 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16869.993336 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16869.993336 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16574.256521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16574.256521 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590116 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 35661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.547938 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443928 # number of writebacks -system.cpu.dcache.writebacks::total 443928 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 726830 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 726830 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2355742 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2355742 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2355742 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262431 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262431 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 443933 # number of writebacks +system.cpu.dcache.writebacks::total 443933 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722205 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 722205 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628938 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2351143 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2351143 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2351143 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262429 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262429 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463292 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463292 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463292 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2635998000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4319921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 108000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6955919000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6955919000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463279 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463279 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463279 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2612152000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357934500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6970086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6970086500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -800,16 +800,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13123.493361 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16461.168841 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 15428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15014.114209 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15014.114209 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.486682 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16606.146805 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15045.116442 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15045.116442 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index 3548dbe1a..dc034cfd1 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.607446 # Number of seconds simulated -sim_ticks 607445544000 # Number of ticks simulated -final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.607292 # Number of seconds simulated +sim_ticks 607292111000 # Number of ticks simulated +final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56942 # Simulator instruction rate (inst/s) -host_op_rate 104918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39304494 # Simulator tick rate (ticks/s) -host_mem_usage 295872 # Number of bytes of host memory used -host_seconds 15454.86 # Real time elapsed on the host +host_inst_rate 91190 # Simulator instruction rate (inst/s) +host_op_rate 168022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62928697 # Simulator tick rate (ticks/s) +host_mem_usage 248736 # Number of bytes of host memory used +host_seconds 9650.48 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory -system.physmem.bytes_read::total 1750912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 1750848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 57664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57664 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162176 # Number of bytes written to this memory system.physmem.bytes_written::total 162176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27358 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27357 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2534 # Number of write requests responded to by this memory system.physmem.num_writes::total 2534 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2787384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2882418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 266980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 266980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2787384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3149398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 94953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2788088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2883041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 267048 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 267048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2788088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3150089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27359 # Total number of read requests seen system.physmem.writeReqs 2534 # Total number of write requests seen system.physmem.cpureqs 29893 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1750912 # Total number of bytes read from memory +system.physmem.bytesRead 1750848 # Total number of bytes read from memory system.physmem.bytesWritten 162176 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1750912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1750848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162176 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1747 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1742 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1701 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 1712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1676 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 156 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 1708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1735 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 159 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 607445530000 # Total gap between requests +system.physmem.totGap 607292095000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 26894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -171,265 +171,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 68456669 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 822256669 # Sum of mem lat for all requests -system.physmem.totBusLat 109436000 # Total cycles spent in databus access -system.physmem.totBankLat 644364000 # Total cycles spent in bank access -system.physmem.avgQLat 2502.16 # Average queueing delay per request -system.physmem.avgBankLat 23552.18 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30054.34 # Average memory access latency +system.physmem.totQLat 90448613 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests +system.physmem.totBusLat 136795000 # Total cycles spent in databus access +system.physmem.totBankLat 668305000 # Total cycles spent in bank access +system.physmem.avgQLat 3305.99 # Average queueing delay per request +system.physmem.avgBankLat 24427.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32733.24 # Average memory access latency system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.27 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 6.29 # Average write queue length over time -system.physmem.readRowHits 17697 # Number of row buffer hits during reads -system.physmem.writeRowHits 1084 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes -system.physmem.avgGap 20320661.36 # Average gap between requests -system.cpu.branchPred.lookups 158385701 # Number of BP lookups -system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups -system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits +system.physmem.avgWrQLen 6.24 # Average write queue length over time +system.physmem.readRowHits 16426 # Number of row buffer hits during reads +system.physmem.writeRowHits 1032 # Number of row buffer hits during writes +system.physmem.readRowHitRate 60.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.73 # Row buffer hit rate for writes +system.physmem.avgGap 20315528.55 # Average gap between requests +system.cpu.branchPred.lookups 158482804 # Number of BP lookups +system.cpu.branchPred.condPredicted 158482804 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26384558 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 84639114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84422216 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.743738 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1214891089 # number of cpu cycles simulated +system.cpu.numCycles 1214584223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed -system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 84079165 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 399080479 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88232216 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 574634441 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 187842503 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11743851 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.253312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 179034165 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1457747721 # Number of instructions fetch has processed +system.cpu.fetch.Branches 158482804 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84422216 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 399024262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88084887 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 574618713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 378 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 188004827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11985682 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.059311 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.252911 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 822675212 67.74% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26883309 2.21% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 13192065 1.09% 71.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20566257 1.69% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26639433 2.19% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18282936 1.51% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31338155 2.58% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 39109954 3.22% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215850749 17.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 822415344 67.73% 67.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26978129 2.22% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13144140 1.08% 71.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20617690 1.70% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26634807 2.19% 74.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18232650 1.50% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31447933 2.59% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39056021 3.22% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215694726 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1214538070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.130370 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200462 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 288247470 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 497953948 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 274080522 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92569137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 61686993 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2343830219 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 61686993 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 336887109 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124143936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2487 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 304057721 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 387759824 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2248180627 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 242798221 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 120202889 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2618438730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5723603734 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5723598334 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5400 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895258 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 731543472 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 87 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 731379517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 532059001 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219301341 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 342202544 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144686488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1994506429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1784080761 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243450 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 372613756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 761627172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 239 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1214538070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.468938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.421549 # Number of insts issued each cycle +system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 371594187 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 759078017 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 237 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1214221440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 360345169 29.67% 29.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 364336445 30.00% 59.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234287346 19.29% 78.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141446603 11.65% 90.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60702765 5.00% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39742301 3.27% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11032116 0.91% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2048046 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 597279 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1214538070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1214221440 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437572 15.09% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2259609 77.90% 92.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 203424 7.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 459684 15.86% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2241246 77.33% 93.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197213 6.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812462 2.62% 2.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1065847679 59.74% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 478866421 26.84% 89.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192554199 10.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812327 2.62% 2.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1065713813 59.74% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 478893732 26.84% 89.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192532359 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1784080761 # Type of FU issued -system.cpu.iq.rate 1.468511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2900605 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4785843297 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2367295034 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1724820361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 350 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1704 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1740168733 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 209903028 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1783952231 # Type of FU issued +system.cpu.iq.rate 1.468776 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2898143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001625 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4785297542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2365259636 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1724635094 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 543 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113016880 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 39297 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31115283 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 182684 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31031188 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2481 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2402 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 61686993 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1142265 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110648 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1994506717 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63004482 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 532059001 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219301341 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 80 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 54039 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2855 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2045569 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24474359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 26519928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1766291934 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 474573600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 17788827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 61543875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1219448 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 109755 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1993488848 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63065998 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 531670409 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219217246 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 52970 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2883 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 182684 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2045175 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24468993 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 26514168 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1766143547 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 474612951 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 17808684 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 666299746 # number of memory reference insts executed -system.cpu.iew.exec_branches 110359604 # Number of branches executed -system.cpu.iew.exec_stores 191726146 # Number of stores executed -system.cpu.iew.exec_rate 1.453869 # Inst execution rate -system.cpu.iew.wb_sent 1725940615 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1724820453 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1267203875 # num instructions producing a value -system.cpu.iew.wb_consumers 1829107615 # num instructions consuming a value +system.cpu.iew.exec_refs 666319153 # number of memory reference insts executed +system.cpu.iew.exec_branches 110355146 # Number of branches executed +system.cpu.iew.exec_stores 191706202 # Number of stores executed +system.cpu.iew.exec_rate 1.454114 # Inst execution rate +system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1267063012 # num instructions producing a value +system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.419733 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692799 # average fanout of values written-back +system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 373014217 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 371996186 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 26390469 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1152851077 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.406508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.830012 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 26384610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1152677565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.406719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.830300 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 418199687 36.28% 36.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 415017727 36.00% 72.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87014149 7.55% 79.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122172880 10.60% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24164674 2.10% 92.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25337442 2.20% 94.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16460362 1.43% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12052065 1.05% 97.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32432091 2.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 418027879 36.27% 36.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 415124601 36.01% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86915055 7.54% 79.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122122398 10.59% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24176868 2.10% 92.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25399940 2.20% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16385768 1.42% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12050207 1.05% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32474849 2.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1152851077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1152677565 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493926 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,194 +440,194 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354437 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32432091 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32474849 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3114927129 # The number of ROB reads -system.cpu.rob.rob_writes 4050738571 # The number of ROB writes -system.cpu.timesIdled 58873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 353019 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3113692828 # The number of ROB reads +system.cpu.rob.rob_writes 4048559892 # The number of ROB writes +system.cpu.timesIdled 59027 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 362783 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493926 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.380518 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.380518 # CPI: Total CPI of All Threads -system.cpu.ipc 0.724366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.724366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3542903494 # number of integer regfile reads -system.cpu.int_regfile_writes 1974699145 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 910807256 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 815.551450 # Cycle average of tags in use -system.cpu.icache.total_refs 187841113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 206418.805495 # Average number of references to valid blocks. +system.cpu.cpi 1.380170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.380170 # CPI: Total CPI of All Threads +system.cpu.ipc 0.724549 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.724549 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3542852942 # number of integer regfile reads +system.cpu.int_regfile_writes 1974486988 # number of integer regfile writes +system.cpu.fp_regfile_reads 123 # number of floating regfile reads +system.cpu.misc_regfile_reads 910772207 # number of misc regfile reads +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 816.669933 # Cycle average of tags in use +system.cpu.icache.total_refs 188003443 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 918 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 204796.778867 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 815.551450 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.398218 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.398218 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 187841119 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 187841119 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 187841119 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 187841119 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 187841119 # number of overall hits -system.cpu.icache.overall_hits::total 187841119 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1384 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1384 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1384 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1384 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1384 # number of overall misses -system.cpu.icache.overall_misses::total 1384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64353500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64353500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 187842503 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 187842503 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 187842503 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 187842503 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 187842503 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 816.669933 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.398765 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.398765 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 188003447 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 188003447 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 188003447 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 188003447 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47135.869565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47135.869565 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47382000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47382000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50259.259259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50259.259259 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55245.951972 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,142 +638,142 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 2534 # number of writebacks system.cpu.l2cache.writebacks::total 2534 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 902 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4560 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 901 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4561 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 452307975 # 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miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001010 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001010 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001010 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14285.059322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14285.059322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16490.622232 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16490.622232 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15472.914465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15472.914465 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 474 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.001011 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001011 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001011 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.875000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 428963 # number of writebacks -system.cpu.dcache.writebacks::total 428963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7361 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 84 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 84 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7445 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7445 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7445 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246350 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246350 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450124 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450124 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3570238499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6093778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6093778999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6093778999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 429018 # number of writebacks +system.cpu.dcache.writebacks::total 429018 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 81 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 81 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7545 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7545 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7545 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203817 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203817 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246374 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450191 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450191 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -782,14 +782,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000994 system.cpu.dcache.demand_mshr_miss_rate::total 0.000994 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12384.016116 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14492.545155 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13538.000638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13538.000638 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 5f270b948..b0849c006 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026773 # Number of seconds simulated -sim_ticks 26773408500 # Number of ticks simulated -final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026779 # Number of seconds simulated +sim_ticks 26779468500 # Number of ticks simulated +final_tick 26779468500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111467 # Simulator instruction rate (inst/s) -host_op_rate 112267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32943427 # Simulator tick rate (ticks/s) -host_mem_usage 421388 # Number of bytes of host memory used -host_seconds 812.71 # Real time elapsed on the host +host_inst_rate 196675 # Simulator instruction rate (inst/s) +host_op_rate 198087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58139571 # Simulator tick rate (ticks/s) +host_mem_usage 373976 # Number of bytes of host memory used +host_seconds 460.61 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 992576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15509 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35392729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37073203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35392729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37073203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15509 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory +system.physmem.bytes_read::total 993088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15517 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1689653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35394280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37083932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1689653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1689653 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1689653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35394280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 37083932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15517 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15512 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992576 # Total number of bytes read from memory +system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 993088 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 993088 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 902 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1011 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 933 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1002 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26773229500 # Total gap between requests +system.physmem.totGap 26779289500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15509 # Categorize read packet sizes +system.physmem.readPktSize::6 15517 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 3 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 10802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 45602981 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 279992981 # Sum of mem lat for all requests -system.physmem.totBusLat 62036000 # Total cycles spent in databus access -system.physmem.totBankLat 172354000 # Total cycles spent in bank access -system.physmem.avgQLat 2940.42 # Average queueing delay per request -system.physmem.avgBankLat 11113.16 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18053.58 # Average memory access latency -system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 52084984 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 311719984 # Sum of mem lat for all requests +system.physmem.totBusLat 77585000 # Total cycles spent in databus access +system.physmem.totBankLat 182050000 # Total cycles spent in bank access +system.physmem.avgQLat 3356.64 # Average queueing delay per request +system.physmem.avgBankLat 11732.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20088.93 # Average memory access latency +system.physmem.avgRdBW 37.08 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 37.08 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 15086 # Number of row buffer hits during reads +system.physmem.readRowHits 14783 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726302.76 # Average gap between requests -system.cpu.branchPred.lookups 26672080 # Number of BP lookups -system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits +system.physmem.avgGap 1725803.28 # Average gap between requests +system.cpu.branchPred.lookups 26678818 # Number of BP lookups +system.cpu.branchPred.condPredicted 21998913 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842318 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11366409 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11281153 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.249930 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69723 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 201 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,134 +237,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53546818 # number of cpu cycles simulated +system.cpu.numCycles 53558938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11338226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24008993 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4747196 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11262084 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14172731 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127871641 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26678818 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11350876 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24033181 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4760167 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11226793 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13843627 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 330314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53334178 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412341 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.215312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13844867 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 331224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53334396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.414044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.215935 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29363698 55.06% 55.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3375400 6.33% 61.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2026423 3.80% 65.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553443 2.91% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668565 3.13% 71.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2920644 5.48% 76.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511002 2.83% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091875 2.05% 81.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9823128 18.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29339451 55.01% 55.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3389540 6.36% 61.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2028066 3.80% 65.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1555662 2.92% 68.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667100 3.13% 71.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2918330 5.47% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1510510 2.83% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090066 2.04% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9835671 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53334178 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498108 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.386304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16944806 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9096910 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405465 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1004110 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3882887 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4441553 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8682 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 125956281 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42689 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3882887 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18731656 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3549082 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 155235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21520684 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5494634 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123060237 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 429079 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4593412 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1240 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143474506 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536032151 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536027496 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4655 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53334396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498121 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.387494 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16935376 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9075535 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22432463 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 998016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3893006 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442432 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8659 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126044255 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42607 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3893006 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18714710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3545279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 156066 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21549370 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5475965 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123134352 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 422701 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4592939 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1259 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143588919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536358187 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536353466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4721 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36060320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4617 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4615 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12531131 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29463379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5514746 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2152870 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1249780 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118072720 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8484 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105142122 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71988 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26643181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65222929 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 266 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53334178 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971384 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.909777 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36174733 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12509318 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29470006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5522308 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2104178 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1264650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118149095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8470 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105144375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26722736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65554797 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 252 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53334396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.971418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.910922 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15298443 28.68% 28.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11631181 21.81% 50.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8279084 15.52% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6786399 12.72% 78.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4950529 9.28% 88.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2953624 5.54% 93.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2464815 4.62% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 526374 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443729 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15312252 28.71% 28.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11634281 21.81% 50.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8274633 15.51% 66.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6753758 12.66% 78.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4949297 9.28% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2972831 5.57% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2466224 4.62% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 528093 0.99% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 443027 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53334178 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53334396 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 44991 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 339313 51.37% 58.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 276174 41.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 44474 6.73% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 340155 51.46% 58.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 276363 41.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74410825 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10970 0.01% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74414194 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued @@ -385,91 +385,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 146 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 143 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 186 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25604346 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5115650 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25601639 24.35% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5117225 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105142122 # Type of FU issued -system.cpu.iq.rate 1.963555 # Inst issue rate -system.cpu.iq.fu_busy_cnt 660505 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006282 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264350195 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144728935 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102671361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 720 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1005 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105802266 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 442877 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105144375 # Type of FU issued +system.cpu.iq.rate 1.963153 # Inst issue rate +system.cpu.iq.fu_busy_cnt 661019 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006287 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264361545 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144884747 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102673470 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 727 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1011 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 322 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105805031 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 363 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 444404 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6889413 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6770 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6285 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 769902 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6896040 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6651 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 777464 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 27948 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31327 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3882887 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 927098 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118093920 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309711 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29463379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5514746 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4596 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66094 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6965 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6285 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446526 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 446132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892658 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104164248 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25284832 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977874 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3893006 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 929576 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127351 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118170277 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309597 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29470006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5522308 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4582 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66448 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6858 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446675 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445546 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104166430 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25281924 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 977945 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12716 # number of nop insts executed -system.cpu.iew.exec_refs 30343472 # number of memory reference insts executed -system.cpu.iew.exec_branches 21324084 # Number of branches executed -system.cpu.iew.exec_stores 5058640 # Number of stores executed -system.cpu.iew.exec_rate 1.945293 # Inst execution rate -system.cpu.iew.wb_sent 102950061 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102671670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62244850 # num instructions producing a value -system.cpu.iew.wb_consumers 104302213 # num instructions consuming a value +system.cpu.iew.exec_nop 12712 # number of nop insts executed +system.cpu.iew.exec_refs 30342174 # number of memory reference insts executed +system.cpu.iew.exec_branches 21323986 # Number of branches executed +system.cpu.iew.exec_stores 5060250 # Number of stores executed +system.cpu.iew.exec_rate 1.944893 # Inst execution rate +system.cpu.iew.wb_sent 102951824 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102673792 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62219945 # num instructions producing a value +system.cpu.iew.wb_consumers 104261628 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917419 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596774 # average fanout of values written-back +system.cpu.iew.wb_rate 1.917024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596767 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26843909 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26920302 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834006 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49451291 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541193 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833747 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49441390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.845680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.541256 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19963736 40.37% 40.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13137085 26.57% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4166734 8.43% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3433201 6.94% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1540600 3.12% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 738938 1.49% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 946959 1.91% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 248344 0.50% 89.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275694 10.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19945415 40.34% 40.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13149428 26.60% 66.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4162611 8.42% 75.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3435070 6.95% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1540295 3.12% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 748484 1.51% 86.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 932633 1.89% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 245930 0.50% 89.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5281524 10.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49451291 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49441390 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,200 +480,200 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5281524 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162266732 # The number of ROB reads -system.cpu.rob.rob_writes 240096387 # The number of ROB writes -system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 212640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162327394 # The number of ROB reads +system.cpu.rob.rob_writes 240259263 # The number of ROB writes +system.cpu.timesIdled 43763 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 224542 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591091 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495496065 # number of integer regfile reads -system.cpu.int_regfile_writes 120529637 # number of integer regfile writes -system.cpu.fp_regfile_reads 153 # number of floating regfile reads -system.cpu.fp_regfile_writes 387 # number of floating regfile writes -system.cpu.misc_regfile_reads 29090556 # number of misc regfile reads +system.cpu.cpi 0.591225 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.591225 # CPI: Total CPI of All Threads +system.cpu.ipc 1.691404 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.691404 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495495273 # number of integer regfile reads +system.cpu.int_regfile_writes 120530797 # number of integer regfile writes +system.cpu.fp_regfile_reads 175 # number of floating regfile reads +system.cpu.fp_regfile_writes 405 # number of floating regfile writes +system.cpu.misc_regfile_reads 29088840 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 628.046446 # Cycle average of tags in use -system.cpu.icache.total_refs 13842647 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 730 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18962.530137 # Average number of references to valid blocks. +system.cpu.icache.replacements 3 # number of replacements +system.cpu.icache.tagsinuse 630.551988 # Cycle average of tags in use +system.cpu.icache.total_refs 13843878 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 18886.600273 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 628.046446 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306663 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306663 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13842647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13842647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13842647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13842647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13842647 # number of overall hits -system.cpu.icache.overall_hits::total 13842647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 979 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 979 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 979 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 979 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 979 # number of overall misses -system.cpu.icache.overall_misses::total 979 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 47680999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 47680999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 47680999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 47680999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 47680999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 47680999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13843626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13843626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13843626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13843626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13843626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13843626 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.551988 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307887 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307887 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13843878 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13843878 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13843878 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13843878 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13843878 # number of overall hits +system.cpu.icache.overall_hits::total 13843878 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 988 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 988 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 988 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 988 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 988 # number of overall misses +system.cpu.icache.overall_misses::total 988 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49634499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49634499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49634499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49634499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49634499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49634499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13844866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13844866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13844866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13844866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13844866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13844866 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48703.778345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48703.778345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48703.778345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48703.778345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48703.778345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1057 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50237.347166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50237.347166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50237.347166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50237.347166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50237.347166 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 132.125000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 736 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15509 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 703 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15509 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26990085 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10560900 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37550985 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 707 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15517 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 707 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15517 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28010860 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11866667 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 39877527 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 421398919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 421398919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26990085 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 431959819 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 458949904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26990085 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 431959819 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 458949904 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001072 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.334007 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.334007 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016354 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963014 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016354 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38392.724040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39553.932584 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38712.355670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 445060185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 445060185 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28010860 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 456926852 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 484937712 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28010860 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 456926852 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 484937712 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001081 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.333570 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.333570 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016362 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39619.321075 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43788.439114 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40774.567485 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28984.037348 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28984.037348 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38392.724040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29174.646697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29592.488491 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30611.471559 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30611.471559 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39619.321075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30852.589602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31252.027583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943481 # number of replacements -system.cpu.dcache.tagsinuse 3674.468837 # Cycle average of tags in use -system.cpu.dcache.total_refs 28144290 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947577 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.701322 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7935444000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.468837 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897087 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897087 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23599200 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23599200 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4537276 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4537276 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits +system.cpu.dcache.replacements 943534 # number of replacements +system.cpu.dcache.tagsinuse 3674.806480 # Cycle average of tags in use +system.cpu.dcache.total_refs 28135871 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.690777 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7938358000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3674.806480 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.897170 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.897170 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23591287 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23591287 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4536767 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4536767 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3920 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3920 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28136476 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136476 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136476 # number of overall hits -system.cpu.dcache.overall_hits::total 28136476 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173036 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173036 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 197705 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 197705 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1370741 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1370741 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1370741 # number of overall misses -system.cpu.dcache.overall_misses::total 1370741 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13886322000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13886322000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5375913921 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5375913921 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19262235921 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19262235921 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19262235921 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19262235921 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24772236 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24772236 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28128054 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28128054 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28128054 # number of overall hits +system.cpu.dcache.overall_hits::total 28128054 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173096 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173096 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 198214 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 198214 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1371310 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1371310 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1371310 # number of overall misses +system.cpu.dcache.overall_misses::total 1371310 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13884435000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13884435000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5574763392 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19459198392 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19459198392 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19459198392 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19459198392 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24764383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24764383 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3918 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3918 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29507217 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29507217 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29507217 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29507217 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047353 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047353 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041754 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046454 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046454 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046454 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046454 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11837.933363 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11837.933363 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27191.593136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27191.593136 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29214.285714 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29214.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14052.425601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14052.425601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14052.425601 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132657 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29499364 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29499364 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29499364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29499364 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047370 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047370 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041862 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041862 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001528 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001528 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046486 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046486 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046486 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046486 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.719327 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.719327 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28124.972969 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28124.972969 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14190.225691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14190.225691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14190.225691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 152485 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23814 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23871 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.570547 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387877 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks -system.cpu.dcache.writebacks::total 942884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 268972 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 268972 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154186 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 423158 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 423158 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 423158 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 423158 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904064 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904064 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43519 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947583 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947583 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9987518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9987518000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 958248463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 958248463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945766463 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10945766463 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945766463 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10945766463 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036495 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036495 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009191 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009191 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032114 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032114 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11047.357267 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11047.357267 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22019.082768 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22019.082768 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11551.248242 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11551.248242 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942924 # number of writebacks +system.cpu.dcache.writebacks::total 942924 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269038 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269038 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154638 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 154638 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 423676 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 423676 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 423676 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 423676 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904058 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 904058 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43576 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947634 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947634 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947634 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947634 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 980693945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 980693945 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10971127945 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10971127945 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10971127945 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10971127945 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036506 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009203 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032124 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.656042 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.656042 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22505.368666 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22505.368666 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11577.389525 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11577.389525 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 860f57b09..8e442dc5d 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065983 # Number of seconds simulated -sim_ticks 65982862500 # Number of ticks simulated -final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.066005 # Number of seconds simulated +sim_ticks 66004575000 # Number of ticks simulated +final_tick 66004575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72483 # Simulator instruction rate (inst/s) -host_op_rate 127630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30271870 # Simulator tick rate (ticks/s) -host_mem_usage 430980 # Number of bytes of host memory used -host_seconds 2179.68 # Real time elapsed on the host +host_inst_rate 124260 # Simulator instruction rate (inst/s) +host_op_rate 218802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51913433 # Simulator tick rate (ticks/s) +host_mem_usage 384868 # Number of bytes of host memory used +host_seconds 1271.44 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192463 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory -system.physmem.bytes_read::total 1948288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11136 # Number of bytes written to this memory -system.physmem.bytes_written::total 11136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 988378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28538804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29527182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988378 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168771 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168771 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28538804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29695953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30444 # Total number of read requests seen -system.physmem.writeReqs 174 # Total number of write requests seen -system.physmem.cpureqs 30619 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1948288 # Total number of bytes read from memory -system.physmem.bytesWritten 11136 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1948288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 11136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882560 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10816 # Number of bytes written to this memory +system.physmem.bytes_written::total 10816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29415 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30432 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 169 # Number of write requests responded to by this memory +system.physmem.num_writes::total 169 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 986113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28521659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29507773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 986113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 986113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 986113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28521659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29671640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30434 # Total number of read requests seen +system.physmem.writeReqs 169 # Total number of write requests seen +system.physmem.cpureqs 30604 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1947648 # Total number of bytes read from memory +system.physmem.bytesWritten 10816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1947648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 2031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1999 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1881 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1910 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1972 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1932 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1846 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 93 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 11 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 46 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 14 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 1 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 11 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 1 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65982843000 # Total gap between requests +system.physmem.totGap 66004558000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30444 # Categorize read packet sizes +system.physmem.readPktSize::6 30434 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 174 # categorize write packet sizes +system.physmem.writePktSize::6 169 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 1 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 29860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 405 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -146,11 +146,11 @@ system.physmem.wrQLenPdf::4 8 # Wh system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see @@ -171,161 +171,160 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 10445857 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 571603857 # Sum of mem lat for all requests -system.physmem.totBusLat 121544000 # Total cycles spent in databus access -system.physmem.totBankLat 439614000 # Total cycles spent in bank access -system.physmem.avgQLat 343.77 # Average queueing delay per request -system.physmem.avgBankLat 14467.65 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18811.42 # Average memory access latency -system.physmem.avgRdBW 29.53 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.53 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.19 # Data bus utilization in percentage +system.physmem.totQLat 12335337 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 610214087 # Sum of mem lat for all requests +system.physmem.totBusLat 151870000 # Total cycles spent in databus access +system.physmem.totBankLat 446008750 # Total cycles spent in bank access +system.physmem.avgQLat 406.11 # Average queueing delay per request +system.physmem.avgBankLat 14683.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20090.01 # Average memory access latency +system.physmem.avgRdBW 29.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.24 # Average write queue length over time -system.physmem.readRowHits 29640 # Number of row buffer hits during reads -system.physmem.writeRowHits 45 # Number of row buffer hits during writes -system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes -system.physmem.avgGap 2155034.39 # Average gap between requests -system.cpu.branchPred.lookups 34537566 # Number of BP lookups -system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups -system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits +system.physmem.avgWrQLen 1.18 # Average write queue length over time +system.physmem.readRowHits 29113 # Number of row buffer hits during reads +system.physmem.writeRowHits 87 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 51.48 # Row buffer hit rate for writes +system.physmem.avgGap 2156800.25 # Average gap between requests +system.cpu.branchPred.lookups 34551755 # Number of BP lookups +system.cpu.branchPred.condPredicted 34551755 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 910403 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24766802 # Number of BTB lookups +system.cpu.branchPred.BTBHits 24665055 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 99.589180 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131965726 # number of cpu cycles simulated +system.cpu.numCycles 132009151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed -system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24642661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 56492855 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6109576 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43628030 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25952051 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 188971 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131886743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.485312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.326723 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26590977 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 185543024 # Number of instructions fetch has processed +system.cpu.fetch.Branches 34551755 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24665055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 56499392 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6118358 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 43667810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 138 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 25944504 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189453 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131930197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.484743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326414 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77942049 59.10% 59.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1996023 1.51% 60.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2954192 2.24% 62.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3924230 2.98% 65.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7791327 5.91% 71.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757391 3.61% 75.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2730462 2.07% 77.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1561040 1.18% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28230029 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77978275 59.11% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1995894 1.51% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2955143 2.24% 62.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3921314 2.97% 65.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7795304 5.91% 71.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757842 3.61% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2730359 2.07% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1578596 1.20% 78.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28217470 21.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131886743 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.261716 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.406198 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37433496 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35884188 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44759605 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8645670 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5163784 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 324546222 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 5163784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42999384 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8526748 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9161 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 47575820 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27611846 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 320149985 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 225 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53569 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25749083 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 361 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 322162823 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 849088667 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 849086832 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1835 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131930197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.261738 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.405532 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37427999 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35920173 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44744893 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8665277 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5171855 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 324565548 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 5171855 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42969195 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8593654 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9092 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 47590664 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27595737 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 320190802 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 211 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 56984 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25724332 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 365 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 322194206 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 849198017 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 849196232 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1785 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212745 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 42950078 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62353215 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 102529083 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 35255084 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39579305 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5971941 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 315806334 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1679 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 302165189 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115128 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 36987116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 54145851 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131886743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.291096 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.700528 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 42981461 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62356862 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 102568377 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 35231338 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39589479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6005074 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 315870239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1674 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 302163622 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115310 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 37046058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 54286160 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1229 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131930197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700150 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24537309 18.60% 18.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23216690 17.60% 36.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25879367 19.62% 55.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25801755 19.56% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18920728 14.35% 89.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8321327 6.31% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4137839 3.14% 99.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 905905 0.69% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 165823 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24515615 18.58% 18.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23292289 17.66% 36.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25896464 19.63% 55.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25797972 19.55% 75.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18916380 14.34% 89.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8292938 6.29% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4139203 3.14% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 915627 0.69% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 163709 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131886743 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131930197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 38358 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1830721 93.50% 95.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88976 4.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 38493 1.98% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1820587 93.51% 95.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 87813 4.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31295 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 171151869 56.64% 56.65% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31282 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 171146899 56.64% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.65% # Type of FU issued @@ -354,84 +353,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.65% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.65% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97747173 32.35% 89.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33234817 11.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97755630 32.35% 89.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33229776 11.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 302165189 # Type of FU issued -system.cpu.iq.rate 2.289725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1958055 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738289800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 352827074 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 299525455 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 863 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 304091716 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 233 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54002404 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 302163622 # Type of FU issued +system.cpu.iq.rate 2.288960 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1946893 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006443 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738319072 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 352950108 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 299522625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 572 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 867 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 304078975 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 53992768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11749699 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33919 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3815332 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11788993 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26852 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33996 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3791586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3226 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8521 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8506 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5163784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1727826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159628 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 315808013 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197001 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 102529083 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 35255084 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 5171855 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1763635 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159728 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 315871913 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 195728 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 102568377 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 35231338 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 464 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3215 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73485 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33919 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 521490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 966645 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 300546126 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97278076 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1619063 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 3188 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33996 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 522451 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444817 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 967268 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 300543939 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97286160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1619683 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 130293374 # number of memory reference insts executed -system.cpu.iew.exec_branches 30888175 # Number of branches executed -system.cpu.iew.exec_stores 33015298 # Number of stores executed -system.cpu.iew.exec_rate 2.277456 # Inst execution rate -system.cpu.iew.wb_sent 299954363 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 299525609 # cumulative count of insts written-back -system.cpu.iew.wb_producers 219474385 # num instructions producing a value -system.cpu.iew.wb_consumers 297941322 # num instructions consuming a value +system.cpu.iew.exec_refs 130298049 # number of memory reference insts executed +system.cpu.iew.exec_branches 30887567 # Number of branches executed +system.cpu.iew.exec_stores 33011889 # Number of stores executed +system.cpu.iew.exec_rate 2.276690 # Inst execution rate +system.cpu.iew.wb_sent 299950982 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 299522787 # cumulative count of insts written-back +system.cpu.iew.wb_producers 219513248 # num instructions producing a value +system.cpu.iew.wb_consumers 298024509 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.269723 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736636 # average fanout of values written-back +system.cpu.iew.wb_rate 2.268955 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736561 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 37628513 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 37692291 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 909867 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126722959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.195281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.965844 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910422 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126758342 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.194668 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.965617 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58163271 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19278050 15.21% 61.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11813019 9.32% 70.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9592484 7.57% 78.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741744 1.37% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2072615 1.64% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1297671 1.02% 82.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 717994 0.57% 82.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22046111 17.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58200495 45.91% 45.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19281721 15.21% 61.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11800672 9.31% 70.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9590531 7.57% 78.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1751465 1.38% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2073903 1.64% 81.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1296843 1.02% 82.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 720324 0.57% 82.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22042388 17.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126722959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126758342 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192463 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -442,197 +441,197 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186172 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22046111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22042388 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 420497824 # The number of ROB reads -system.cpu.rob.rob_writes 636810847 # The number of ROB writes -system.cpu.timesIdled 13700 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 78983 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 420600708 # The number of ROB reads +system.cpu.rob.rob_writes 636946432 # The number of ROB writes +system.cpu.timesIdled 13762 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78954 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192463 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.835287 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835287 # CPI: Total CPI of All Threads -system.cpu.ipc 1.197194 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.197194 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 592820364 # number of integer regfile reads -system.cpu.int_regfile_writes 300190131 # number of integer regfile writes -system.cpu.fp_regfile_reads 138 # number of floating regfile reads -system.cpu.fp_regfile_writes 78 # number of floating regfile writes -system.cpu.misc_regfile_reads 192690356 # number of misc regfile reads -system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 836.141368 # Cycle average of tags in use -system.cpu.icache.total_refs 25950700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1039 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24976.612127 # Average number of references to valid blocks. +system.cpu.cpi 0.835562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835562 # CPI: Total CPI of All Threads +system.cpu.ipc 1.196800 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.196800 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 592847791 # number of integer regfile reads +system.cpu.int_regfile_writes 300194164 # number of integer regfile writes +system.cpu.fp_regfile_reads 150 # number of floating regfile reads +system.cpu.fp_regfile_writes 76 # number of floating regfile writes +system.cpu.misc_regfile_reads 192689354 # number of misc regfile reads +system.cpu.icache.replacements 61 # number of replacements +system.cpu.icache.tagsinuse 835.847711 # Cycle average of tags in use +system.cpu.icache.total_refs 25943160 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1033 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25114.385286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 836.141368 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.408272 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.408272 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25950700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25950700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25950700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25950700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25950700 # number of overall hits -system.cpu.icache.overall_hits::total 25950700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1351 # number of overall misses -system.cpu.icache.overall_misses::total 1351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65349000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65349000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65349000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65349000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65349000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65349000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25952051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25952051 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25952051 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25952051 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25952051 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25952051 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 835.847711 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.408129 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.408129 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25943160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25943160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25943160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25943160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25943160 # number of overall hits +system.cpu.icache.overall_hits::total 25943160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1344 # number of overall misses +system.cpu.icache.overall_misses::total 1344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65684000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65684000 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41754.582184 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352592 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352592 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984511 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014651 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984511 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014651 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49786.627335 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50455.635492 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49981.171548 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42062.431034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42062.431034 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 42435.549057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49786.627335 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42181.408709 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 42435.549057 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,168 +640,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 174 # number of writebacks -system.cpu.l2cache.writebacks::total 174 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1019 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1443 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 169 # number of writebacks +system.cpu.l2cache.writebacks::total 169 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1017 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38000083 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15880649 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53880732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29000 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30434 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29417 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30434 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38011868 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15869892 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53881760 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 824195395 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 824195395 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38000083 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 840076044 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 878076127 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 915973896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38011868 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 877962028 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 915973896 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352690 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352690 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014656 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014656 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.543670 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37454.360849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37339.384615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984511 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37376.468043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38057.294964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37574.449093 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28419.550878 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28419.550878 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37291.543670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28549.738114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28842.337636 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29727.315034 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29727.315034 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37376.468043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29845.396471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30097.059079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072071 # number of replacements -system.cpu.dcache.tagsinuse 4072.565350 # Cycle average of tags in use -system.cpu.dcache.total_refs 71946755 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076167 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.653645 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21155511000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.565350 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994279 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40605272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40605272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341476 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076191 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.661567 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21154875000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.471954 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994256 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 40622570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40622570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341456 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341456 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71964026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71964026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71964026 # number of overall hits +system.cpu.dcache.overall_hits::total 71964026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2625435 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2625435 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98296 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98296 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2723731 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2723731 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2723731 # number of overall misses +system.cpu.dcache.overall_misses::total 2723731 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31317831000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31317831000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2109058498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2109058498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33426889498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33426889498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33426889498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33426889498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43248005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43248005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74670210 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74670210 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74670210 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74670210 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060725 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060725 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74687757 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74687757 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74687757 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74687757 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060706 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060706 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003126 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003126 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.973272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.973272 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21247.389983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21247.389983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12267.155737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12267.155737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12267.155737 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32306 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036468 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036468 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036468 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036468 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11928.625542 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11928.625542 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21456.198604 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21456.198604 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12272.463580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.463580 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12272.463580 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32211 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9475 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.400632 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.399578 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066432 # number of writebacks -system.cpu.dcache.writebacks::total 2066432 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631139 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2066104 # number of writebacks +system.cpu.dcache.writebacks::total 2066104 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631384 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631384 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16152 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 16152 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994047 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82124 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82124 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076171 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076171 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21983434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21983434000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1812851998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23796285998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23796285998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23796285998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23796285998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046126 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002612 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027805 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027805 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.531518 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.531518 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22074.570138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11461.621417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11461.621417 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 647536 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647536 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647536 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647536 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076195 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076195 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076195 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076195 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987856500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987856500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833812998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833812998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23821669498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23821669498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23821669498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23821669498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027798 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027798 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027798 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.727250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.727250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22324.369376 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22324.369376 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.714896 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.714896 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index a996ac821..c3d2ef3b8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199845 # Number of seconds simulated -sim_ticks 199845137000 # Number of ticks simulated -final_tick 199845137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199960 # Number of seconds simulated +sim_ticks 199959919500 # Number of ticks simulated +final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125858 # Simulator instruction rate (inst/s) -host_op_rate 141897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49782690 # Simulator tick rate (ticks/s) -host_mem_usage 271600 # Number of bytes of host memory used -host_seconds 4014.35 # Real time elapsed on the host +host_inst_rate 164124 # Simulator instruction rate (inst/s) +host_op_rate 185039 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64955915 # Simulator tick rate (ticks/s) +host_mem_usage 268876 # Number of bytes of host memory used +host_seconds 3078.39 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9264064 # Number of bytes read from this memory -system.physmem.bytes_read::total 9480896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6248064 # Number of bytes written to this memory -system.physmem.bytes_written::total 6248064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3388 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144751 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148139 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97626 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97626 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1085000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46356214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47441214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1085000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1085000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31264529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31264529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31264529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1085000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46356214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78705743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148141 # Total number of read requests seen -system.physmem.writeReqs 97626 # Total number of write requests seen -system.physmem.cpureqs 245778 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9480896 # Total number of bytes read from memory -system.physmem.bytesWritten 6248064 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9480896 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6248064 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9221 # Track reads on a per bank basis +system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory +system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory +system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148088 # Total number of read requests seen +system.physmem.writeReqs 97603 # Total number of write requests seen +system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9477568 # Total number of bytes read from memory +system.physmem.bytesWritten 6246592 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8810 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8975 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9245 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9704 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8950 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9023 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8762 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5947 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6637 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6064 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5787 # Track writes on a per bank basis +system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 199845120000 # Total gap between requests +system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry +system.physmem.totGap 199959894000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148141 # Categorize read packet sizes +system.physmem.readPktSize::6 148088 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97626 # categorize write packet sizes +system.physmem.writePktSize::6 99440 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,69 +138,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1637260686 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4709936686 # Sum of mem lat for all requests -system.physmem.totBusLat 592324000 # Total cycles spent in databus access -system.physmem.totBankLat 2480352000 # Total cycles spent in bank access -system.physmem.avgQLat 11056.52 # Average queueing delay per request -system.physmem.avgBankLat 16749.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31806.49 # Average memory access latency -system.physmem.avgRdBW 47.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.26 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.49 # Data bus utilization in percentage +system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests +system.physmem.totBusLat 740055000 # Total cycles spent in databus access +system.physmem.totBankLat 2530756250 # Total cycles spent in bank access +system.physmem.avgQLat 11482.05 # Average queueing delay per request +system.physmem.avgBankLat 17098.43 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 33580.49 # Average memory access latency +system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.64 # Average write queue length over time -system.physmem.readRowHits 128534 # Number of row buffer hits during reads -system.physmem.writeRowHits 35160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.01 # Row buffer hit rate for writes -system.physmem.avgGap 813148.71 # Average gap between requests -system.cpu.branchPred.lookups 182820446 # Number of BP lookups -system.cpu.branchPred.condPredicted 143128871 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7268870 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92944153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87230072 # Number of BTB hits +system.physmem.avgWrQLen 8.80 # Average write queue length over time +system.physmem.readRowHits 125322 # Number of row buffer hits during reads +system.physmem.writeRowHits 52822 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes +system.physmem.avgGap 813867.39 # Average gap between requests +system.cpu.branchPred.lookups 182791909 # Number of BP lookups +system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.852135 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12684982 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116077 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +244,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399690275 # number of cpu cycles simulated +system.cpu.numCycles 399919840 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119371931 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761680364 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182820446 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99915054 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170174199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35702256 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75350704 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 616 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114527354 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441016 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392530086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.176527 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990721 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222368477 56.65% 56.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14183765 3.61% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22901577 5.83% 66.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22747664 5.80% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20903604 5.33% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11591587 2.95% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13062137 3.33% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11992821 3.06% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52778454 13.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392530086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457405 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.905676 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129024913 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70885415 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158884550 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6176695 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27558513 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26126183 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76772 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825683046 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296199 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27558513 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135608190 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9588825 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46459719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158300780 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15014059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800754331 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1065 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3044118 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8771537 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 204 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954467105 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3501224581 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3501223353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1228 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288214814 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293021 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293019 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41499614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170286842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73502565 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28542432 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15757224 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755181384 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775400 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665429696 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1394216 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187494219 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479993782 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797768 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392530086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.695232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736006 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137153831 34.94% 34.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69768231 17.77% 52.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71497423 18.21% 70.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53360624 13.59% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31181551 7.94% 92.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16101363 4.10% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8735003 2.23% 98.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2914770 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1817290 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392530086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 481185 5.01% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6545421 68.20% 73.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2570325 26.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447832117 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383268 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 86 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153411814 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63802408 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665429696 # Type of FU issued -system.cpu.iq.rate 1.664863 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9596931 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734380418 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947258082 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646140584 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 274 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued +system.cpu.iq.rate 1.663662 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 675026522 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 105 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8582869 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44257287 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42197 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 811123 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16642088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4090 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27558513 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4987467 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372691 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760516980 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1117257 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170286842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73502565 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286858 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219486 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11052 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 811123 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4340984 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003792 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8344776 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 656001968 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150122200 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9427728 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1560196 # number of nop insts executed -system.cpu.iew.exec_refs 212633148 # number of memory reference insts executed -system.cpu.iew.exec_branches 138504923 # Number of branches executed -system.cpu.iew.exec_stores 62510948 # Number of stores executed -system.cpu.iew.exec_rate 1.641276 # Inst execution rate -system.cpu.iew.wb_sent 651119979 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646140600 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374813030 # num instructions producing a value -system.cpu.iew.wb_consumers 646558310 # num instructions consuming a value +system.cpu.iew.exec_nop 1558698 # number of nop insts executed +system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed +system.cpu.iew.exec_branches 138500041 # Number of branches executed +system.cpu.iew.exec_stores 62497101 # Number of stores executed +system.cpu.iew.exec_rate 1.640104 # Inst execution rate +system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374768785 # num instructions producing a value +system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616603 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579705 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189575186 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7194795 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 364971573 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564418 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233675 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157304822 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98491978 26.99% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33807803 9.26% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18748044 5.14% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16202992 4.44% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7453577 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6993904 1.92% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3174450 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22794003 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 364971573 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,199 +487,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22794003 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102713785 # The number of ROB reads -system.cpu.rob.rob_writes 1548767048 # The number of ROB writes -system.cpu.timesIdled 306858 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7160189 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102658217 # The number of ROB reads +system.cpu.rob.rob_writes 1548511592 # The number of ROB writes +system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791093 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791093 # CPI: Total CPI of All Threads -system.cpu.ipc 1.264073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.264073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3059184222 # number of integer regfile reads -system.cpu.int_regfile_writes 752090779 # number of integer regfile writes +system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads +system.cpu.int_regfile_writes 752002162 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210880028 # number of misc regfile reads +system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15058 # number of replacements -system.cpu.icache.tagsinuse 1101.681539 # Cycle average of tags in use -system.cpu.icache.total_refs 114506253 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16915 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6769.509489 # Average number of references to valid blocks. +system.cpu.icache.replacements 15017 # number of replacements +system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use +system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.681539 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537930 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537930 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114506253 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114506253 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114506253 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114506253 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114506253 # number of overall hits -system.cpu.icache.overall_hits::total 114506253 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21101 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21101 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21101 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21101 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21101 # number of overall misses -system.cpu.icache.overall_misses::total 21101 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 452371500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 452371500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 452371500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 452371500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 452371500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 452371500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114527354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114527354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114527354 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114527354 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114527354 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114527354 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits +system.cpu.icache.overall_hits::total 114497128 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses +system.cpu.icache.overall_misses::total 21044 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21438.391545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21438.391545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21438.391545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21438.391545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21438.391545 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35.700000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16997 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16997 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16997 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16997 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16997 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16997 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 339326500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 339326500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339326500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 339326500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4078 # 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mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19963.905395 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19963.905395 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19963.905395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19963.905395 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21831.339149 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21831.339149 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115392 # number of replacements -system.cpu.l2cache.tagsinuse 27104.061391 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781385 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146645 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.147601 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100645092000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23030.603679 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 365.807656 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3707.650056 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702838 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011164 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113149 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827150 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13507 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804164 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817671 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110730 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110730 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247532 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192376 # number of replacements -system.cpu.dcache.tagsinuse 4058.257289 # Cycle average of tags in use -system.cpu.dcache.total_refs 190193687 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196472 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.962088 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4128824000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.257289 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990785 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990785 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136223717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136223717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50992367 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50992367 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488803 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488803 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1192712 # number of replacements +system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use +system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187216084 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187216084 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187216084 # number of overall hits -system.cpu.dcache.overall_hits::total 187216084 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1697690 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1697690 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3246939 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3246939 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 35 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 35 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4944629 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4944629 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4944629 # number of overall misses -system.cpu.dcache.overall_misses::total 4944629 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26054770000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26054770000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58807860452 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58807860452 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 537000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 537000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84862630452 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84862630452 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84862630452 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84862630452 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137921407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137921407 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits +system.cpu.dcache.overall_hits::total 187206164 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses +system.cpu.dcache.overall_misses::total 4943656 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488838 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488838 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192160713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192160713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192160713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192160713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012309 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012309 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059863 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059863 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025732 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025732 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025732 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025732 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15347.189416 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15347.189416 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18111.784808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18111.784808 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15342.857143 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15342.857143 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17162.588023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17162.588023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17162.588023 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16266 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14829 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1654 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 595 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.834341 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 24.922689 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110730 # number of writebacks -system.cpu.dcache.writebacks::total 1110730 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 849485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 849485 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898590 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2898590 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 35 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3748075 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3748075 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3748075 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3748075 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848205 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848205 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348349 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348349 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196554 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196554 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196554 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196554 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11474356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11474356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8274514996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8274514996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19748871496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19748871496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19748871496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19748871496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13527.810494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13527.810494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23753.520165 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23753.520165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16504.789166 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16504.789166 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks +system.cpu.dcache.writebacks::total 1111113 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2768ee697..f32034add 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434475 # Number of seconds simulated -sim_ticks 434474519000 # Number of ticks simulated -final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434532 # Number of seconds simulated +sim_ticks 434531908500 # Number of ticks simulated +final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63257 # Simulator instruction rate (inst/s) -host_op_rate 116969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33237666 # Simulator tick rate (ticks/s) -host_mem_usage 473612 # Number of bytes of host memory used -host_seconds 13071.75 # Real time elapsed on the host +host_inst_rate 91853 # Simulator instruction rate (inst/s) +host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48269802 # Simulator tick rate (ticks/s) +host_mem_usage 425632 # Number of bytes of host memory used +host_seconds 9002.15 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24478784 # Number of bytes read from this memory -system.physmem.bytes_read::total 24687552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796800 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382481 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385743 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293700 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293700 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 480507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56341127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56821634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43263297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56341127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100084930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385745 # Total number of read requests seen -system.physmem.writeReqs 293700 # Total number of write requests seen -system.physmem.cpureqs 892876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24687552 # Total number of bytes read from memory -system.physmem.bytesWritten 18796800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24687552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18796800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 153 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 213431 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24893 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24148 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18446 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385654 # Total number of read requests seen +system.physmem.writeReqs 293648 # Total number of write requests seen +system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24681728 # Total number of bytes read from memory +system.physmem.bytesWritten 18793472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434474502000 # Total gap between requests +system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry +system.physmem.totGap 434531891500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385745 # Categorize read packet sizes +system.physmem.readPktSize::6 385654 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293700 # categorize write packet sizes +system.physmem.writePktSize::6 297032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes +system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,195 +138,194 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests -system.physmem.totBusLat 1542368000 # Total cycles spent in databus access -system.physmem.totBankLat 6530944000 # Total cycles spent in bank access -system.physmem.avgQLat 9127.90 # Average queueing delay per request -system.physmem.avgBankLat 16937.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.34 # Average memory access latency -system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests +system.physmem.totBusLat 1927515000 # Total cycles spent in databus access +system.physmem.totBankLat 6660733750 # Total cycles spent in bank access +system.physmem.avgQLat 8857.09 # Average queueing delay per request +system.physmem.avgBankLat 17278.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31135.12 # Average memory access latency +system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.43 # Average write queue length over time -system.physmem.readRowHits 340663 # Number of row buffer hits during reads -system.physmem.writeRowHits 151214 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes -system.physmem.avgGap 639455.00 # Average gap between requests -system.cpu.branchPred.lookups 215014033 # Number of BP lookups -system.cpu.branchPred.condPredicted 215014033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13139181 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150598539 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147901505 # Number of BTB hits +system.physmem.avgWrQLen 9.81 # Average write queue length over time +system.physmem.readRowHits 331850 # Number of row buffer hits during reads +system.physmem.writeRowHits 191739 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes +system.physmem.avgGap 639674.09 # Average gap between requests +system.cpu.branchPred.lookups 214985170 # Number of BP lookups +system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.209123 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 868949039 # number of cpu cycles simulated +system.cpu.numCycles 869063818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed -system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18484631 2.16% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24605565 2.88% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30659669 3.59% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28862609 3.38% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120157955 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21404699 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 100960761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216593007 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356094891 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355960834 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 134057 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602552155 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1359 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330141203 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512720290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204905378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196472643 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55515054 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034068735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808313369 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 844321 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7763763 50.73% 83.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2595950 16.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718674 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190900507 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -355,84 +354,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438963543 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175730645 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808313369 # Type of FU issued -system.cpu.iq.rate 2.081035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43013 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820889036 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10538 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170573463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued +system.cpu.iq.rate 2.080616 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128618134 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 471778 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270529 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55745634 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12450 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 553 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70029976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17665795 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2858627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034091928 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2374153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512720290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204905820 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6054 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1808225 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 77432 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270529 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9117470 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4488132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13605602 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780566222 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431424657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27747147 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602146985 # number of memory reference insts executed -system.cpu.iew.exec_branches 169282711 # Number of branches executed -system.cpu.iew.exec_stores 170722328 # Number of stores executed -system.cpu.iew.exec_rate 2.049103 # Inst execution rate -system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341647639 # num instructions producing a value -system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value +system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed +system.cpu.iew.exec_branches 169273677 # Number of branches executed +system.cpu.iew.exec_stores 170713056 # Number of stores executed +system.cpu.iew.exec_rate 2.048683 # Inst execution rate +system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341566013 # num instructions producing a value +system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -443,203 +442,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749272924 # The number of ROB reads -system.cpu.rob.rob_writes 4138465929 # The number of ROB writes -system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747864885 # The number of ROB reads +system.cpu.rob.rob_writes 4138016116 # The number of ROB writes +system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050881 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951583 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951583 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357585069 # number of integer regfile reads -system.cpu.int_regfile_writes 1848487641 # number of integer regfile writes -system.cpu.fp_regfile_reads 5173 # number of floating regfile reads +system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads +system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes +system.cpu.fp_regfile_reads 4985 # number of floating regfile reads system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads -system.cpu.icache.replacements 5393 # number of replacements -system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use -system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads +system.cpu.icache.replacements 5428 # number of replacements +system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use +system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits -system.cpu.icache.overall_hits::total 173271214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses -system.cpu.icache.overall_misses::total 224243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits +system.cpu.icache.overall_hits::total 173214256 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 225311 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 225311 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 225311 # number of overall misses +system.cpu.icache.overall_misses::total 225311 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1422825499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1422825499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1422825499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1422825499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1422825499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1422825499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173439567 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173439567 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173439567 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173439567 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173439567 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173439567 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001299 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001299 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001299 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001299 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001299 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001299 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6314.940234 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52930.293236 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462552 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151808 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462552 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151808 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60784.829721 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57511.434924 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57570.530059 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 33.633594 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 33.633594 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50233.681222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50233.681222 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53637.165515 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60784.829721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.800676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53637.165515 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,168 +647,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293700 # number of writebacks -system.cpu.l2cache.writebacks::total 293700 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3263 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179015 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 213396 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 213396 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206766 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206766 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382518 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141813443 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6996065941 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137879384 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343894304 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343894304 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141813443 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339960245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15481773688 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141813443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339960245 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15481773688 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 293648 # number of writebacks +system.cpu.l2cache.writebacks::total 293648 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175686 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178916 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 214369 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 214369 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385687 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156219180 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7929842195 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8086061375 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2149350076 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2149350076 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7799617575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7799617575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156219180 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15729459770 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15885678950 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156219180 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15729459770 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15885678950 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268040 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268040 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151839 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43461.061293 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39806.465594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39873.079820 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151808 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151808 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48365.071207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45136.449091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45194.735938 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.403426 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.403426 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37721.041998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37721.041998 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529684 # number of replacements -system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use -system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits -system.cpu.dcache.overall_hits::total 404771823 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses -system.cpu.dcache.overall_misses::total 3896832 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529546 # number of replacements +system.cpu.dcache.tagsinuse 4087.815974 # Cycle average of tags in use +system.cpu.dcache.total_refs 405263721 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533642 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.953032 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits +system.cpu.dcache.overall_hits::total 404682244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses +system.cpu.dcache.overall_misses::total 3901645 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks -system.cpu.dcache.writebacks::total 2331225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks +system.cpu.dcache.writebacks::total 2331178 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 7980de17a..6c858f4a6 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139847 # Number of seconds simulated -sim_ticks 139846906500 # Number of ticks simulated -final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139855 # Number of seconds simulated +sim_ticks 139855372500 # Number of ticks simulated +final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94955 # Simulator instruction rate (inst/s) -host_op_rate 94955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33309069 # Simulator tick rate (ticks/s) -host_mem_usage 278532 # Number of bytes of host memory used -host_seconds 4198.46 # Real time elapsed on the host +host_inst_rate 164436 # Simulator instruction rate (inst/s) +host_op_rate 164436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57685897 # Simulator tick rate (ticks/s) +host_mem_usage 230388 # Number of bytes of host memory used +host_seconds 2424.43 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1537224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1816386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3353610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1537224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1537224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1816386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3353610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139846854500 # Total gap between requests +system.physmem.totGap 139855320500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 39390791 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 174626791 # Sum of mem lat for all requests -system.physmem.totBusLat 29312000 # Total cycles spent in databus access -system.physmem.totBankLat 105924000 # Total cycles spent in bank access -system.physmem.avgQLat 5375.38 # Average queueing delay per request -system.physmem.avgBankLat 14454.69 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23830.08 # Average memory access latency +system.physmem.totQLat 47661305 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests +system.physmem.totBusLat 36640000 # Total cycles spent in databus access +system.physmem.totBankLat 113038750 # Total cycles spent in bank access +system.physmem.avgQLat 6504.00 # Average queueing delay per request +system.physmem.avgBankLat 15425.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26929.59 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6444 # Number of row buffer hits during reads +system.physmem.readRowHits 6132 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19083904.82 # Average gap between requests -system.cpu.branchPred.lookups 53489670 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted +system.physmem.avgGap 19085060.11 # Average gap between requests +system.cpu.branchPred.lookups 53489671 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits +system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754613 # DTB read hits +system.cpu.dtb.read_hits 94754610 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754634 # DTB read accesses -system.cpu.dtb.write_hits 73521103 # DTB write hits +system.cpu.dtb.read_accesses 94754631 # DTB read accesses +system.cpu.dtb.write_hits 73521101 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521138 # DTB write accesses -system.cpu.dtb.data_hits 168275716 # DTB hits +system.cpu.dtb.write_accesses 73521136 # DTB write accesses +system.cpu.dtb.data_hits 168275711 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275772 # DTB accesses -system.cpu.itb.fetch_hits 48611354 # ITB hits +system.cpu.dtb.data_accesses 168275767 # DTB accesses +system.cpu.itb.fetch_hits 48611339 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655874 # ITB accesses +system.cpu.itb.fetch_accesses 48655859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279693814 # number of cpu cycles simulated +system.cpu.numCycles 279710746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722447 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631948 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828429 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484563 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400729 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13387179 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306635 # Number of cycles cpu stages are processed. -system.cpu.activity 95.213631 # Percentage of cycles cpu is active +system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed. +system.cpu.activity 95.207865 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -266,124 +266,124 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701577 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701577 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425361 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.425361 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 77946120 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747694 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.131625 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107042067 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651747 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.728840 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102478598 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215216 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.360435 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 180949238 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.304526 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90225845 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467969 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.741208 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1831.257835 # Cycle average of tags in use -system.cpu.icache.total_refs 48606847 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use +system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.714322 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.257835 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894169 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606847 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606847 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606847 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606847 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606847 # number of overall hits -system.cpu.icache.overall_hits::total 48606847 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4507 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4507 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4507 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4507 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4507 # number of overall misses -system.cpu.icache.overall_misses::total 4507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 195448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 195448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 195448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 195448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 195448500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611354 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611354 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611354 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611354 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611354 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits +system.cpu.icache.overall_hits::total 48606831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses +system.cpu.icache.overall_misses::total 4508 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43365.542489 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43365.542489 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43365.542489 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43365.542489 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170297500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170297500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170297500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170297500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43632.462209 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43632.462209 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43632.462209 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3907.773744 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.670185 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2909.388487 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.715072 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088787 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119256 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 160908500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45014500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 205923000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 151967500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 160908500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 196982000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 357890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 160908500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 196982000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 357890500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47903.691575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54629.247573 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49228.544107 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48320.349762 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48838.769105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47903.691575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49630.133535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48838.769105 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118404553 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 34670717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153075270 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 112966799 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118404553 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147637516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 266042069 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118404553 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147637516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 266042069 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35249.941352 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42076.112864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36594.613913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35919.490938 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35249.941352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37197.660872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36304.867495 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.615449 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254423 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.704961 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.615449 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802152 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501238 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501238 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254423 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254423 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254423 # number of overall hits -system.cpu.dcache.overall_hits::total 168254423 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19491 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19491 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20795 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20795 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20795 # number of overall misses -system.cpu.dcache.overall_misses::total 20795 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64310000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64310000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 715525500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 715525500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 779835500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 779835500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 779835500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits +system.cpu.dcache.overall_hits::total 168254397 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses +system.cpu.dcache.overall_misses::total 20821 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -556,32 +556,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49317.484663 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49317.484663 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36710.558719 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36710.558719 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37501.106035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37501.106035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16708 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.229907 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16289 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16289 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16643 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16643 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16643 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47442500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 203182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 203182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49939.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48638.194878 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48935.934489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48935.934489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 078219244..f63466b63 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077336 # Number of seconds simulated -sim_ticks 77336466500 # Number of ticks simulated -final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077334 # Number of seconds simulated +sim_ticks 77333663500 # Number of ticks simulated +final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141610 # Simulator instruction rate (inst/s) -host_op_rate 141610 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29159685 # Simulator tick rate (ticks/s) -host_mem_usage 279556 # Number of bytes of host memory used -host_seconds 2652.17 # Real time elapsed on the host +host_inst_rate 196388 # Simulator instruction rate (inst/s) +host_op_rate 196388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40437661 # Simulator tick rate (ticks/s) +host_mem_usage 232448 # Number of bytes of host memory used +host_seconds 1912.42 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory -system.physmem.bytes_read::total 476288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7442 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2855057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3303590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6158647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2855057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2855057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3303590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6158647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7442 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory +system.physmem.bytes_read::total 476672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7448 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7442 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476288 # Total number of bytes read from memory +system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476672 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476288 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 480 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 405 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 545 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77336398000 # Total gap between requests +system.physmem.totGap 77333595000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7442 # Categorize read packet sizes +system.physmem.readPktSize::6 7448 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 40921923 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 178783923 # Sum of mem lat for all requests -system.physmem.totBusLat 29768000 # Total cycles spent in databus access -system.physmem.totBankLat 108094000 # Total cycles spent in bank access -system.physmem.avgQLat 5498.78 # Average queueing delay per request -system.physmem.avgBankLat 14524.86 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24023.64 # Average memory access latency +system.physmem.totQLat 53873160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests +system.physmem.totBusLat 37240000 # Total cycles spent in databus access +system.physmem.totBankLat 115898750 # Total cycles spent in bank access +system.physmem.avgQLat 7233.24 # Average queueing delay per request +system.physmem.avgBankLat 15561.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27794.30 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6502 # Number of row buffer hits during reads +system.physmem.readRowHits 6188 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10391883.63 # Average gap between requests -system.cpu.branchPred.lookups 50254079 # Number of BP lookups -system.cpu.branchPred.condPredicted 29238788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1202354 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26185724 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23237791 # Number of BTB hits +system.physmem.avgGap 10383135.74 # Average gap between requests +system.cpu.branchPred.lookups 50250166 # Number of BP lookups +system.cpu.branchPred.condPredicted 29237479 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25926395 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.742213 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9009650 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.591056 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791760 # DTB read hits -system.cpu.dtb.read_misses 77689 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101869449 # DTB read accesses -system.cpu.dtb.write_hits 78414713 # DTB write hits -system.cpu.dtb.write_misses 1485 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 78416198 # DTB write accesses -system.cpu.dtb.data_hits 180206473 # DTB hits -system.cpu.dtb.data_misses 79174 # DTB misses -system.cpu.dtb.data_acv 48607 # DTB access violations -system.cpu.dtb.data_accesses 180285647 # DTB accesses -system.cpu.itb.fetch_hits 50234226 # ITB hits -system.cpu.itb.fetch_misses 374 # ITB misses +system.cpu.dtb.read_hits 101791406 # DTB read hits +system.cpu.dtb.read_misses 78057 # DTB read misses +system.cpu.dtb.read_acv 48605 # DTB read access violations +system.cpu.dtb.read_accesses 101869463 # DTB read accesses +system.cpu.dtb.write_hits 78427886 # DTB write hits +system.cpu.dtb.write_misses 1487 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 78429373 # DTB write accesses +system.cpu.dtb.data_hits 180219292 # DTB hits +system.cpu.dtb.data_misses 79544 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180298836 # DTB accesses +system.cpu.itb.fetch_hits 50219857 # ITB hits +system.cpu.itb.fetch_misses 371 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50234600 # ITB accesses +system.cpu.itb.fetch_accesses 50220228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,238 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154672935 # number of cpu cycles simulated +system.cpu.numCycles 154667329 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32247441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78789768 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6120508 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19691338 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9175 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50234226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 409224 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.904750 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75702065 49.00% 49.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4283300 2.77% 51.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6877325 4.45% 56.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5367764 3.47% 59.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11752749 7.61% 67.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7805511 5.05% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5606089 3.63% 75.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1832349 1.19% 77.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35264681 22.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154491833 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324905 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.901349 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56470400 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15041439 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74166392 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3937938 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4875664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9475904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4278 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444843868 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12237 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4875664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59604786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4871643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 401502 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75064420 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9673818 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440376827 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19255 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7994088 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287328410 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578957076 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306311574 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272645502 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9471001 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4302 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27796081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36810 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27798585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104665260 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80564409 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8907082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6393839 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408148309 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401749536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 973581 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32442077 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15221672 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 73 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154491833 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600458 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28272588 18.30% 18.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25828142 16.72% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25544882 16.53% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24283906 15.72% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21283015 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15483551 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8467826 5.48% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4000243 2.59% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1327680 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154491833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34079 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57868 0.49% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5831 0.05% 0.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5354 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1930027 16.34% 17.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748928 14.81% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5061323 42.85% 74.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2967669 25.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155748072 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126114 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32812204 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7499410 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793875 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556840 4.12% 54.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1578743 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103369723 25.73% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79230974 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401749536 # Type of FU issued -system.cpu.iq.rate 2.597413 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11811079 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029399 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634008068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260192564 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234721556 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336767497 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180447135 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161345688 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241449037 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172077997 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15060402 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued +system.cpu.iq.rate 2.597191 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9910773 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111367 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 49045 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7043680 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48930 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2589 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4875664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2512017 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367237 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432932337 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125430 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104665260 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80564409 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 91 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 94 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 49045 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 948042 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 404840 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1352882 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398223090 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3526446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48930 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24783740 # number of nop insts executed -system.cpu.iew.exec_refs 180334326 # number of memory reference insts executed -system.cpu.iew.exec_branches 46552042 # Number of branches executed -system.cpu.iew.exec_stores 78416231 # Number of stores executed -system.cpu.iew.exec_rate 2.574614 # Inst execution rate -system.cpu.iew.wb_sent 396695169 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396067244 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193570018 # num instructions producing a value -system.cpu.iew.wb_consumers 271138332 # num instructions consuming a value +system.cpu.iew.exec_nop 24785464 # number of nop insts executed +system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed +system.cpu.iew.exec_branches 46544583 # Number of branches executed +system.cpu.iew.exec_stores 78429410 # Number of stores executed +system.cpu.iew.exec_rate 2.574493 # Inst execution rate +system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193534236 # num instructions producing a value +system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.560676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713916 # average fanout of values written-back +system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34296903 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1198153 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149616169 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.664582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55282421 36.95% 36.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22517619 15.05% 52.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13057157 8.73% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11465050 7.66% 68.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8178831 5.47% 73.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460295 3.65% 77.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171821 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3274025 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25208950 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149616169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -469,192 +469,192 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25208950 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557365728 # The number of ROB reads -system.cpu.rob.rob_writes 870806965 # The number of ROB writes -system.cpu.timesIdled 3403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 181102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557294459 # The number of ROB reads +system.cpu.rob.rob_writes 870687579 # The number of ROB writes +system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411830 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411830 # CPI: Total CPI of All Threads -system.cpu.ipc 2.428187 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.428187 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398054965 # number of integer regfile reads -system.cpu.int_regfile_writes 170113807 # number of integer regfile writes -system.cpu.fp_regfile_reads 156515246 # number of floating regfile reads -system.cpu.fp_regfile_writes 104037972 # number of floating regfile writes +system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads +system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398027050 # number of integer regfile reads +system.cpu.int_regfile_writes 170092718 # number of integer regfile writes +system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads +system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2129 # number of replacements -system.cpu.icache.tagsinuse 1832.082194 # Cycle average of tags in use -system.cpu.icache.total_refs 50228789 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4056 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12383.823718 # Average number of references to valid blocks. +system.cpu.icache.replacements 2144 # number of replacements +system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use +system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.082194 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894571 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50228789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50228789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50228789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50228789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50228789 # number of overall hits -system.cpu.icache.overall_hits::total 50228789 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5437 # number of overall misses -system.cpu.icache.overall_misses::total 5437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 226400000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 226400000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 226400000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 226400000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 226400000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50234226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50234226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50234226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50234226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50234226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000108 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000108 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000108 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000108 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000108 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41640.610631 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41640.610631 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41640.610631 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41640.610631 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50214380 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50214380 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50214380 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50214380 # number of overall hits +system.cpu.icache.overall_hits::total 50214380 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses +system.cpu.icache.overall_misses::total 5477 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50219857 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50219857 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50219857 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122247748 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151000497 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273248245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122247748 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151000497 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273248245 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.868819 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.854171 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981197 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35926.540402 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35434.129855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37825.775802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36717.044477 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 4316 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3132 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981203 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 780 # number of replacements -system.cpu.dcache.tagsinuse 3297.205890 # Cycle average of tags in use -system.cpu.dcache.total_refs 159967351 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use +system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38251.399091 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3297.205890 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.804982 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 86466482 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86466482 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500862 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 159967344 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 159967344 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 159967344 # number of overall hits -system.cpu.dcache.overall_hits::total 159967344 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21677 # number of overall misses -system.cpu.dcache.overall_misses::total 21677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83400000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83400000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 721598130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 721598130 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 804998130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 804998130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 804998130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86468292 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86468292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159960712 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159989021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159989021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159989021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159989021 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46077.348066 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46077.348066 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36321.444103 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36321.444103 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37136.048807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37136.048807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23923 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.912837 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 657 # number of writebacks system.cpu.dcache.writebacks::total 657 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 819 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 819 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 991 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 991 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16577 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16577 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17398 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 990 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3192 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51550500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 155023000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 206573500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 206573500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 206573500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -811,14 +811,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52018.668012 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48581.322469 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49395.863223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49395.863223 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index cecd350a2..c2e0aed87 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068072 # Number of seconds simulated -sim_ticks 68071881000 # Number of ticks simulated -final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068358 # Number of seconds simulated +sim_ticks 68358106500 # Number of ticks simulated +final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102151 # Simulator instruction rate (inst/s) -host_op_rate 130595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25467625 # Simulator tick rate (ticks/s) -host_mem_usage 296712 # Number of bytes of host memory used -host_seconds 2672.88 # Real time elapsed on the host +host_inst_rate 148173 # Simulator instruction rate (inst/s) +host_op_rate 189432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37097000 # Simulator tick rate (ticks/s) +host_mem_usage 250340 # Number of bytes of host memory used +host_seconds 1842.69 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2846873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4002357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6849230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2846873 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2846873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4002357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6849230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 465728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7278 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 466240 # Total number of bytes read from memory +system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 465728 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 466240 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 456 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 360 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68071860500 # Total gap between requests +system.physmem.totGap 68358086000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7286 # Categorize read packet sizes +system.physmem.readPktSize::6 7278 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 2 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 38841760 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 170087760 # Sum of mem lat for all requests -system.physmem.totBusLat 29144000 # Total cycles spent in databus access -system.physmem.totBankLat 102102000 # Total cycles spent in bank access -system.physmem.avgQLat 5331.01 # Average queueing delay per request -system.physmem.avgBankLat 14013.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23344.46 # Average memory access latency -system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 46727256 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests +system.physmem.totBusLat 36390000 # Total cycles spent in databus access +system.physmem.totBankLat 109065000 # Total cycles spent in bank access +system.physmem.avgQLat 6420.34 # Average queueing delay per request +system.physmem.avgBankLat 14985.57 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 26405.92 # Average memory access latency +system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6372 # Number of row buffer hits during reads +system.physmem.readRowHits 6070 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9342830.15 # Average gap between requests -system.cpu.branchPred.lookups 41692065 # Number of BP lookups -system.cpu.branchPred.condPredicted 21046025 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1612310 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25558633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16675018 # Number of BTB hits +system.physmem.avgGap 9392427.32 # Average gap between requests +system.cpu.branchPred.lookups 41732744 # Number of BP lookups +system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.242214 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6736046 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 7190 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,100 +237,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136143763 # number of cpu cycles simulated +system.cpu.numCycles 136716214 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23411064 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70618145 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6665842 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21550456 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1364 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed +system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37376595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 521732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.990728 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456678 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65940392 48.51% 48.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6730475 4.95% 53.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5637804 4.15% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5998950 4.41% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4879102 3.59% 65.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4141679 3.05% 68.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3188425 2.35% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4149669 3.05% 74.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35266625 25.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 135933121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.306236 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325886 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45271721 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16691056 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66469199 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2527476 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4973669 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7265289 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69057 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 400237870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218381 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4973669 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50782794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1926905 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 308736 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63418534 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14522483 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 392567341 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 52 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667501 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10227766 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1022 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431145358 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2325492453 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1253893551 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1071598902 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46579165 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11899 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11898 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36419091 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103284417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91190896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4278404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5313371 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383399978 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373603209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1225399 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 33612220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 83720105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 135933121 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.748434 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.022451 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24617806 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19905628 14.64% 32.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20463769 15.05% 47.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18134866 13.34% 61.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23975475 17.64% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15748338 11.59% 90.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799560 6.47% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3376937 2.48% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 910742 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 135933121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9041 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4688 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -349,127 +349,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46127 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7573 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 401 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 189986 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6027 0.03% 1.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241589 1.36% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9303270 52.42% 55.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7940124 44.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126062452 33.74% 33.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174186 0.58% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6778330 1.81% 36.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468082 2.27% 38.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426363 0.92% 39.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600385 0.43% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20905129 5.60% 45.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7170133 1.92% 47.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133112 1.91% 49.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175289 0.05% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101416985 27.15% 76.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88292763 23.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373603209 # Type of FU issued -system.cpu.iq.rate 2.744182 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17748829 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047507 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 652552700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 286781782 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249670215 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249561067 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130267469 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118091463 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 262665125 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128686913 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11143467 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued +system.cpu.iq.rate 2.736374 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8635669 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113833 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14304 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8815313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 179767 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4973669 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 290169 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 43007 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 383424336 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 947805 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103284417 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91190896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 376 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14304 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1257323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 355165 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1612488 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 369752091 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100205261 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3851118 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1499 # number of nop insts executed -system.cpu.iew.exec_refs 187415465 # number of memory reference insts executed -system.cpu.iew.exec_branches 38269539 # Number of branches executed -system.cpu.iew.exec_stores 87210204 # Number of stores executed -system.cpu.iew.exec_rate 2.715894 # Inst execution rate -system.cpu.iew.wb_sent 368418252 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 367761678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182872307 # num instructions producing a value -system.cpu.iew.wb_consumers 363527613 # num instructions consuming a value +system.cpu.iew.exec_nop 1542 # number of nop insts executed +system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed +system.cpu.iew.exec_branches 38278467 # Number of branches executed +system.cpu.iew.exec_stores 87368516 # Number of stores executed +system.cpu.iew.exec_rate 2.707829 # Inst execution rate +system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back +system.cpu.iew.wb_producers 183056844 # num instructions producing a value +system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.701275 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503049 # average fanout of values written-back +system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34359338 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1543637 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130959452 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.665444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660816 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34245793 26.15% 26.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28403736 21.69% 47.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13297993 10.15% 57.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11400251 8.71% 66.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13789663 10.53% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417902 5.66% 82.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3851196 2.94% 85.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3914096 2.99% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14638822 11.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130959452 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -480,198 +480,198 @@ system.cpu.commit.branches 36546710 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14638822 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 499742506 # The number of ROB reads -system.cpu.rob.rob_writes 771826211 # The number of ROB writes -system.cpu.timesIdled 6299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 210642 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 501013476 # The number of ROB reads +system.cpu.rob.rob_writes 773587232 # The number of ROB writes +system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.498628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.498628 # CPI: Total CPI of All Threads -system.cpu.ipc 2.005503 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.005503 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1767787991 # number of integer regfile reads -system.cpu.int_regfile_writes 232574551 # number of integer regfile writes -system.cpu.fp_regfile_reads 188239368 # number of floating regfile reads -system.cpu.fp_regfile_writes 132566541 # number of floating regfile writes -system.cpu.misc_regfile_reads 566998882 # number of misc regfile reads +system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads +system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads +system.cpu.int_regfile_writes 232882500 # number of integer regfile writes +system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads +system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes +system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13918 # number of replacements -system.cpu.icache.tagsinuse 1846.260886 # Cycle average of tags in use -system.cpu.icache.total_refs 37359528 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15804 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2363.928626 # Average number of references to valid blocks. +system.cpu.icache.replacements 13893 # number of replacements +system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use +system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1846.260886 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.901495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.901495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37359528 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37359528 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37359528 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37359528 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37359528 # number of overall hits -system.cpu.icache.overall_hits::total 37359528 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17066 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17066 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17066 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17066 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17066 # number of overall misses -system.cpu.icache.overall_misses::total 17066 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 359194498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 359194498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 359194498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 359194498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 359194498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37376594 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37376594 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37376594 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37376594 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37376594 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21047.374780 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21047.374780 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21047.374780 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21047.374780 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 550 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits +system.cpu.icache.overall_hits::total 37534809 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses +system.cpu.icache.overall_misses::total 17059 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.947368 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1259 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1259 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1259 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1259 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1259 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15807 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15807 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15807 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15807 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15807 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 293030998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 293030998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 293030998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 293030998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18538.052635 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18538.052635 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18538.052635 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18538.052635 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1275 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296328498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 296328498 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296328498 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 296328498 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000420 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000420 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000420 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356894 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191648 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356894 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36563.581380 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37980.273288 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37024.345511 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33736.643547 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36563.581380 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35192.058022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35762.239775 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3109.588822 # Cycle average of tags in use -system.cpu.dcache.total_refs 170749767 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use +system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37038.995011 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3109.588822 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.759177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88696383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88696383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031533 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031533 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170727916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170727916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170727916 # number of overall hits -system.cpu.dcache.overall_hits::total 170727916 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4041 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4041 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21132 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21132 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits +system.cpu.dcache.overall_hits::total 170903328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25173 # number of overall misses -system.cpu.dcache.overall_misses::total 25173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 164980000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 164980000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 832721164 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 832721164 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 115000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 997701164 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 997701164 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 997701164 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88700424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88700424 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses +system.cpu.dcache.overall_misses::total 25163 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170753089 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170753089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170753089 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170753089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses @@ -805,52 +805,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40826.528087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40826.528087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39405.695817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39405.695817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39633.780797 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39633.780797 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13427 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 430 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.225581 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.583333 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks -system.cpu.dcache.writebacks::total 1039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2244 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2244 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18317 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks +system.cpu.dcache.writebacks::total 1043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20561 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20561 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1797 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1797 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2815 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2815 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80314500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 132089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212404000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212404000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212404000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44693.656093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46923.445826 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46054.640069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46054.640069 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8443dfdcb..5cf480155 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.626365 # Number of seconds simulated -sim_ticks 626365181000 # Number of ticks simulated -final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629815 # Number of seconds simulated +sim_ticks 629814900000 # Number of ticks simulated +final_tick 629814900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114572 # Simulator instruction rate (inst/s) -host_op_rate 114572 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39364843 # Simulator tick rate (ticks/s) -host_mem_usage 295992 # Number of bytes of host memory used -host_seconds 15911.79 # Real time elapsed on the host +host_inst_rate 180734 # Simulator instruction rate (inst/s) +host_op_rate 180734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62438874 # Simulator tick rate (ticks/s) +host_mem_usage 248904 # Number of bytes of host memory used +host_seconds 10086.90 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30294656 # Number of bytes read from this memory -system.physmem.bytes_read::total 30470720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295232 # Number of bytes read from this memory +system.physmem.bytes_read::total 30471488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473354 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476117 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 281088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48365805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48646893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 281088 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6836446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6836446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 281088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48365805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55483340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476105 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 279854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48101803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48381656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 279854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6799001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6799001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 279854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48101803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55180657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476117 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30470720 # Total number of bytes read from memory +system.physmem.cpureqs 543025 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30471488 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30470720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30471488 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 93 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29636 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29984 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29791 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4160 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 29663 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29780 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 626365119500 # Total gap between requests +system.physmem.totGap 629814837500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476105 # Categorize read packet sizes +system.physmem.readPktSize::6 476117 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 406602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 406568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2909 # Wh system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,56 +171,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2248288249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 16547544249 # Sum of mem lat for all requests -system.physmem.totBusLat 1904048000 # Total cycles spent in databus access -system.physmem.totBankLat 12395208000 # Total cycles spent in bank access -system.physmem.avgQLat 4723.18 # Average queueing delay per request -system.physmem.avgBankLat 26039.70 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34762.87 # Average memory access latency -system.physmem.avgRdBW 48.65 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 2509077325 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20518523575 # Sum of mem lat for all requests +system.physmem.totBusLat 2380165000 # Total cycles spent in databus access +system.physmem.totBankLat 15629281250 # Total cycles spent in bank access +system.physmem.avgQLat 5270.81 # Average queueing delay per request +system.physmem.avgBankLat 32832.35 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43103.15 # Average memory access latency +system.physmem.avgRdBW 48.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 265467 # Number of row buffer hits during reads -system.physmem.writeRowHits 48790 # Number of row buffer hits during writes -system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes -system.physmem.avgGap 1153499.31 # Average gap between requests -system.cpu.branchPred.lookups 388924238 # Number of BP lookups -system.cpu.branchPred.condPredicted 255857711 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25855826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 319270007 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258448229 # Number of BTB hits +system.physmem.readRowHits 143855 # Number of row buffer hits during reads +system.physmem.writeRowHits 46184 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes +system.physmem.avgGap 1159826.60 # Average gap between requests +system.cpu.branchPred.lookups 389306486 # Number of BP lookups +system.cpu.branchPred.condPredicted 255918117 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25837227 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 318716729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258426851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.949736 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57345473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6929 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.083554 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57314223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6830 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522560373 # DTB read hits -system.cpu.dtb.read_misses 588728 # DTB read misses +system.cpu.dtb.read_hits 523161150 # DTB read hits +system.cpu.dtb.read_misses 589917 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 523149101 # DTB read accesses -system.cpu.dtb.write_hits 283071161 # DTB write hits -system.cpu.dtb.write_misses 50270 # DTB write misses +system.cpu.dtb.read_accesses 523751067 # DTB read accesses +system.cpu.dtb.write_hits 283054328 # DTB write hits +system.cpu.dtb.write_misses 50219 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283121431 # DTB write accesses -system.cpu.dtb.data_hits 805631534 # DTB hits -system.cpu.dtb.data_misses 638998 # DTB misses +system.cpu.dtb.write_accesses 283104547 # DTB write accesses +system.cpu.dtb.data_hits 806215478 # DTB hits +system.cpu.dtb.data_misses 640136 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 806270532 # DTB accesses -system.cpu.itb.fetch_hits 395323042 # ITB hits -system.cpu.itb.fetch_misses 713 # ITB misses +system.cpu.dtb.data_accesses 806855614 # DTB accesses +system.cpu.itb.fetch_hits 394785394 # ITB hits +system.cpu.itb.fetch_misses 699 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 395323755 # ITB accesses +system.cpu.itb.fetch_accesses 394786093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,98 +234,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1252730363 # number of cpu cycles simulated +system.cpu.numCycles 1259629801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315793702 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630639053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158095234 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 69542401 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6974 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 395323042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11287657 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.637399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141502 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 410360591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3276218906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 389306486 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315741074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 630494032 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158021665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72839727 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7225 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394785394 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10887979 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.630661 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 611816578 49.24% 49.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57562553 4.63% 53.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43380535 3.49% 57.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71885087 5.79% 63.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129158557 10.40% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46353903 3.73% 77.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41221359 3.32% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7475471 0.60% 81.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233601588 18.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614903336 49.37% 49.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57906135 4.65% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43369742 3.48% 57.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71861713 5.77% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128784934 10.34% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45918421 3.69% 77.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41219044 3.31% 80.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7530301 0.60% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 233903742 18.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1242455631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310461 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.615768 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438637304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56111569 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606899212 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9069214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131738332 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31728331 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12429 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3195294876 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46495 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131738332 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467849375 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 21501203 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 26667 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586406570 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 34933484 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3096787172 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15151 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28695106 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2055570524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3581032022 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3460282692 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120749330 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1245397368 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309064 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.600938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438252598 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 59249665 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 607151892 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9059684 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131683529 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32106155 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12464 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3195982000 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46456 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131683529 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467489876 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24458626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 586624719 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35112981 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3097789893 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 99 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15390 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28842141 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2055592035 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3582007579 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3461235411 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120772168 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 670601454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4229 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 95 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109203185 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 744330520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351486216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69160897 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8862018 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2624452005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 84 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160789811 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17925786 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 801345385 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726874664 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1242455631 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.739128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803652 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 670622965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 110 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109569448 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 744863024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351426191 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68774306 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8838853 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2625568629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 106 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2161657606 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17941272 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802459111 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 727402983 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 67 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1245397368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803838 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 445618907 35.87% 35.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 197093468 15.86% 51.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251212495 20.22% 71.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120765174 9.72% 81.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104645405 8.42% 90.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79514591 6.40% 96.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24185782 1.95% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17651908 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767901 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 448194916 35.99% 35.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 197399515 15.85% 51.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251498314 20.19% 72.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120129049 9.65% 81.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104781180 8.41% 90.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79785428 6.41% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24208472 1.94% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17632328 1.42% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768166 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1242455631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1245397368 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146234 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146254 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available @@ -354,118 +354,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25650345 69.73% 72.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9987945 27.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25630359 69.68% 72.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10007683 27.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234634682 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851271 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589669482 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293155183 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1235285403 57.15% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851426 1.29% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589902835 27.29% 86.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293138748 13.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160789811 # Type of FU issued -system.cpu.iq.rate 1.724864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36784524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017024 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5467643878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3337715121 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990557348 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101685 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88155822 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610149 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2120121697 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449886 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62086371 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2161657606 # Type of FU issued +system.cpu.iq.rate 1.716105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36784296 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017017 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5472336078 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3339899399 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1991115322 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151102070 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88201964 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73610146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2120988960 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77450190 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62844771 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 233260494 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21308 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76027 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140691320 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 233792998 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 726346 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76067 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140631295 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4419 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2184 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2432 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131738332 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7963688 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 401158 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987881141 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 737486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 744330520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351486216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 84 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 191221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1459 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76027 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25850018 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 29386 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25879404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066687986 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 523149239 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94101825 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131683529 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10419712 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 524131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2988971416 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 730880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 744863024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351426191 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 106 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195253 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76067 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25831488 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28075 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25859563 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2067932709 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 523751206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93724897 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363429052 # number of nop insts executed -system.cpu.iew.exec_refs 806271170 # number of memory reference insts executed -system.cpu.iew.exec_branches 277685226 # Number of branches executed -system.cpu.iew.exec_stores 283121931 # Number of stores executed -system.cpu.iew.exec_rate 1.649747 # Inst execution rate -system.cpu.iew.wb_sent 2066566988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2064167497 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1181646251 # num instructions producing a value -system.cpu.iew.wb_consumers 1754266128 # num instructions consuming a value +system.cpu.iew.exec_nop 363402681 # number of nop insts executed +system.cpu.iew.exec_refs 806856273 # number of memory reference insts executed +system.cpu.iew.exec_branches 278042301 # Number of branches executed +system.cpu.iew.exec_stores 283105067 # Number of stores executed +system.cpu.iew.exec_rate 1.641699 # Inst execution rate +system.cpu.iew.wb_sent 2067106315 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2064725468 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181149065 # num instructions producing a value +system.cpu.iew.wb_consumers 1753530061 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.647735 # insts written-back per cycle +system.cpu.iew.wb_rate 1.639153 # insts written-back per cycle system.cpu.iew.wb_fanout 0.673584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961921272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 963038308 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25843781 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1110717299 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.808730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509348 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25825176 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1113713839 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.803863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.507965 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 491335332 44.24% 44.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228930715 20.61% 64.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119800633 10.79% 75.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58838434 5.30% 80.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50772069 4.57% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24138536 2.17% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19157540 1.72% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16738195 1.51% 90.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101005845 9.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 494406511 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228855545 20.55% 64.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119827890 10.76% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58850017 5.28% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50714183 4.55% 85.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24146625 2.17% 87.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19124586 1.72% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16719001 1.50% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101069481 9.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1110717299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1113713839 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101005845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101069481 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3974983920 # The number of ROB reads -system.cpu.rob.rob_writes 6073558017 # The number of ROB writes -system.cpu.timesIdled 212495 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10274732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3979033860 # The number of ROB reads +system.cpu.rob.rob_writes 6075737407 # The number of ROB writes +system.cpu.timesIdled 331555 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14232433 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.687164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.687164 # CPI: Total CPI of All Threads -system.cpu.ipc 1.455256 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.455256 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2628560765 # number of integer regfile reads -system.cpu.int_regfile_writes 1497106363 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811457 # number of floating regfile reads -system.cpu.fp_regfile_writes 52660996 # number of floating regfile writes +system.cpu.cpi 0.690949 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690949 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447285 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2629419671 # number of integer regfile reads +system.cpu.int_regfile_writes 1497304474 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811610 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661263 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 8336 # number of replacements -system.cpu.icache.tagsinuse 1656.236510 # Cycle average of tags in use -system.cpu.icache.total_refs 395310182 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1655.843165 # Cycle average of tags in use +system.cpu.icache.total_refs 394772509 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10048 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39342.175756 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 39288.665307 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1656.236510 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.808709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.808709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 395310182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 395310182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 395310182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 395310182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 395310182 # number of overall hits -system.cpu.icache.overall_hits::total 395310182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12860 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12860 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12860 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12860 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12860 # number of overall misses -system.cpu.icache.overall_misses::total 12860 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 302484999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 302484999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 302484999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 302484999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 302484999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 395323042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 395323042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 395323042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 395323042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 395323042 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1655.843165 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808517 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808517 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394772509 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394772509 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394772509 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394772509 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394772509 # number of overall hits +system.cpu.icache.overall_hits::total 394772509 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12885 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12885 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12885 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12885 # number of overall misses +system.cpu.icache.overall_misses::total 12885 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310466999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310466999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310466999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310466999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310466999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394785394 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394785394 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394785394 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394785394 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394785394 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23521.384059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23521.384059 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23521.384059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23521.384059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23521.384059 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 562 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24095.226931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24095.226931 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24095.226931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24095.226931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24095.226931 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1110 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.466667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.375000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2811 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2811 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2811 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2811 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67903.050117 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67813.678946 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56524.486194 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56524.486194 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66228.509529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54626.678766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66296.032854 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66228.509529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308773 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273858 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308773 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39891.494186 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46367.696811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46324.148038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41147.342069 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41147.342069 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39891.494186 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45630.423744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 45597.251438 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406509 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409264 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473363 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476118 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473363 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476118 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116276173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22528768631 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22645044804 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2972753104 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2972753104 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116276173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25501521735 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25617797908 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116276173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25501521735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25617797908 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278353 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308777 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308777 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42205.507441 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55420.098032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55331.142744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44466.346127 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42205.507441 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53873.077818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53805.564814 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527785 # number of replacements -system.cpu.dcache.tagsinuse 4094.883301 # Cycle average of tags in use -system.cpu.dcache.total_refs 668274960 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531881 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 436.244695 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 304908000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.883301 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999727 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 458541726 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458541726 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733214 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 668274940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 668274940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 668274940 # number of overall hits -system.cpu.dcache.overall_hits::total 668274940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925848 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925848 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061682 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061682 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2987530 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987530 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987530 # number of overall misses -system.cpu.dcache.overall_misses::total 2987530 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59762661000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33641566357 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93404227357 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93404227357 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93404227357 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460467574 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460467574 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1527805 # number of replacements +system.cpu.dcache.tagsinuse 4094.859699 # Cycle average of tags in use +system.cpu.dcache.total_refs 668117069 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 436.135931 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 314208000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.859699 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 458383895 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 458383895 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733146 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733146 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 28 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 28 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 668117041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 668117041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 668117041 # number of overall hits +system.cpu.dcache.overall_hits::total 668117041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925777 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925777 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061750 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061750 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses +system.cpu.dcache.overall_misses::total 2987527 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64904546500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35420882879 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 44000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 100325429379 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 100325429379 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 100325429379 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 460309672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 460309672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 671262470 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 671262470 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 671262470 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 671262470 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004182 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 671104568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 671104568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 671104568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 671104568 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004451 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004451 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004451 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004451 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31031.868039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31031.868039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31687.045986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31687.045986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31264.699386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31264.699386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11600 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 365 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33703.043758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33703.043758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33360.850369 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33360.850369 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33581.430186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33581.430186 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14466 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 388 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.780822 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.283505 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95985 # number of writebacks -system.cpu.dcache.writebacks::total 95985 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455649 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455649 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455649 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460243 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531881 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531881 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531881 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35985859000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676864000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39662723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39662723000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003171 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks +system.cpu.dcache.writebacks::total 95989 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465519 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465519 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990108 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455627 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455627 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455627 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460258 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531900 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531900 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531900 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39601531500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899018500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43500550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43500550000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003172 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002282 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002282 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24643.746965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51325.609313 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25891.517030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25891.517030 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.034483 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27119.544286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54423.641160 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28396.468438 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28396.468438 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 96fe6f71c..2843a5b3f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.625047 # Number of seconds simulated -sim_ticks 625047295000 # Number of ticks simulated -final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.627778 # Number of seconds simulated +sim_ticks 627777658000 # Number of ticks simulated +final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72768 # Simulator instruction rate (inst/s) -host_op_rate 99100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32855066 # Simulator tick rate (ticks/s) -host_mem_usage 309740 # Number of bytes of host memory used -host_seconds 19024.38 # Real time elapsed on the host +host_inst_rate 102547 # Simulator instruction rate (inst/s) +host_op_rate 139655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46502403 # Simulator tick rate (ticks/s) +host_mem_usage 263380 # Number of bytes of host memory used +host_seconds 13499.90 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory -system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474974 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474966 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30398336 # Total number of bytes read from memory +system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397824 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis +system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 625047219500 # Total gap between requests +system.physmem.totGap 627777588500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474974 # Categorize read packet sizes +system.physmem.readPktSize::6 474966 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests -system.physmem.totBusLat 1899232000 # Total cycles spent in databus access -system.physmem.totBankLat 12875828000 # Total cycles spent in bank access -system.physmem.avgQLat 7035.71 # Average queueing delay per request -system.physmem.avgBankLat 27117.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38153.68 # Average memory access latency -system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests +system.physmem.totBusLat 2374030000 # Total cycles spent in databus access +system.physmem.totBankLat 15605837500 # Total cycles spent in bank access +system.physmem.avgQLat 6703.98 # Average queueing delay per request +system.physmem.avgBankLat 32867.82 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 44571.80 # Average memory access latency +system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.44 # Average write queue length over time -system.physmem.readRowHits 249146 # Number of row buffer hits during reads -system.physmem.writeRowHits 48036 # Number of row buffer hits during writes -system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes -system.physmem.avgGap 1155201.56 # Average gap between requests -system.cpu.branchPred.lookups 438808047 # Number of BP lookups -system.cpu.branchPred.condPredicted 349805436 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30625316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 249957064 # Number of BTB lookups -system.cpu.branchPred.BTBHits 227370417 # Number of BTB hits +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 143321 # Number of row buffer hits during reads +system.physmem.writeRowHits 45521 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes +system.physmem.avgGap 1160264.94 # Average gap between requests +system.cpu.branchPred.lookups 438315949 # Number of BP lookups +system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.963789 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52357585 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806128 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,238 +244,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1250094591 # number of cpu cycles simulated +system.cpu.numCycles 1255555317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued -system.cpu.iq.rate 1.950082 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued +system.cpu.iq.rate 1.941304 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12401 # number of nop insts executed -system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed -system.cpu.iew.exec_branches 322475744 # Number of branches executed -system.cpu.iew.exec_stores 423637242 # Number of stores executed -system.cpu.iew.exec_rate 1.890762 # Inst execution rate -system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347866502 # num instructions producing a value -system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value +system.cpu.iew.exec_nop 12468 # number of nop insts executed +system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed +system.cpu.iew.exec_branches 322574295 # Number of branches executed +system.cpu.iew.exec_stores 423720933 # Number of stores executed +system.cpu.iew.exec_rate 1.882449 # Inst execution rate +system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347631532 # num instructions producing a value +system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,200 +487,200 @@ system.cpu.commit.branches 299634395 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3806292582 # The number of ROB reads -system.cpu.rob.rob_writes 5746483501 # The number of ROB writes -system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3802577661 # The number of ROB reads +system.cpu.rob.rob_writes 5740389540 # The number of ROB writes +system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads -system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads -system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads +system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads +system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads +system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22468 # number of replacements -system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use -system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks. +system.cpu.icache.replacements 22740 # number of replacements +system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use +system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits -system.cpu.icache.overall_hits::total 333175666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses -system.cpu.icache.overall_misses::total 30702 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # 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number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses +system.cpu.icache.overall_misses::total 31628 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481224999 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1537223 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1561644 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24421 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1537223 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1561644 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099300 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.274601 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999304 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999304 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100663 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.307457 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.304258 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100663 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.307457 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.304258 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52210.818593 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63621.892658 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 63554.055971 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49126.643965 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49126.643965 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61547.139702 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61547.139702 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099300 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.307415 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.304161 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.384486 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.495564 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48036.988271 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48036.988271 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67561.596957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67561.596957 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -690,193 +691,193 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # 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number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2429 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96251295 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20717048717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20813300012 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43404340 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43404340 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832468177 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43064306 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43064306 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2356932012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2356932012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103136612 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086263577 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26189400189 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103136612 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086263577 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.831062 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58379.047814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58285.626676 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532939 # number of replacements -system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use -system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1533127 # number of replacements +system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use +system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # 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number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses -system.cpu.dcache.overall_misses::total 2788032 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses +system.cpu.dcache.overall_misses::total 2795405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks -system.cpu.dcache.writebacks::total 96308 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks +system.cpu.dcache.writebacks::total 96321 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 8052f41c2..2f98c15fc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043266 # Number of seconds simulated -sim_ticks 43266024500 # Number of ticks simulated -final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.042726 # Number of seconds simulated +sim_ticks 42726055500 # Number of ticks simulated +final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92573 # Simulator instruction rate (inst/s) -host_op_rate 92573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45339086 # Simulator tick rate (ticks/s) -host_mem_usage 308556 # Number of bytes of host memory used -host_seconds 954.28 # Real time elapsed on the host +host_inst_rate 156388 # Simulator instruction rate (inst/s) +host_op_rate 156388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75637274 # Simulator tick rate (ticks/s) +host_mem_usage 259292 # Number of bytes of host memory used +host_seconds 564.88 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454720 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165517 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10509863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 234326313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 244836176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10509863 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 168626725 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 168626725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10509863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 234326313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 413462901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165517 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165519 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279514 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593088 # Total number of bytes read from memory +system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593216 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593088 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10218 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10217 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10334 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10242 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43266004500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry +system.physmem.totGap 42726035000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165517 # Categorize read packet sizes +system.physmem.readPktSize::6 165519 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 113997 # categorize write packet sizes +system.physmem.writePktSize::6 114011 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 71923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see @@ -161,45 +161,45 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9309879146 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11706015146 # Sum of mem lat for all requests -system.physmem.totBusLat 662068000 # Total cycles spent in databus access -system.physmem.totBankLat 1734068000 # Total cycles spent in bank access -system.physmem.avgQLat 56247.27 # Average queueing delay per request -system.physmem.avgBankLat 10476.68 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70723.94 # Average memory access latency -system.physmem.avgRdBW 244.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 168.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 244.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 168.63 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.27 # Average read queue length over time -system.physmem.avgWrQLen 10.35 # Average write queue length over time -system.physmem.readRowHits 151965 # Number of row buffer hits during reads -system.physmem.writeRowHits 41713 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes -system.physmem.avgGap 154790.12 # Average gap between requests -system.cpu.branchPred.lookups 18742312 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits +system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests +system.physmem.totBusLat 827595000 # Total cycles spent in databus access +system.physmem.totBankLat 1765926250 # Total cycles spent in bank access +system.physmem.avgQLat 42615.22 # Average queueing delay per request +system.physmem.avgBankLat 10669.02 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58284.24 # Average memory access latency +system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.23 # Average read queue length over time +system.physmem.avgWrQLen 10.42 # Average write queue length over time +system.physmem.readRowHits 148856 # Number of row buffer hits during reads +system.physmem.writeRowHits 71620 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes +system.physmem.avgGap 152857.21 # Average gap between requests +system.cpu.branchPred.lookups 18742591 # Number of BP lookups +system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -209,18 +209,18 @@ system.cpu.dtb.read_hits 20277550 # DT system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 20367698 # DTB read accesses -system.cpu.dtb.write_hits 14728696 # DTB write hits +system.cpu.dtb.write_hits 14728779 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14735948 # DTB write accesses -system.cpu.dtb.data_hits 35006246 # DTB hits +system.cpu.dtb.write_accesses 14736031 # DTB write accesses +system.cpu.dtb.data_hits 35006329 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103646 # DTB accesses -system.cpu.itb.fetch_hits 12367278 # ITB hits -system.cpu.itb.fetch_misses 11044 # ITB misses +system.cpu.dtb.data_accesses 35103729 # DTB accesses +system.cpu.itb.fetch_hits 12368275 # ITB hits +system.cpu.itb.fetch_misses 11063 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378322 # ITB accesses +system.cpu.itb.fetch_accesses 12379338 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 86532050 # number of cpu cycles simulated +system.cpu.numCycles 85452112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126488722 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66053 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293683 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14165611 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060577 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447125 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216806 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4663931 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.863863 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777842 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060657 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77186042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 230961 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16958681 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69573369 # Number of cycles cpu stages are processed. -system.cpu.activity 80.401850 # Percentage of cycles cpu is active +system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. +system.cpu.activity 81.422683 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -273,194 +273,194 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.979527 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.979527 # CPI: Total CPI of All Threads -system.cpu.ipc 1.020901 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads +system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.020901 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33881250 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52650800 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.845432 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44079875 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42452175 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 49.059481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 43502532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029518 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.726683 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 64419596 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112454 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.554062 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40482959 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049091 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 53.216226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84282 # number of replacements -system.cpu.icache.tagsinuse 1908.908494 # Cycle average of tags in use -system.cpu.icache.total_refs 12250113 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86328 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.901967 # Average number of references to valid blocks. +system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52654819 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1822166500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1822166500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1822166500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367269 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367269 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15553.334870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15553.334870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15553.334870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15553.334870 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 309 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits +system.cpu.icache.overall_hits::total 12251160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117106 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.263158 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30828 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30828 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30828 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30828 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1279244500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1279244500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1279244500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14818.419285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14818.419285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14818.419285 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 86328 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290673 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 86328 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290673 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082302 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235707 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082302 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569427 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082302 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569427 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56005.418719 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55958.486247 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55968.116444 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109010.218426 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109010.218426 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97913.860812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56005.418719 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99793.513118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97913.860812 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -471,84 +471,84 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7105 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34626 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7105 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165517 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7105 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165517 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307703601 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1187367459 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1495071060 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235707 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569427 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43308.036735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87333.706449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85443.855960 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements -system.cpu.dcache.tagsinuse 4078.683111 # Cycle average of tags in use -system.cpu.dcache.total_refs 33755002 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use +system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.186337 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 248488000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.683111 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995772 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995772 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574731 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3942448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3942448000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 91414151500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 91414151500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 95356599500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 95356599500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 95356599500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 95356599500 # number of overall miss cycles +system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits +system.cpu.dcache.overall_hits::total 33754882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -559,38 +559,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032531 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032531 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032531 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032531 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40910.768209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40910.768209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88012.808503 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 88012.808503 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84013.662839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84013.662839 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6187652 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 65 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116324 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.193253 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 65 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks system.cpu.dcache.writebacks::total 168350 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35602 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35602 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895066 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895066 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -599,14 +599,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345 system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1934793000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14541156500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16475949500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16475949500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16475949500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -615,14 +615,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31840.582572 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101275.640758 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80628.101984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80628.101984 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ee0778484..2c49ec916 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024415 # Number of seconds simulated -sim_ticks 24414646000 # Number of ticks simulated -final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023883 # Number of seconds simulated +sim_ticks 23882696000 # Number of ticks simulated +final_tick 23882696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131517 # Simulator instruction rate (inst/s) -host_op_rate 131517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40342582 # Simulator tick rate (ticks/s) -host_mem_usage 309584 # Number of bytes of host memory used -host_seconds 605.18 # Real time elapsed on the host +host_inst_rate 224964 # Simulator instruction rate (inst/s) +host_op_rate 224964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67503934 # Simulator tick rate (ticks/s) +host_mem_usage 262380 # Number of bytes of host memory used +host_seconds 353.80 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153920 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158655 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166317 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20084993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 415894623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 435979616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20084993 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 298876338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 298876338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20084993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 415894623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 734855955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166317 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280332 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644288 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644288 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 490816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154176 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158659 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166328 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20551114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425168750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 445719863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20551114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 305536025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 305536025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20551114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425168750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 751255888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166328 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644992 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10644992 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10379 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9953 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10252 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6884 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6936 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7376 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10412 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10156 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10115 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7275 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24414612500 # Total gap between requests +system.physmem.totGap 23882663000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166317 # Categorize read packet sizes +system.physmem.readPktSize::6 166328 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 114015 # categorize write packet sizes +system.physmem.writePktSize::6 114016 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,11 +105,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 67939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,14 +138,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4949 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 9394568799 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11745778799 # Sum of mem lat for all requests -system.physmem.totBusLat 665260000 # Total cycles spent in databus access -system.physmem.totBankLat 1685950000 # Total cycles spent in bank access -system.physmem.avgQLat 56486.60 # Average queueing delay per request -system.physmem.avgBankLat 10137.09 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 70623.69 # Average memory access latency -system.physmem.avgRdBW 435.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 298.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 435.98 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 298.88 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.48 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 152275 # Number of row buffer hits during reads -system.physmem.writeRowHits 40821 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes -system.physmem.avgGap 87091.78 # Average gap between requests -system.cpu.branchPred.lookups 16536427 # Number of BP lookups -system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits +system.physmem.totQLat 7244561154 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9788827404 # Sum of mem lat for all requests +system.physmem.totBusLat 831635000 # Total cycles spent in databus access +system.physmem.totBankLat 1712631250 # Total cycles spent in bank access +system.physmem.avgQLat 43556.13 # Average queueing delay per request +system.physmem.avgBankLat 10296.77 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58852.91 # Average memory access latency +system.physmem.avgRdBW 445.72 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 305.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 445.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 305.54 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.41 # Average read queue length over time +system.physmem.avgWrQLen 10.04 # Average write queue length over time +system.physmem.readRowHits 149202 # Number of row buffer hits during reads +system.physmem.writeRowHits 70865 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.15 # Row buffer hit rate for writes +system.physmem.avgGap 85190.56 # Average gap between requests +system.cpu.branchPred.lookups 16542352 # Number of BP lookups +system.cpu.branchPred.condPredicted 10681130 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 417709 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11519084 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7344749 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.761572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40943 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403664 # DTB read hits -system.cpu.dtb.read_misses 220373 # DTB read misses -system.cpu.dtb.read_acv 50 # DTB read access violations -system.cpu.dtb.read_accesses 22624037 # DTB read accesses -system.cpu.dtb.write_hits 15711393 # DTB write hits -system.cpu.dtb.write_misses 41143 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15752536 # DTB write accesses -system.cpu.dtb.data_hits 38115057 # DTB hits -system.cpu.dtb.data_misses 261516 # DTB misses -system.cpu.dtb.data_acv 54 # DTB access violations -system.cpu.dtb.data_accesses 38376573 # DTB accesses -system.cpu.itb.fetch_hits 13911095 # ITB hits -system.cpu.itb.fetch_misses 34570 # ITB misses +system.cpu.dtb.read_hits 22396635 # DTB read hits +system.cpu.dtb.read_misses 219070 # DTB read misses +system.cpu.dtb.read_acv 53 # DTB read access violations +system.cpu.dtb.read_accesses 22615705 # DTB read accesses +system.cpu.dtb.write_hits 15704107 # DTB write hits +system.cpu.dtb.write_misses 40999 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15745106 # DTB write accesses +system.cpu.dtb.data_hits 38100742 # DTB hits +system.cpu.dtb.data_misses 260069 # DTB misses +system.cpu.dtb.data_acv 59 # DTB access violations +system.cpu.dtb.data_accesses 38360811 # DTB accesses +system.cpu.itb.fetch_hits 13916224 # ITB hits +system.cpu.itb.fetch_misses 34938 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945665 # ITB accesses +system.cpu.itb.fetch_accesses 13951162 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,238 +234,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 48829295 # number of cpu cycles simulated +system.cpu.numCycles 47765395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9328996 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19544366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2001802 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6569447 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 313140 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13911095 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206120 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.412284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.135635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15792461 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105331722 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16542352 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9334802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19546012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2000871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6407929 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 309888 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13916224 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206477 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.420490 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.137268 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24136481 55.26% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528556 3.50% 58.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1370450 3.14% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1506920 3.45% 65.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4142263 9.48% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846581 4.23% 79.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 675220 1.55% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1067886 2.44% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7406490 16.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23970685 55.08% 55.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1532413 3.52% 58.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1373284 3.16% 61.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510754 3.47% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137026 9.51% 74.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849440 4.25% 78.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 675147 1.55% 80.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069291 2.46% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7398657 17.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43680847 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.338658 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.157938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16869436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6110909 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18556945 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 793975 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1349582 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748874 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107098 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103640564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305578 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1349582 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17328003 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3849727 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18840913 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2228217 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102377631 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2729 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2099672 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61646345 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123373260 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122920505 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452755 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43516697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346325 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205189 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16865376 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5950414 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18541793 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 811002 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348112 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3746218 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106835 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103623462 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302130 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348112 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17322335 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3664232 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84922 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18847631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102361026 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 441 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2593 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2123305 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61634933 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123335826 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122884489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451337 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9099464 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5534 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4609870 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23237420 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16278692 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1191956 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452268 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90762555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5288 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88451556 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99102 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10723978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4670719 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 705 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43680847 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.024951 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.111086 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9088052 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5535 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4634659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23233430 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16268738 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1206800 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 454955 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90740192 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5270 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88424187 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96369 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10688335 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4670210 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43516697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.031960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108941 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15440168 35.35% 35.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6886071 15.76% 51.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5612203 12.85% 63.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4740584 10.85% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4695591 10.75% 85.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649897 6.07% 91.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1923598 4.40% 96.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1315990 3.01% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 416745 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15243033 35.03% 35.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6914940 15.89% 50.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5620995 12.92% 63.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4761900 10.94% 74.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4675938 10.75% 85.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2651856 6.09% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1932644 4.44% 96.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1300467 2.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 414924 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43680847 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43516697 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126167 6.80% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 781555 42.12% 48.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 947649 51.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125783 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785729 42.22% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 949726 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366923 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43857 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121501 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49355625 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43814 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121422 0.14% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121281 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 51 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22854121 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15904789 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121345 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38953 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22849621 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15893267 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88451556 # Type of FU issued -system.cpu.iq.rate 1.811444 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1855371 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221933846 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101092156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86564383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604586 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 417604 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294342 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90004545 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302382 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1470214 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88424187 # Type of FU issued +system.cpu.iq.rate 1.851219 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861238 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021049 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 221719097 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101035757 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86539045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415879 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294278 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89983556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301869 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467344 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2960782 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4826 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1665315 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2956792 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4757 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18083 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2876 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81924 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2846 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 90923 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1349582 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2855245 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 77128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100251958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 208716 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23237420 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16278692 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5288 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60129 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 488 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 198098 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161281 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87608240 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22627118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 843316 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348112 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2689881 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74163 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100228982 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217751 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23233430 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16268738 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5270 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60091 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18083 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 196583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160586 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 357169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578672 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 845515 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9484115 # number of nop insts executed -system.cpu.iew.exec_refs 38379967 # number of memory reference insts executed -system.cpu.iew.exec_branches 15086881 # Number of branches executed -system.cpu.iew.exec_stores 15752849 # Number of stores executed -system.cpu.iew.exec_rate 1.794174 # Inst execution rate -system.cpu.iew.wb_sent 87251382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86858725 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33364118 # num instructions producing a value -system.cpu.iew.wb_consumers 43780682 # num instructions consuming a value +system.cpu.iew.exec_nop 9483520 # number of nop insts executed +system.cpu.iew.exec_refs 38364354 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084185 # Number of branches executed +system.cpu.iew.exec_stores 15745471 # Number of stores executed +system.cpu.iew.exec_rate 1.833517 # Inst execution rate +system.cpu.iew.wb_sent 87223381 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86833323 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33358386 # num instructions producing a value +system.cpu.iew.wb_consumers 43765374 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.778824 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762074 # average fanout of values written-back +system.cpu.iew.wb_rate 1.817913 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762210 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8914358 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 313984 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42331265 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.086889 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804714 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 313123 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42168585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.094940 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.806680 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19478152 46.01% 46.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7019307 16.58% 62.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3402930 8.04% 70.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2062880 4.87% 75.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2059752 4.87% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1161194 2.74% 83.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1088223 2.57% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718067 1.70% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5340760 12.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19301880 45.77% 45.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7026183 16.66% 62.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3423669 8.12% 70.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2056444 4.88% 75.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2047690 4.86% 80.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1162920 2.76% 83.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1093248 2.59% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719437 1.71% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337114 12.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42331265 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42168585 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,192 +476,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5340760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132928193 # The number of ROB reads -system.cpu.rob.rob_writes 195862433 # The number of ROB writes -system.cpu.timesIdled 69428 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5148448 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132743851 # The number of ROB reads +system.cpu.rob.rob_writes 195810249 # The number of ROB writes +system.cpu.timesIdled 70469 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4248698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.613497 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.613497 # CPI: Total CPI of All Threads -system.cpu.ipc 1.630000 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.630000 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115949669 # number of integer regfile reads -system.cpu.int_regfile_writes 57525330 # number of integer regfile writes -system.cpu.fp_regfile_reads 249508 # number of floating regfile reads -system.cpu.fp_regfile_writes 240213 # number of floating regfile writes -system.cpu.misc_regfile_reads 38023 # number of misc regfile reads +system.cpu.cpi 0.600130 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.600130 # CPI: Total CPI of All Threads +system.cpu.ipc 1.666306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.666306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115907691 # number of integer regfile reads +system.cpu.int_regfile_writes 57507162 # number of integer regfile writes +system.cpu.fp_regfile_reads 249392 # number of floating regfile reads +system.cpu.fp_regfile_writes 240337 # number of floating regfile writes +system.cpu.misc_regfile_reads 38035 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91621 # number of replacements -system.cpu.icache.tagsinuse 1930.572235 # Cycle average of tags in use -system.cpu.icache.total_refs 13805106 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.381802 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19945764000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.572235 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942662 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942662 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13805106 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13805106 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13805106 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13805106 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13805106 # number of overall hits -system.cpu.icache.overall_hits::total 13805106 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105989 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105989 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105989 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105989 # number of overall misses -system.cpu.icache.overall_misses::total 105989 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1780097998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1780097998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1780097998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1780097998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1780097998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13911095 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13911095 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13911095 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13911095 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13911095 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007619 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007619 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007619 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007619 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007619 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16795.120229 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16795.120229 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16795.120229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16795.120229 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 364 # number of cycles access was blocked +system.cpu.icache.replacements 91216 # number of replacements +system.cpu.icache.tagsinuse 1928.922459 # Cycle average of tags in use +system.cpu.icache.total_refs 13810559 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93264 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 148.080277 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19641578000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1928.922459 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941857 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941857 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13810559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13810559 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13810559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13810559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13810559 # number of overall hits +system.cpu.icache.overall_hits::total 13810559 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105664 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105664 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105664 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105664 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105664 # number of overall misses +system.cpu.icache.overall_misses::total 105664 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863781999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1863781999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1863781999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1863781999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1863781999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13916223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13916223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13916223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13916223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13916223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007593 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007593 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007593 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007593 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007593 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17638.760590 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17638.760590 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17638.760590 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17638.760590 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1009 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.071429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12319 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12319 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12319 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12319 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12319 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93670 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93670 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93670 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93670 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93670 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1391219000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1391219000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1391219000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006733 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006733 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006733 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14852.343333 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14852.343333 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14852.343333 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12399 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12399 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12399 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12399 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93265 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93265 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93265 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93265 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93265 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93265 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1450659000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1450659000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1450659000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1450659000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1450659000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1450659000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15554.162869 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15554.162869 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15554.162869 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15554.162869 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 132407 # number of replacements -system.cpu.l2cache.tagsinuse 30853.775951 # Cycle average of tags in use -system.cpu.l2cache.total_refs 160055 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 164479 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.973103 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132416 # number of replacements +system.cpu.l2cache.tagsinuse 30823.572935 # Cycle average of tags in use +system.cpu.l2cache.total_refs 159534 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164488 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.969882 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26652.913522 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2131.265496 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2069.596933 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.065041 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.063159 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941583 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 86007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34313 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120320 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168957 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52775.726597 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74685.543083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73675.206386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201507 # number of replacements -system.cpu.dcache.tagsinuse 4077.368240 # Cycle average of tags in use -system.cpu.dcache.total_refs 34205521 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205603 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.366838 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 173993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.368240 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995451 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20631452 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20631452 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574012 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34205464 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34205464 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34205464 # number of overall hits -system.cpu.dcache.overall_hits::total 34205464 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267045 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267045 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039365 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306410 # number of overall misses -system.cpu.dcache.overall_misses::total 1306410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12450634000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12450634000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 93436551833 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105887185833 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105887185833 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105887185833 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20898497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20898497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201431 # number of replacements +system.cpu.dcache.tagsinuse 4076.502318 # Cycle average of tags in use +system.cpu.dcache.total_refs 34195386 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205527 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.379045 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178801000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.502318 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995240 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20621336 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20621336 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13573997 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13573997 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34195333 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34195333 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34195333 # number of overall hits +system.cpu.dcache.overall_hits::total 34195333 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 266907 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 266907 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039380 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039380 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306287 # number of overall misses +system.cpu.dcache.overall_misses::total 1306287 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12007604500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12007604500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79088080451 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91095684951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91095684951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91095684951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20888243 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20888243 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35511874 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35511874 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35511874 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35511874 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35501620 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35501620 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35501620 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35501620 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012778 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012778 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071124 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036788 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036788 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036788 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036788 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46623.730083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46623.730083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89897.727779 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89897.727779 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81052.032542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81052.032542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5486905 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071125 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036795 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036795 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036795 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036795 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44987.971466 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44987.971466 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76091.593499 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76091.593499 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69736.348100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69736.348100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4377310 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112436 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112282 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.800251 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.984966 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168957 # number of writebacks -system.cpu.dcache.writebacks::total 168957 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895935 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895935 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62173 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62173 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143430 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143430 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205603 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205603 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205603 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2029919500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14640535990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16670455490 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16670455490 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32649.534364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102074.433452 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81080.798870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81080.798870 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168913 # number of writebacks +system.cpu.dcache.writebacks::total 168913 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204795 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204795 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895965 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895965 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100760 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100760 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62112 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143415 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143415 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205527 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205527 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205527 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205527 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2016329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12443477492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14459806992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14459806992 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32462.801069 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86765.523076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70354.780598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70354.780598 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 57be29288..bdf692e24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026275 # Number of seconds simulated -sim_ticks 26275145500 # Number of ticks simulated -final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025578 # Number of seconds simulated +sim_ticks 25577832000 # Number of ticks simulated +final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87619 # Simulator instruction rate (inst/s) -host_op_rate 124343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32467681 # Simulator tick rate (ticks/s) -host_mem_usage 316828 # Number of bytes of host memory used -host_seconds 809.27 # Real time elapsed on the host +host_inst_rate 153227 # Simulator instruction rate (inst/s) +host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55271946 # Simulator tick rate (ticks/s) +host_mem_usage 270340 # Number of bytes of host memory used +host_seconds 462.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128759 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128759 # Total number of read requests seen -system.physmem.writeReqs 83947 # Total number of write requests seen -system.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240576 # Total number of bytes read from memory -system.physmem.bytesWritten 5372608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128779 # Total number of read requests seen +system.physmem.writeReqs 83944 # Total number of write requests seen +system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241856 # Total number of bytes read from memory +system.physmem.bytesWritten 5372416 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 323 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis +system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26275013500 # Total gap between requests +system.physmem.totGap 25577735000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128759 # Categorize read packet sizes +system.physmem.readPktSize::6 128779 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83947 # categorize write packet sizes +system.physmem.writePktSize::6 83944 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 323 # categorize neither packet sizes +system.physmem.neitherpktsize::6 312 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -138,11 +138,11 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -155,52 +155,52 @@ system.physmem.wrQLenPdf::13 3650 # Wh system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4891352059 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests -system.physmem.totBusLat 515028000 # Total cycles spent in databus access -system.physmem.totBankLat 1370824000 # Total cycles spent in bank access -system.physmem.avgQLat 37989.02 # Average queueing delay per request -system.physmem.avgBankLat 10646.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52635.62 # Average memory access latency -system.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.26 # Average read queue length over time -system.physmem.avgWrQLen 9.34 # Average write queue length over time -system.physmem.readRowHits 118922 # Number of row buffer hits during reads -system.physmem.writeRowHits 27176 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes -system.physmem.avgGap 123527.37 # Average gap between requests -system.cpu.branchPred.lookups 16626972 # Number of BP lookups -system.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7773827 # Number of BTB hits +system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totBusLat 643885000 # Total cycles spent in databus access +system.physmem.totBankLat 1400135000 # Total cycles spent in bank access +system.physmem.avgQLat 24884.99 # Average queueing delay per request +system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 4.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.21 # Average read queue length over time +system.physmem.avgWrQLen 9.73 # Average write queue length over time +system.physmem.readRowHits 116758 # Number of row buffer hits during reads +system.physmem.writeRowHits 52879 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes +system.physmem.avgGap 120239.63 # Average gap between requests +system.cpu.branchPred.lookups 16629564 # Number of BP lookups +system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +244,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 52550292 # number of cpu cycles simulated +system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19476912 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19115469 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20502 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -399,84 +399,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107269202 # Type of FU issued -system.cpu.iq.rate 2.041267 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued +system.cpu.iq.rate 2.096836 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9757 # number of nop insts executed -system.cpu.iew.exec_refs 49948126 # number of memory reference insts executed -system.cpu.iew.exec_branches 14604066 # Number of branches executed -system.cpu.iew.exec_stores 21346027 # Number of stores executed -system.cpu.iew.exec_rate 2.021647 # Inst execution rate -system.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105581404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53258894 # num instructions producing a value -system.cpu.iew.wb_consumers 103486689 # num instructions consuming a value +system.cpu.iew.exec_nop 9761 # number of nop insts executed +system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602542 # Number of branches executed +system.cpu.iew.exec_stores 21344564 # Number of stores executed +system.cpu.iew.exec_rate 2.076700 # Inst execution rate +system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53282087 # num instructions producing a value +system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.009150 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back +system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,204 +487,204 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149922829 # The number of ROB reads -system.cpu.rob.rob_writes 224870236 # The number of ROB writes -system.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_writes 224865260 # The number of ROB writes +system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.741109 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads -system.cpu.ipc 1.349329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511669135 # number of integer regfile reads -system.cpu.int_regfile_writes 103349973 # number of integer regfile writes -system.cpu.fp_regfile_reads 690 # number of floating regfile reads -system.cpu.fp_regfile_writes 602 # number of floating regfile writes -system.cpu.misc_regfile_reads 49186281 # number of misc regfile reads +system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511661177 # number of integer regfile reads +system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.fp_regfile_reads 804 # number of floating regfile reads +system.cpu.fp_regfile_writes 688 # number of floating regfile writes +system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 29504 # number of replacements -system.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use -system.cpu.icache.total_refs 11653533 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks. +system.cpu.icache.replacements 28586 # number of replacements +system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits -system.cpu.icache.overall_hits::total 11653539 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses -system.cpu.icache.overall_misses::total 35502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits +system.cpu.icache.overall_hits::total 11645446 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses +system.cpu.icache.overall_misses::total 34686 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31864 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 575585499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 575585499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 575585499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 575585499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 575585499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 575585499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002726 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002726 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002726 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18063.818071 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18063.818071 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95629 # number of replacements -system.cpu.l2cache.tagsinuse 30144.051156 # Cycle average of tags in use -system.cpu.l2cache.total_refs 89024 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126742 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60157.185571 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10046.024845 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks +system.cpu.l2cache.writebacks::total 83944 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158352 # number of replacements -system.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use -system.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26058145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26058145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18265070 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18265070 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15998 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15998 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158328 # number of replacements +system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use +system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits -system.cpu.dcache.overall_hits::total 44323215 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124984 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124984 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1584831 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1584831 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1709815 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1709815 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1709815 # number of overall misses -system.cpu.dcache.overall_misses::total 1709815 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4634379500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4634379500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 120528782979 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 120528782979 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 125163162479 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 125163162479 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 125163162479 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 125163162479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26183129 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26183129 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits +system.cpu.dcache.overall_hits::total 44337922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses +system.cpu.dcache.overall_misses::total 1707147 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129085 # number of writebacks -system.cpu.dcache.writebacks::total 129085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks +system.cpu.dcache.writebacks::total 129109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 2c8c2e903..bbfef95ab 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.985090 # Number of seconds simulated -sim_ticks 985089830500 # Number of ticks simulated -final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.993559 # Number of seconds simulated +sim_ticks 993559170500 # Number of ticks simulated +final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87940 # Simulator instruction rate (inst/s) -host_op_rate 87940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47603973 # Simulator tick rate (ticks/s) -host_mem_usage 516412 # Number of bytes of host memory used -host_seconds 20693.44 # Real time elapsed on the host +host_inst_rate 148425 # Simulator instruction rate (inst/s) +host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81036604 # Simulator tick rate (ticks/s) +host_mem_usage 464668 # Number of bytes of host memory used +host_seconds 12260.62 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959687 # Total number of read requests seen -system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419968 # Total number of bytes read from memory -system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() +system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 126177745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 126233078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 65578089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 65578089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 126177745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959688 # Total number of read requests seen +system.physmem.writeReqs 1018058 # Total number of write requests seen +system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420032 # Total number of bytes read from memory +system.physmem.bytesWritten 65155712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63395 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65307 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122179 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 121801 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 121647 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 123761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121195 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 121884 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121113 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 123789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 985089778500 # Total gap between requests +system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959687 # Categorize read packet sizes +system.physmem.readPktSize::6 1959688 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018055 # categorize write packet sizes +system.physmem.writePktSize::6 1018171 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44262 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests -system.physmem.totBusLat 7836420000 # Total cycles spent in databus access -system.physmem.totBankLat 57752478000 # Total cycles spent in bank access -system.physmem.avgQLat 10025.42 # Average queueing delay per request -system.physmem.avgBankLat 29479.01 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43504.43 # Average memory access latency -system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.21 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.09 # Average read queue length over time -system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834572 # Number of row buffer hits during reads -system.physmem.writeRowHits 194113 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 330817.71 # Average gap between requests -system.cpu.branchPred.lookups 326556831 # Number of BP lookups -system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits +system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totBusLat 9795530000 # Total cycles spent in databus access +system.physmem.totBankLat 58644685000 # Total cycles spent in bank access +system.physmem.avgQLat 18298.46 # Average queueing delay per request +system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 65.58 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 10.46 # Average write queue length over time +system.physmem.readRowHits 770935 # Number of row buffer hits during reads +system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 333661.47 # Average gap between requests +system.cpu.branchPred.lookups 326540496 # Number of BP lookups +system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.613527 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784566 # DTB read hits +system.cpu.dtb.read_hits 444796007 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681644 # DTB read accesses -system.cpu.dtb.write_hits 160833172 # DTB write hits +system.cpu.dtb.read_accesses 449693085 # DTB read accesses +system.cpu.dtb.write_hits 160833351 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534476 # DTB write accesses -system.cpu.dtb.data_hits 605617738 # DTB hits +system.cpu.dtb.write_accesses 162534655 # DTB write accesses +system.cpu.dtb.data_hits 605629358 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612216120 # DTB accesses -system.cpu.itb.fetch_hits 231916745 # ITB hits +system.cpu.dtb.data_accesses 612227740 # DTB accesses +system.cpu.itb.fetch_hits 232025962 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231916767 # ITB accesses +system.cpu.itb.fetch_accesses 232025984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,34 +234,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1970179662 # number of cpu cycles simulated +system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617888959 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83550128 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.175613 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139371391 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. -system.cpu.activity 79.773501 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100703 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -273,191 +273,191 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.091955 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads -system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.091955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use -system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use +system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits -system.cpu.icache.overall_hits::total 231915637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses -system.cpu.icache.overall_misses::total 1108 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits +system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses +system.cpu.icache.overall_misses::total 1109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107378 # number of replacements -system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use -system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593539212 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593539212 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593539212 # number of overall hits -system.cpu.dcache.overall_hits::total 593539212 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4458042 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4458042 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11784953 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11784953 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11784953 # number of overall misses -system.cpu.dcache.overall_misses::total 11784953 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 160323624500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 160323624500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles +system.cpu.dcache.replacements 9107372 # number of replacements +system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use +system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits +system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326905 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,54 +556,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks -system.cpu.dcache.writebacks::total 3693296 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks +system.cpu.dcache.writebacks::total 3693293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889185 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +612,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index c63a4e0f8..db2985766 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.655920 # Number of seconds simulated -sim_ticks 655919824500 # Number of ticks simulated -final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665563 # Number of seconds simulated +sim_ticks 665562897500 # Number of ticks simulated +final_tick 665562897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111017 # Simulator instruction rate (inst/s) -host_op_rate 111017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41944886 # Simulator tick rate (ticks/s) -host_mem_usage 517560 # Number of bytes of host memory used -host_seconds 15637.66 # Real time elapsed on the host +host_inst_rate 181531 # Simulator instruction rate (inst/s) +host_op_rate 181531 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69595242 # Simulator tick rate (ticks/s) +host_mem_usage 467736 # Number of bytes of host memory used +host_seconds 9563.34 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796416 # Number of bytes read from this memory -system.physmem.bytes_read::total 125857920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262592 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965569 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966530 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019728 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019728 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 191786269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 191880037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 99497819 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 99497819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 191786269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291377856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966530 # Total number of read requests seen -system.physmem.writeReqs 1019728 # Total number of write requests seen -system.physmem.cpureqs 2986258 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125857920 # Total number of bytes read from memory -system.physmem.bytesWritten 65262592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125857920 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 571 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125801472 # Number of bytes read from this memory +system.physmem.bytes_read::total 125863104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65262912 # Number of bytes written to this memory +system.physmem.bytes_written::total 65262912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019733 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 189015152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189107753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98056716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98056716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 189015152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287164469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966611 # Total number of read requests seen +system.physmem.writeReqs 1019733 # Total number of write requests seen +system.physmem.cpureqs 2988993 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125863104 # Total number of bytes read from memory +system.physmem.bytesWritten 65262912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125863104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65262912 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 562 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 123004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 123239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 121669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 124908 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 123890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 123027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 120849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 122324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 124974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123664 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63503 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 62809 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 62611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 64078 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 63409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64056 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 65441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64564 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 122665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 121417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124451 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63122 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63474 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63840 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63360 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64652 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 63751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64373 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 655919756000 # Total gap between requests +system.physmem.numWrRetry 2649 # Number of times wr buffer was full causing retry +system.physmem.totGap 665562829000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966530 # Categorize read packet sizes +system.physmem.readPktSize::6 1966611 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1019728 # categorize write packet sizes +system.physmem.writePktSize::6 1022382 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1634092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1625792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 43349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44320 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see @@ -161,66 +161,66 @@ system.physmem.wrQLenPdf::19 44336 # Wh system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 20705208242 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85868216242 # Sum of mem lat for all requests -system.physmem.totBusLat 7863836000 # Total cycles spent in databus access -system.physmem.totBankLat 57299172000 # Total cycles spent in bank access -system.physmem.avgQLat 10531.86 # Average queueing delay per request -system.physmem.avgBankLat 29145.66 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43677.52 # Average memory access latency -system.physmem.avgRdBW 191.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 99.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 191.88 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 99.50 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 10.55 # Average write queue length over time -system.physmem.readRowHits 840760 # Number of row buffer hits during reads -system.physmem.writeRowHits 193886 # Number of row buffer hits during writes -system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes -system.physmem.avgGap 219646.04 # Average gap between requests -system.cpu.branchPred.lookups 381024003 # Number of BP lookups -system.cpu.branchPred.condPredicted 296029232 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16079219 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 261934224 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259237388 # Number of BTB hits +system.physmem.totQLat 34363983237 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102498683237 # Sum of mem lat for all requests +system.physmem.totBusLat 9830245000 # Total cycles spent in databus access +system.physmem.totBankLat 58304455000 # Total cycles spent in bank access +system.physmem.avgQLat 17478.70 # Average queueing delay per request +system.physmem.avgBankLat 29655.65 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 52134.35 # Average memory access latency +system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 10.79 # Average write queue length over time +system.physmem.readRowHits 776053 # Number of row buffer hits during reads +system.physmem.writeRowHits 286138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes +system.physmem.avgGap 222868.77 # Average gap between requests +system.cpu.branchPred.lookups 381322658 # Number of BP lookups +system.cpu.branchPred.condPredicted 296346711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16069927 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262182430 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259521497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.970415 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24703724 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3041 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.985083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24701305 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3076 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613741491 # DTB read hits -system.cpu.dtb.read_misses 11247891 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 624989382 # DTB read accesses -system.cpu.dtb.write_hits 212247245 # DTB write hits -system.cpu.dtb.write_misses 7144332 # DTB write misses +system.cpu.dtb.read_hits 613798645 # DTB read hits +system.cpu.dtb.read_misses 11251599 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 625050244 # DTB read accesses +system.cpu.dtb.write_hits 212271089 # DTB write hits +system.cpu.dtb.write_misses 7143652 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219391577 # DTB write accesses -system.cpu.dtb.data_hits 825988736 # DTB hits -system.cpu.dtb.data_misses 18392223 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 844380959 # DTB accesses -system.cpu.itb.fetch_hits 390708850 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.write_accesses 219414741 # DTB write accesses +system.cpu.dtb.data_hits 826069734 # DTB hits +system.cpu.dtb.data_misses 18395251 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 844464985 # DTB accesses +system.cpu.itb.fetch_hits 390709896 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390708888 # ITB accesses +system.cpu.itb.fetch_accesses 390709940 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -234,139 +234,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1311839650 # number of cpu cycles simulated +system.cpu.numCycles 1331125796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283941112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 573880213 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140086808 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 165153102 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390708850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8061624 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.510971 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402151320 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159313188 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381322658 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284222802 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574163176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140279243 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173671179 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390709896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8056983 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152796 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 683625224 54.36% 54.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42619367 3.39% 57.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21744894 1.73% 59.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39684878 3.16% 62.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129121337 10.27% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61516601 4.89% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38545793 3.07% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28125558 2.24% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212521785 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692293872 54.66% 54.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42630313 3.37% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21744461 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39673370 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129246893 10.21% 73.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61513639 4.86% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38552077 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28113770 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212688653 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1257505437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.290450 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.406971 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433733980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 146719588 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542274905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18455051 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116321913 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58305735 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 954 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3085307728 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2035 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116321913 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456557347 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 93252503 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5104 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535232007 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56136563 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3003562340 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 560555 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1735251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50037437 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2245657329 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3895152131 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3893909248 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1242883 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266457048 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286466 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433835858 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155176701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542390430 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18584911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116469148 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58290582 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3086789571 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2029 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116469148 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456704578 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101399871 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535436988 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56439421 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3004825157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566473 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1727265 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50367655 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246602827 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897066108 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3895827965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1238143 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 869454366 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 190 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120669951 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679225578 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255273844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68130212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37368209 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2722510883 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 144 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508555980 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3078936 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 977267031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 413974741 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 115 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1257505437 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.994867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973352 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 870399864 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 161 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121306422 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679329311 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255341435 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67772546 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36892101 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723405673 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508908939 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3097394 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978157995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 414914582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266457048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981045 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.973109 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 417762073 33.22% 33.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201459942 16.02% 49.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185268981 14.73% 63.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153261704 12.19% 76.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133079768 10.58% 86.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81048988 6.45% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65262511 5.19% 98.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15257874 1.21% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5103596 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426262331 33.66% 33.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201879469 15.94% 49.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185440300 14.64% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153069981 12.09% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133127020 10.51% 86.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81075751 6.40% 93.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65263497 5.15% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15238482 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5100217 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1257505437 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266457048 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2150864 11.67% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11870466 64.42% 76.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4405017 23.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2147356 11.64% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11882629 64.43% 76.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4412064 23.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643219876 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643457358 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 108 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 253 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 157 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 38 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -388,84 +388,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641326950 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224008572 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641426814 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224024134 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508555980 # Type of FU issued -system.cpu.iq.rate 1.912243 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18426347 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6294223850 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3698666551 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412312770 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898830 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217307 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851008 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526043830 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938497 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62613731 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508908939 # Type of FU issued +system.cpu.iq.rate 1.884802 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18442049 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6303917077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700456251 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412530118 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897292 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1213669 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850482 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526413076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937912 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62601543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234629915 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264851 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107543 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94545342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234733648 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263681 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 107887 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94612933 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 100 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1452143 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 149 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1508556 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116321913 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 41870148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1143259 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2864507060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8845706 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679225578 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255273844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 144 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 295805 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17199 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107543 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10354551 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8556122 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18910673 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461271813 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 624989902 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47284167 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116469148 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45249808 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153798 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865411802 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8865893 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679329311 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255341435 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17062 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 107887 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10351897 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8549059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18900956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461552831 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625050873 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47356108 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141996033 # number of nop insts executed -system.cpu.iew.exec_refs 844381512 # number of memory reference insts executed -system.cpu.iew.exec_branches 300766985 # Number of branches executed -system.cpu.iew.exec_stores 219391610 # Number of stores executed -system.cpu.iew.exec_rate 1.876199 # Inst execution rate -system.cpu.iew.wb_sent 2441119325 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413163778 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388569148 # num instructions producing a value -system.cpu.iew.wb_consumers 1764314853 # num instructions consuming a value +system.cpu.iew.exec_nop 142006007 # number of nop insts executed +system.cpu.iew.exec_refs 844465652 # number of memory reference insts executed +system.cpu.iew.exec_branches 300780520 # Number of branches executed +system.cpu.iew.exec_stores 219414779 # Number of stores executed +system.cpu.iew.exec_rate 1.849226 # Inst execution rate +system.cpu.iew.wb_sent 2441340597 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413380600 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388547079 # num instructions producing a value +system.cpu.iew.wb_consumers 1764258867 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.839526 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787030 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813037 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787043 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 823556826 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824496541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16078403 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1141183524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.594643 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.519930 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16069169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1149987900 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582434 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 628040121 55.03% 55.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174132211 15.26% 70.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86354537 7.57% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53988637 4.73% 82.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34269513 3.00% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24750272 2.17% 87.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22050678 1.93% 89.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22940990 2.01% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94656565 8.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636582703 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174528815 15.18% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86154838 7.49% 78.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53696009 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34510870 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25214106 2.19% 87.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21871895 1.90% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22921084 1.99% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94507580 8.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1141183524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1149987900 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -476,189 +476,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94656565 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94507580 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3604084711 # The number of ROB reads -system.cpu.rob.rob_writes 5403096067 # The number of ROB writes -system.cpu.timesIdled 804666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 54334213 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3613977787 # The number of ROB reads +system.cpu.rob.rob_writes 5405122718 # The number of ROB writes +system.cpu.timesIdled 818240 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64668748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.755649 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755649 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323366 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323366 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3316903206 # number of integer regfile reads -system.cpu.int_regfile_writes 1931453212 # number of integer regfile writes -system.cpu.fp_regfile_reads 30791 # number of floating regfile reads -system.cpu.fp_regfile_writes 509 # number of floating regfile writes +system.cpu.cpi 0.766758 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766758 # CPI: Total CPI of All Threads +system.cpu.ipc 1.304192 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.304192 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317304663 # number of integer regfile reads +system.cpu.int_regfile_writes 1931628776 # number of integer regfile writes +system.cpu.fp_regfile_reads 30090 # number of floating regfile reads +system.cpu.fp_regfile_writes 557 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 768.875728 # Cycle average of tags in use -system.cpu.icache.total_refs 390707378 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 406563.348595 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.264197 # Cycle average of tags in use +system.cpu.icache.total_refs 390708412 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 963 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 405720.053998 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 768.875728 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375428 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375428 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390707378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390707378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390707378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390707378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390707378 # number of overall hits -system.cpu.icache.overall_hits::total 390707378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1472 # number of overall misses -system.cpu.icache.overall_misses::total 1472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 78332000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 78332000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 78332000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 78332000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 78332000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390708850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390708850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390708850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390708850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390708850 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.264197 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377082 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377082 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390708412 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390708412 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390708412 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390708412 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390708412 # number of overall hits +system.cpu.icache.overall_hits::total 390708412 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses +system.cpu.icache.overall_misses::total 1482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 83554999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 83554999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 83554999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 83554999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 83554999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 83554999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390709894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390709894 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390709894 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390709894 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390709894 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390709894 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # 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number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019728 # number of writebacks -system.cpu.l2cache.writebacks::total 1019728 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 961 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190397 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191358 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775172 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775172 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1965569 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1966530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1965569 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1966530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43023532 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 65297790926 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65340814458 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 42150717127 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 42150717127 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43023532 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107448508053 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 107491531585 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43023532 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107448508053 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 107491531585 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1019733 # number of writebacks +system.cpu.l2cache.writebacks::total 1019733 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1191502 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775109 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 775109 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1965648 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1966611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1965648 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1966611 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46150301 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 75292068672 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 75338218973 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48421097021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48421097021 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46150301 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 123713165693 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123759315994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46150301 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 123713165693 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123759315994 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163144 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163255 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411546 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163270 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411509 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214193 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214197 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214193 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44769.544225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54853.793252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54845.658868 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54375.954146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54375.954146 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44769.544225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54665.345278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54660.509418 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214115 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214197 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47923.469367 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.001037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63229.620238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62470.048756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62470.048756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47923.469367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62937.599048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62930.247006 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176047 # number of replacements -system.cpu.dcache.tagsinuse 4087.418525 # Cycle average of tags in use -system.cpu.dcache.total_refs 694335392 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.634485 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5062814000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.418525 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997905 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538685115 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538685115 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155650275 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155650275 # number of WriteReq hits +system.cpu.dcache.replacements 9176263 # number of replacements +system.cpu.dcache.tagsinuse 4087.522413 # Cycle average of tags in use +system.cpu.dcache.total_refs 694338200 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180359 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.633012 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.522413 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538691860 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538691860 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155646338 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155646338 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694335390 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694335390 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694335390 # number of overall hits -system.cpu.dcache.overall_hits::total 694335390 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11273608 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11273608 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5078227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5078227 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694338198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694338198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694338198 # number of overall hits +system.cpu.dcache.overall_hits::total 694338198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11282428 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11282428 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5082164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5082164 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16351835 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16351835 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16351835 # number of overall misses -system.cpu.dcache.overall_misses::total 16351835 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 280031703000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 217034506033 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 497066209033 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 497066209033 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 497066209033 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549958723 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549958723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16364592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16364592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16364592 # number of overall misses +system.cpu.dcache.overall_misses::total 16364592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 295012100000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 224191521595 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 431500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 519203621595 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 519203621595 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 519203621595 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549974288 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549974288 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710687225 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710687225 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710687225 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710687225 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020499 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031595 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031595 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710702790 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710702790 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710702790 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710702790 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023008 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023008 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023008 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023008 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24839.581348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24839.581348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42738.244280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42738.244280 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30398.191337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30398.191337 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10428893 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5642690 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 733632 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26147.926670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26147.926670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44113.397678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44113.397678 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 431500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 431500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31727.257337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31727.257337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12329196 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5816488 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735313 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.215428 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 86.632020 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.767276 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.300335 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724933 # number of writebacks -system.cpu.dcache.writebacks::total 3724933 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3977017 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3194676 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7171693 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7171693 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7171693 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883551 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3725054 # number of writebacks +system.cpu.dcache.writebacks::total 3725054 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3985636 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198598 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7184234 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7184234 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7184234 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883566 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883566 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 149546401000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65349746897 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 46500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 214896147897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214896147897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 214896147897 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180358 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180358 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180358 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159255490500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71503545346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 429500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230759035846 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230759035846 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230759035846 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses @@ -831,16 +831,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20495.379418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34694.970774 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 46500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23408.804341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23408.804341 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.411839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37961.794461 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 429500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25136.169618 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25136.169618 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index fe1996e1b..fe58c49f1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.506354 # Number of seconds simulated -sim_ticks 506353996500 # Number of ticks simulated -final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386177000 # Number of ticks simulated +final_tick 517386177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105319 # Simulator instruction rate (inst/s) -host_op_rate 117491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34526611 # Simulator tick rate (ticks/s) -host_mem_usage 552892 # Number of bytes of host memory used -host_seconds 14665.62 # Real time elapsed on the host +host_inst_rate 165493 # Simulator instruction rate (inst/s) +host_op_rate 184620 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55435711 # Simulator tick rate (ticks/s) +host_mem_usage 502788 # Number of bytes of host memory used +host_seconds 9333.08 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory -system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143728256 # Number of bytes read from this memory +system.physmem.bytes_read::total 143776256 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory -system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 70436224 # Number of bytes written to this memory +system.physmem.bytes_written::total 70436224 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2247186 # Total number of read requests seen -system.physmem.writeReqs 1100812 # Total number of write requests seen -system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143819904 # Total number of bytes read from memory -system.physmem.bytesWritten 70451968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 2245754 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246504 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100566 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100566 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277796861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277889635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92774 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136138589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136138589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277796861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414028224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246504 # Total number of read requests seen +system.physmem.writeReqs 1100566 # Total number of write requests seen +system.physmem.cpureqs 3350665 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143776256 # Total number of bytes read from memory +system.physmem.bytesWritten 70436224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143776256 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70436224 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 651 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 139999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138551 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136478 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139234 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141757 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69121 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68349 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69052 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 67029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68911 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 506353933500 # Total gap between requests +system.physmem.numWrRetry 3595 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386097500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2247186 # Categorize read packet sizes +system.physmem.readPktSize::6 2246504 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1100812 # categorize write packet sizes +system.physmem.writePktSize::6 1104161 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,12 +105,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1563469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68688 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,69 +138,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests -system.physmem.totBusLat 8986056000 # Total cycles spent in databus access -system.physmem.totBankLat 66751888000 # Total cycles spent in bank access -system.physmem.avgQLat 12022.89 # Average queueing delay per request -system.physmem.avgBankLat 29713.54 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45736.44 # Average memory access latency -system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 914505 # Number of row buffer hits during reads -system.physmem.writeRowHits 189005 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes -system.physmem.avgGap 151240.81 # Average gap between requests -system.cpu.branchPred.lookups 301930111 # Number of BP lookups -system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits +system.physmem.totQLat 51687050307 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131176334057 # Sum of mem lat for all requests +system.physmem.totBusLat 11229265000 # Total cycles spent in databus access +system.physmem.totBankLat 68260018750 # Total cycles spent in bank access +system.physmem.avgQLat 23014.44 # Average queueing delay per request +system.physmem.avgBankLat 30393.81 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 58408.25 # Average memory access latency +system.physmem.avgRdBW 277.89 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 10.38 # Average write queue length over time +system.physmem.readRowHits 827421 # Number of row buffer hits during reads +system.physmem.writeRowHits 271011 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.62 # Row buffer hit rate for writes +system.physmem.avgGap 154578.81 # Average gap between requests +system.cpu.branchPred.lookups 303247532 # Number of BP lookups +system.cpu.branchPred.condPredicted 249450034 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218023 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 175041543 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161435617 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.227030 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17558020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 197 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,237 +244,238 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1012707994 # number of cpu cycles simulated +system.cpu.numCycles 1034772355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed -system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298171037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186159989 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303247532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 178993637 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435067157 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87822274 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155469980 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 663 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288529454 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5728473 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523348 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213310 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523521931 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25504837 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086427 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48350867 5.04% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43002654 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46446539 4.85% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38408277 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18709630 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175557852 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958589014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112697 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329732299 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133726687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405163333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20087198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69879497 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46055159 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 678 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2366957956 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2458 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69879497 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353264569 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63487571 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18775 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400193247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71745355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304463172 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133379 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5038858 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58609164 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 17 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279851599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642208168 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642204755 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3413 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573531669 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 681 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 678 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158828994 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624462299 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220966139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86157140 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71007424 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201342631 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018151759 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3999657 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473702297 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125076843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 544 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958589014 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906417 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277560944 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151408943 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161184316 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119741050 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124054843 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850392 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38407609 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9813288 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2567629 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958589014 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872793 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5710 0.02% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18283969 76.42% 80.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4762893 19.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236667909 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925774 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 51 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587469094 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193088896 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued -system.cpu.iq.rate 1.990712 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018151759 # Type of FU issued +system.cpu.iq.rate 1.950334 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23925365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011855 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022817228 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675235301 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957490366 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 132 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042076961 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 163 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64626006 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138535530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 270863 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192819 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46119094 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4653355 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69879497 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28935964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1499081 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201343583 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6151222 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624462299 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220966139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 473850 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 90091 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192819 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153540 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9614603 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768143 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988132356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573881676 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30019403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 127 # number of nop insts executed -system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed -system.cpu.iew.exec_branches 238305534 # Number of branches executed -system.cpu.iew.exec_stores 190166611 # Number of stores executed -system.cpu.iew.exec_rate 1.961484 # Inst execution rate -system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295701772 # num instructions producing a value -system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value +system.cpu.iew.exec_nop 238 # number of nop insts executed +system.cpu.iew.exec_refs 764075762 # number of memory reference insts executed +system.cpu.iew.exec_branches 238335526 # Number of branches executed +system.cpu.iew.exec_stores 190194086 # Number of stores executed +system.cpu.iew.exec_rate 1.921323 # Inst execution rate +system.cpu.iew.wb_sent 1965930006 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957490498 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296385031 # num instructions producing a value +system.cpu.iew.wb_consumers 2061135459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628966 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478367692 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15217365 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888709517 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727981 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401294450 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192123349 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72572906 8.17% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35244916 3.97% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18969010 2.13% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30763331 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20056672 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11441847 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106243036 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888709517 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -485,192 +486,192 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106243036 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2972596181 # The number of ROB reads -system.cpu.rob.rob_writes 4462393115 # The number of ROB writes -system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983907427 # The number of ROB reads +system.cpu.rob.rob_writes 4472910463 # The number of ROB writes +system.cpu.timesIdled 1017511 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76183341 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads -system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads -system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes -system.cpu.fp_regfile_reads 113 # number of floating regfile reads -system.cpu.fp_regfile_writes 115 # number of floating regfile writes -system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492660 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492660 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956386896 # number of integer regfile reads +system.cpu.int_regfile_writes 1937427158 # number of integer regfile writes +system.cpu.fp_regfile_reads 137 # number of floating regfile reads +system.cpu.fp_regfile_writes 146 # number of floating regfile writes +system.cpu.misc_regfile_reads 737590270 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 23 # number of replacements -system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use -system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks. +system.cpu.icache.replacements 21 # number of replacements +system.cpu.icache.tagsinuse 626.247624 # Cycle average of tags in use +system.cpu.icache.total_refs 288528273 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 370382.892169 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits -system.cpu.icache.overall_hits::total 286733320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses -system.cpu.icache.overall_misses::total 1160 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 626.247624 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.305785 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.305785 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288528273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288528273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288528273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288528273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288528273 # number of overall hits +system.cpu.icache.overall_hits::total 288528273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1181 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1181 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1181 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1181 # number of overall misses +system.cpu.icache.overall_misses::total 1181 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66140500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66140500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66140500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66140500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66140500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288529454 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288529454 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288529454 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288529454 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288529454 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56003.810330 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56003.810330 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56003.810330 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56003.810330 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 382 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 382 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 382 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 382 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43554500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 402 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 402 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 402 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 402 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46510000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46510000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46510000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46510000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46510000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46510000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55982.647815 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55982.647815 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59704.749679 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59704.749679 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59704.749679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59704.749679 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59704.749679 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.520943 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962028 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6289310 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6289336 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781550 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781550 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066723 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066723 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7356033 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7356059 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47744.264000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69584.220171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69576.928857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9598379 # number of replacements -system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use -system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.replacements 9597826 # number of replacements +system.cpu.dcache.tagsinuse 4088.019917 # Cycle average of tags in use +system.cpu.dcache.total_refs 656092202 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9601922 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.329258 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3440649000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.019917 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 489045122 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489045122 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167046955 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167046955 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits -system.cpu.dcache.overall_hits::total 656008046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656092077 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656092077 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656092077 # number of overall hits +system.cpu.dcache.overall_hits::total 656092077 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11476427 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11476427 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5539092 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5539092 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses -system.cpu.dcache.overall_misses::total 17008466 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015519 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015519 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015519 # number of overall misses +system.cpu.dcache.overall_misses::total 17015519 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322914399500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229337265001 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552251664501 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552251664501 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552251664501 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500521549 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500521549 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673107596 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673107596 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673107596 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673107596 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28137.189345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28137.189345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41403.404204 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41403.404204 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32455.763736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32455.763736 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26327984 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1057907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182334 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64553 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.267806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.388193 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks -system.cpu.dcache.writebacks::total 3781550 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781250 # number of writebacks +system.cpu.dcache.writebacks::total 3781250 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767955 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645642 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645642 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413597 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413597 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413597 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708472 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893450 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601922 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601922 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601922 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186178488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508071510 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269686560010 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269686560010 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24152.450512 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44103.658143 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28086.726804 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28086.726804 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 2877a6d58..7e4c9be17 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041615 # Number of seconds simulated -sim_ticks 41615049000 # Number of ticks simulated -final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041622 # Number of seconds simulated +sim_ticks 41622221000 # Number of ticks simulated +final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92405 # Simulator instruction rate (inst/s) -host_op_rate 92405 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41842312 # Simulator tick rate (ticks/s) -host_mem_usage 276220 # Number of bytes of host memory used -host_seconds 994.57 # Real time elapsed on the host +host_inst_rate 156492 # Simulator instruction rate (inst/s) +host_op_rate 156492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70874179 # Simulator tick rate (ticks/s) +host_mem_usage 228076 # Number of bytes of host memory used +host_seconds 587.27 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4296907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3297269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7594176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4296907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4296907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3297269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7594176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 229 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 356 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41614997000 # Total gap between requests +system.physmem.totGap 41622168000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 17845427 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 106827427 # Sum of mem lat for all requests -system.physmem.totBusLat 19752000 # Total cycles spent in databus access -system.physmem.totBankLat 69230000 # Total cycles spent in bank access -system.physmem.avgQLat 3613.90 # Average queueing delay per request -system.physmem.avgBankLat 14019.85 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21633.74 # Average memory access latency +system.physmem.totQLat 23375922 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests +system.physmem.totBusLat 24690000 # Total cycles spent in databus access +system.physmem.totBankLat 74071250 # Total cycles spent in bank access +system.physmem.avgQLat 4733.88 # Average queueing delay per request +system.physmem.avgBankLat 15000.25 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24734.14 # Average memory access latency system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4457 # Number of row buffer hits during reads +system.physmem.readRowHits 4243 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8427500.41 # Average gap between requests -system.cpu.branchPred.lookups 13412629 # Number of BP lookups -system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted +system.physmem.avgGap 8428952.61 # Average gap between requests +system.cpu.branchPred.lookups 13412628 # Number of BP lookups +system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996253 # DTB read hits +system.cpu.dtb.read_hits 19996247 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996263 # DTB read accesses -system.cpu.dtb.write_hits 6501863 # DTB write hits +system.cpu.dtb.read_accesses 19996257 # DTB read accesses +system.cpu.dtb.write_hits 6501860 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501886 # DTB write accesses -system.cpu.dtb.data_hits 26498116 # DTB hits +system.cpu.dtb.write_accesses 6501883 # DTB write accesses +system.cpu.dtb.data_hits 26498107 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498149 # DTB accesses -system.cpu.itb.fetch_hits 9956935 # ITB hits +system.cpu.dtb.data_accesses 26498140 # DTB accesses +system.cpu.itb.fetch_hits 9956943 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956984 # ITB accesses +system.cpu.itb.fetch_accesses 9956992 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83230099 # number of cpu cycles simulated +system.cpu.numCycles 83244443 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570549 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146019 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146021 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521872 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521870 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 57404029 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970257 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10685 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7622365 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607734 # Number of cycles cpu stages are processed. -system.cpu.activity 90.841817 # Percentage of cycles cpu is active +system.cpu.timesIdled 10691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7636719 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607724 # Number of cycles cpu stages are processed. +system.cpu.activity 90.826152 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.905629 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.905629 # CPI: Total CPI of All Threads -system.cpu.ipc 1.104205 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.104205 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27549736 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680363 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.899311 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33978401 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251698 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.175345 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33378776 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851323 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.895787 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65203595 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026504 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.658636 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29370403 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859696 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.711801 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29384711 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.730683 # Cycle average of tags in use -system.cpu.icache.total_refs 9945572 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use +system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.702941 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.730683 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728872 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728872 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945572 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945572 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945572 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945572 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945572 # number of overall hits -system.cpu.icache.overall_hits::total 9945572 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11363 # number of overall misses -system.cpu.icache.overall_misses::total 11363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 253418000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 253418000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 253418000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 253418000 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits +system.cpu.icache.overall_hits::total 9945578 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses +system.cpu.icache.overall_misses::total 11365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22302.032914 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22302.032914 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22302.032914 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22302.032914 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,50 +340,50 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1843 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1843 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1843 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1843 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1843 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204186500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 204186500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204186500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 204186500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204186500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204186500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21448.161765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21448.161765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21448.161765 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2190.387059 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.839462 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.429033 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.118565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055586 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066845 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -408,17 +408,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 127130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 149097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 79600500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127130500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101567000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 228697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127130500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101567000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 228697500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -443,17 +443,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45501.252684 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52053.317536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 46361.007463 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46225.609756 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 46313.791009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45501.252684 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47372.667910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 46313.791009 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 91774816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16652177 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -495,51 +495,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32847.106657 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39460.135071 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33714.861007 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33884.375726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32847.106657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34981.843284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33773.974889 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.892023 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.712551 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.892023 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352024 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352024 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488629 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488629 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488629 # number of overall hits -system.cpu.dcache.overall_hits::total 26488629 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits +system.cpu.dcache.overall_hits::total 26488625 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8672 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8672 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8672 # number of overall misses -system.cpu.dcache.overall_misses::total 8672 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28721000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28721000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 329862500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 329862500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 358583500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 358583500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 358583500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses +system.cpu.dcache.overall_misses::total 8676 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -550,25 +550,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49949.565217 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49949.565217 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40738.853897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40738.853897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41349.573339 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41349.573339 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11994 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 830 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.450602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -576,12 +576,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6349 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6349 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6449 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6449 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6449 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -590,14 +590,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22990000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 81618000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 104608000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 104608000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 104608000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -606,14 +606,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46692.219680 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47057.130004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47057.130004 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 32c2b95d3..c7256bad9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023378 # Number of seconds simulated -sim_ticks 23378067000 # Number of ticks simulated -final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023427 # Number of seconds simulated +sim_ticks 23426793000 # Number of ticks simulated +final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125836 # Simulator instruction rate (inst/s) -host_op_rate 125836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34946651 # Simulator tick rate (ticks/s) -host_mem_usage 277248 # Number of bytes of host memory used -host_seconds 668.96 # Real time elapsed on the host +host_inst_rate 213464 # Simulator instruction rate (inst/s) +host_op_rate 213464 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59405864 # Simulator tick rate (ticks/s) +host_mem_usage 230136 # Number of bytes of host memory used +host_seconds 394.35 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory system.physmem.bytes_read::total 334592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8365123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5917327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14282450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8365123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8365123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5917327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14282450 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 334592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 326 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 398 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23377961000 # Total gap between requests +system.physmem.totGap 23426687000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 21787213 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests -system.physmem.totBusLat 20912000 # Total cycles spent in databus access -system.physmem.totBankLat 73612000 # Total cycles spent in bank access -system.physmem.avgQLat 4167.41 # Average queueing delay per request -system.physmem.avgBankLat 14080.34 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22247.75 # Average memory access latency -system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 28657456 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests +system.physmem.totBusLat 26140000 # Total cycles spent in databus access +system.physmem.totBankLat 79090000 # Total cycles spent in bank access +system.physmem.avgQLat 5481.53 # Average queueing delay per request +system.physmem.avgBankLat 15128.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 25609.69 # Average memory access latency +system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.09 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.11 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4677 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4471683.44 # Average gap between requests -system.cpu.branchPred.lookups 14833517 # Number of BP lookups -system.cpu.branchPred.condPredicted 10762267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 917019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8075874 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6944735 # Number of BTB hits +system.physmem.avgGap 4481003.63 # Average gap between requests +system.cpu.branchPred.lookups 14862899 # Number of BP lookups +system.cpu.branchPred.condPredicted 10784279 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 925607 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8448126 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6969256 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.993603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1466052 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3147 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.494698 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468807 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3068 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23102664 # DTB read hits -system.cpu.dtb.read_misses 192481 # DTB read misses +system.cpu.dtb.read_hits 23133213 # DTB read hits +system.cpu.dtb.read_misses 193272 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23295145 # DTB read accesses -system.cpu.dtb.write_hits 7068005 # DTB write hits -system.cpu.dtb.write_misses 1092 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7069097 # DTB write accesses -system.cpu.dtb.data_hits 30170669 # DTB hits -system.cpu.dtb.data_misses 193573 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 30364242 # DTB accesses -system.cpu.itb.fetch_hits 14708082 # ITB hits -system.cpu.itb.fetch_misses 96 # ITB misses +system.cpu.dtb.read_accesses 23326485 # DTB read accesses +system.cpu.dtb.write_hits 7072266 # DTB write hits +system.cpu.dtb.write_misses 1114 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 7073380 # DTB write accesses +system.cpu.dtb.data_hits 30205479 # DTB hits +system.cpu.dtb.data_misses 194386 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30399865 # DTB accesses +system.cpu.itb.fetch_hits 14751258 # ITB hits +system.cpu.itb.fetch_misses 97 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14708178 # ITB accesses +system.cpu.itb.fetch_accesses 14751355 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46756135 # number of cpu cycles simulated +system.cpu.numCycles 46853587 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15478226 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127086204 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14862899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8438063 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22152522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4487790 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5536762 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 83 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2724 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14751258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326039 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24546018 52.56% 52.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2363136 5.06% 57.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191999 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1747286 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2758963 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1151332 2.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1219220 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 775308 1.66% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10945278 23.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46698540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317220 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.712411 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17303274 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4237001 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20547487 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094236 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3516542 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516790 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12060 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124092936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31896 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3516542 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18446150 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 953596 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20476535 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3298441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121253427 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 399455 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2423561 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89048453 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157563733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147863840 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9699893 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 739 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20621092 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 715 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25385907 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8248290 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2586709 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 908922 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105520430 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1810 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96627173 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 179301 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20866432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15656081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1421 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46698540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.069169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.876778 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12145462 26.01% 26.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9347287 20.02% 46.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8392983 17.97% 64.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6295181 13.48% 77.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4922186 10.54% 88.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2865412 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725444 3.69% 97.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 796771 1.71% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 207814 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46698540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 188040 12.01% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 192 0.01% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7132 0.46% 12.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5753 0.37% 12.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842663 53.82% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 443560 28.33% 95.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78346 5.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58768195 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479903 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800414 2.90% 64.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115399 0.12% 64.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387049 2.47% 66.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311103 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759957 0.79% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23849343 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7155484 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued -system.cpu.iq.rate 2.064556 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96627173 # Type of FU issued +system.cpu.iq.rate 2.062322 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1565686 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226574505 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117655638 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87117393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15123368 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8767383 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066303 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90201258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991594 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1516780 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5389709 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18571 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34473 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1747187 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10549 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3516542 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 131686 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18180 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115763317 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371525 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25385907 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8248290 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1810 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2912 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 33 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34473 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538490 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495901 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95392807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23326978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1234366 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10225482 # number of nop insts executed -system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed -system.cpu.iew.exec_branches 12021435 # Number of branches executed -system.cpu.iew.exec_stores 7069294 # Number of stores executed -system.cpu.iew.exec_rate 2.038429 # Inst execution rate -system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64468484 # num instructions producing a value -system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value +system.cpu.iew.exec_nop 10241077 # number of nop insts executed +system.cpu.iew.exec_refs 30400564 # number of memory reference insts executed +system.cpu.iew.exec_branches 12029650 # Number of branches executed +system.cpu.iew.exec_stores 7073586 # Number of stores executed +system.cpu.iew.exec_rate 2.035977 # Inst execution rate +system.cpu.iew.wb_sent 94705450 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94183696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64505139 # num instructions producing a value +system.cpu.iew.wb_consumers 89892889 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back +system.cpu.iew.wb_rate 2.010170 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717578 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23861264 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 913934 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43181998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.128272 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.745397 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16729209 38.74% 38.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9919354 22.97% 61.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4482137 10.38% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2267062 5.25% 77.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606601 3.72% 81.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1122793 2.60% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 721285 1.67% 85.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 818294 1.89% 87.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5515263 12.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43181998 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,192 +469,192 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5515263 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153198746 # The number of ROB reads -system.cpu.rob.rob_writes 234713539 # The number of ROB writes -system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153430014 # The number of ROB reads +system.cpu.rob.rob_writes 235069144 # The number of ROB writes +system.cpu.timesIdled 5265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555432 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800399 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800399 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129015669 # number of integer regfile reads -system.cpu.int_regfile_writes 70499119 # number of integer regfile writes -system.cpu.fp_regfile_reads 6185969 # number of floating regfile reads -system.cpu.fp_regfile_writes 6040722 # number of floating regfile writes -system.cpu.misc_regfile_reads 714490 # number of misc regfile reads +system.cpu.cpi 0.556590 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.556590 # CPI: Total CPI of All Threads +system.cpu.ipc 1.796655 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.796655 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129123035 # number of integer regfile reads +system.cpu.int_regfile_writes 70557439 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190540 # number of floating regfile reads +system.cpu.fp_regfile_writes 6048182 # number of floating regfile writes +system.cpu.misc_regfile_reads 714455 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 9535 # number of replacements -system.cpu.icache.tagsinuse 1597.711655 # Cycle average of tags in use -system.cpu.icache.total_refs 14694095 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11468 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1281.312783 # Average number of references to valid blocks. +system.cpu.icache.replacements 9558 # number of replacements +system.cpu.icache.tagsinuse 1591.672723 # Cycle average of tags in use +system.cpu.icache.total_refs 14737290 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11492 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1282.395580 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1597.711655 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.780133 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.780133 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14694095 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14694095 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14694095 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14694095 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14694095 # number of overall hits -system.cpu.icache.overall_hits::total 14694095 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13987 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13987 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13987 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13987 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13987 # number of overall misses -system.cpu.icache.overall_misses::total 13987 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 308160500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 308160500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 308160500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 308160500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 308160500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14708082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14708082 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14708082 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14708082 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14708082 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000951 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000951 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000951 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000951 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000951 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22031.922499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22031.922499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22031.922499 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1591.672723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777184 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777184 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14737290 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14737290 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14737290 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14737290 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14737290 # number of overall hits +system.cpu.icache.overall_hits::total 14737290 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13967 # number of overall misses +system.cpu.icache.overall_misses::total 13967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317608000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317608000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317608000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317608000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317608000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14751257 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14751257 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14751257 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14751257 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14751257 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000947 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000947 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000947 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000947 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000947 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.886876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22739.886876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.886876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22739.886876 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2519 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2519 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2519 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2519 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2519 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2519 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11468 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11468 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11468 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11468 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11468 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11468 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 234957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 234957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234957500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 234957500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20488.097314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2475 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2475 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2475 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2475 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2475 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2475 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 240859500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 240859500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 240859500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 240859500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 240859500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 240859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000779 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000779 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20958.884441 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20958.884441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20958.884441 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2411.634709 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8474 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.361103 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2404.595595 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8500 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3590 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.671111 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2014.246310 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 379.717288 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 381.714191 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.011588 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.073597 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8404 # number of ReadReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.061194 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.011649 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.073382 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8430 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8459 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6493006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6493006 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 230 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 230 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28096316 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28096316 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28096316 # number of overall hits +system.cpu.dcache.overall_hits::total 28096316 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1004 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1004 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8097 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8097 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9073 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9073 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9073 # number of overall misses -system.cpu.dcache.overall_misses::total 9073 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44122000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44122000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 343188654 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 343188654 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9101 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9101 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9101 # number of overall misses +system.cpu.dcache.overall_misses::total 9101 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 50487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 50487500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 356466299 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 356466299 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 387310654 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 387310654 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 387310654 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 387310654 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21571640 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21571640 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 406953799 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 406953799 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 406953799 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21604314 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21604314 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28072743 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28072743 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28072743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28072743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 231 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28105417 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28105417 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28105417 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28105417 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000323 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000323 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45160.696008 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45160.696008 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42389.902915 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42389.902915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50286.354582 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50286.354582 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44024.490429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44024.490429 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42688.267828 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10592 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44715.283925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44715.283925 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14195 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 468 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 327 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.632479 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.409786 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6364 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6829 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6829 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6829 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6366 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6366 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6855 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6855 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6855 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26453500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82660498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 82660498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30190000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88528998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88528998 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 109113998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109113998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 109113998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118718998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118718998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118718998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004255 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004329 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004329 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51666.992188 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47725.460739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47725.460739 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58621.359223 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51143.268631 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51143.268631 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52857.968833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52857.968833 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b23c244b9..4d507d8ac 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074149 # Number of seconds simulated -sim_ticks 74148853000 # Number of ticks simulated -final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074156 # Number of seconds simulated +sim_ticks 74155951500 # Number of ticks simulated +final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87257 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37550131 # Simulator tick rate (ticks/s) -host_mem_usage 292636 # Number of bytes of host memory used -host_seconds 1974.66 # Real time elapsed on the host +host_inst_rate 108940 # Simulator instruction rate (inst/s) +host_op_rate 119280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46885764 # Simulator tick rate (ticks/s) +host_mem_usage 245224 # Number of bytes of host memory used +host_seconds 1581.63 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111744 # Number of bytes read from this memory -system.physmem.bytes_read::total 243392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131648 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2057 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1746 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3803 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1775456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1507023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3282478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1775456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1775456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1775456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1507023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3282478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3804 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112064 # Number of bytes read from this memory +system.physmem.bytes_read::total 243840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1751 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3810 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1777012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1511194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3288205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1777012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1777012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1777012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1511194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3288205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3811 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3804 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 243392 # Total number of bytes read from memory +system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 243840 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 243840 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 319 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 282 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 261 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 194 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74148834500 # Total gap between requests +system.physmem.totGap 74155933000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3804 # Categorize read packet sizes +system.physmem.readPktSize::6 3811 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 2808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11954297 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 86040297 # Sum of mem lat for all requests -system.physmem.totBusLat 15216000 # Total cycles spent in databus access -system.physmem.totBankLat 58870000 # Total cycles spent in bank access -system.physmem.avgQLat 3142.56 # Average queueing delay per request -system.physmem.avgBankLat 15475.81 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22618.37 # Average memory access latency -system.physmem.avgRdBW 3.28 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 17813284 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests +system.physmem.totBusLat 19055000 # Total cycles spent in databus access +system.physmem.totBankLat 67017500 # Total cycles spent in bank access +system.physmem.avgQLat 4674.18 # Average queueing delay per request +system.physmem.avgBankLat 17585.28 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27259.46 # Average memory access latency +system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.28 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3306 # Number of row buffer hits during reads +system.physmem.readRowHits 3029 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19492332.94 # Average gap between requests -system.cpu.branchPred.lookups 94799058 # Number of BP lookups -system.cpu.branchPred.condPredicted 74801869 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6279291 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44724397 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43048437 # Number of BTB hits +system.physmem.avgGap 19458392.29 # Average gap between requests +system.cpu.branchPred.lookups 94769609 # Number of BP lookups +system.cpu.branchPred.condPredicted 74778233 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6277605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44694278 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43050555 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.252694 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4355507 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88338 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.322297 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4352672 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88403 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -237,135 +237,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148297707 # number of cpu cycles simulated +system.cpu.numCycles 148311904 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47403944 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80363745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27281096 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7190522 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 43 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5914 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39646309 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380172339 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94769609 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47403227 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80367500 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27273234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7195566 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5621 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36846162 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1830987 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148197153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.802808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.153253 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36841499 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1830160 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148194878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152973 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68002614 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5258973 3.55% 49.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10529156 7.10% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10279296 6.94% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8665155 5.85% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6547882 4.42% 73.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6243481 4.21% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8012637 5.41% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24657959 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67997083 45.88% 45.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5272996 3.56% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10535975 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10290073 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8651484 5.84% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6547502 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243559 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8000119 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24656087 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148197153 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.639248 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.564002 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45504222 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5859124 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74799977 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201103 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832727 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14326960 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164415 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392837219 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 734618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832727 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50888432 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722612 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 592441 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70554465 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4606476 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371355589 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3653545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631848996 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581867929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564559444 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17308485 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148194878 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638989 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.563330 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45496007 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5866375 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74802564 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1203257 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20826675 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14321536 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392763604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 730055 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20826675 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50882111 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 721217 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 592672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70557397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4614806 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371296733 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 341377 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3661217 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631671723 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581648558 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564322118 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17326440 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333804857 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25171 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13001756 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43004891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16418786 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5685881 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3634471 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329217927 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47188 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249444233 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 790071 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139538270 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362161071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1972 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148197153 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761683 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333627584 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25019 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25015 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13027360 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43001248 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16425649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5676819 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3663476 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329185491 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47072 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249459953 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787409 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139507738 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 361963164 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148194878 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683324 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761955 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56041941 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22617532 15.26% 53.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24819018 16.75% 69.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20330052 13.72% 83.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12543560 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6522981 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4027974 2.72% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1111240 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182855 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56034848 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22634456 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24811776 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20313354 13.71% 83.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12551343 8.47% 92.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6515797 4.40% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4037298 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1114310 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181696 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148197153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148194878 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 964308 38.46% 38.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5601 0.22% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 100 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1163168 46.39% 85.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 374037 14.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964655 38.37% 38.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5597 0.22% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 98 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 47 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1171629 46.60% 85.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372002 14.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194888705 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979440 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194901733 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979970 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -384,93 +384,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33084 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33123 0.01% 78.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164341 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254530 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76430 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465703 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355599 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13947826 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164480 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254950 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465883 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206474 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71858 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38354449 15.37% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13950286 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249444233 # Type of FU issued -system.cpu.iq.rate 1.682051 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2507262 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010051 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646645921 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466634028 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237875698 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3737031 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2187759 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1841461 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250076224 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1875271 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2007740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249459953 # Type of FU issued +system.cpu.iq.rate 1.681995 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2514028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646678377 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466567894 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237899290 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737844 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2190776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842401 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250099013 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1874968 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2006458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13155407 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11336 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18867 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3774152 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13151764 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11904 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18813 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3781015 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832727 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16956 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 865 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329282292 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 783571 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43004891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16418786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24780 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 273 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18867 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889474 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3759056 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7648530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242951850 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36852953 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6492383 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20826675 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16651 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 839 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329249613 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 779131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43001248 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16425649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24664 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18813 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3890202 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3759917 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650119 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242971028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36855113 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6488925 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17177 # number of nop insts executed -system.cpu.iew.exec_refs 50499895 # number of memory reference insts executed -system.cpu.iew.exec_branches 53421871 # Number of branches executed -system.cpu.iew.exec_stores 13646942 # Number of stores executed -system.cpu.iew.exec_rate 1.638271 # Inst execution rate -system.cpu.iew.wb_sent 240774594 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239717159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148465347 # num instructions producing a value -system.cpu.iew.wb_consumers 267264848 # num instructions consuming a value +system.cpu.iew.exec_nop 17050 # number of nop insts executed +system.cpu.iew.exec_refs 50502517 # number of memory reference insts executed +system.cpu.iew.exec_branches 53426440 # Number of branches executed +system.cpu.iew.exec_stores 13647404 # Number of stores executed +system.cpu.iew.exec_rate 1.638244 # Inst execution rate +system.cpu.iew.wb_sent 240798946 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239741691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148482444 # num instructions producing a value +system.cpu.iew.wb_consumers 267276214 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616459 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555499 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616470 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140611386 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140578703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6125994 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127364426 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186226 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6124430 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127368203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186211 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57685030 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31666758 24.86% 70.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13788542 10.83% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7634444 5.99% 86.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4378206 3.44% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321179 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1702157 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1312824 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7875286 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57677570 45.28% 45.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31688766 24.88% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13782136 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7629564 5.99% 86.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4377691 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1320690 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1704652 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1310037 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877097 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127364426 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127368203 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -481,192 +481,196 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7875286 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877097 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448766216 # The number of ROB reads -system.cpu.rob.rob_writes 679506166 # The number of ROB writes -system.cpu.timesIdled 2556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 100554 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448735499 # The number of ROB reads +system.cpu.rob.rob_writes 679435154 # The number of ROB writes +system.cpu.timesIdled 2602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 117026 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.860680 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.860680 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161872 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161872 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079384127 # number of integer regfile reads -system.cpu.int_regfile_writes 384869699 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912697 # number of floating regfile reads -system.cpu.fp_regfile_writes 2497246 # number of floating regfile writes -system.cpu.misc_regfile_reads 54493639 # number of misc regfile reads +system.cpu.cpi 0.860762 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.860762 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161761 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161761 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079459412 # number of integer regfile reads +system.cpu.int_regfile_writes 384885584 # number of integer regfile writes +system.cpu.fp_regfile_reads 2914044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2498648 # number of floating regfile writes +system.cpu.misc_regfile_reads 54505090 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.icache.replacements 2375 # number of replacements -system.cpu.icache.tagsinuse 1350.215949 # Cycle average of tags in use -system.cpu.icache.total_refs 36840897 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8974.639951 # Average number of references to valid blocks. +system.cpu.icache.replacements 2367 # number of replacements +system.cpu.icache.tagsinuse 1349.329106 # Cycle average of tags in use +system.cpu.icache.total_refs 36836268 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4097 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8991.034415 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.215949 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659285 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659285 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36840897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36840897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36840897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36840897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36840897 # number of overall hits -system.cpu.icache.overall_hits::total 36840897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5265 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5265 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5265 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5265 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5265 # number of overall misses -system.cpu.icache.overall_misses::total 5265 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 158318499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 158318499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 158318499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 158318499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 158318499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 158318499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36846162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36846162 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36846162 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36846162 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36846162 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36846162 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30069.990313 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30069.990313 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30069.990313 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30069.990313 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30069.990313 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 679 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1349.329106 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.658852 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.658852 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36836269 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36836269 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36836269 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36836269 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36836269 # number of overall hits +system.cpu.icache.overall_hits::total 36836269 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5230 # number of overall misses +system.cpu.icache.overall_misses::total 5230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 167188500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 167188500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 167188500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 167188500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 167188500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 167188500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36841499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36841499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36841499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36841499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36841499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36841499 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31967.208413 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31967.208413 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31967.208413 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31967.208413 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31967.208413 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 552 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.722222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1159 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1159 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1159 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1159 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1159 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4106 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4106 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4106 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4106 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4106 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4106 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121527999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 121527999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121527999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 121527999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121527999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 121527999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1129 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1129 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1129 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1129 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1129 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1129 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4101 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4101 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4101 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 128471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 128471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128471500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 128471500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29597.661715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29597.661715 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29597.661715 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29597.661715 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31326.871495 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31326.871495 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31326.871495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 31326.871495 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043583 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.059939 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2043 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2131 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 5.016873 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1429.150441 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 536.739967 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.043614 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.016380 # 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number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits -system.cpu.l2cache.overall_hits::total 2140 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 677 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2740 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2063 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3820 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2063 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1757 # number of overall misses -system.cpu.l2cache.overall_misses::total 3820 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46197.955390 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50571.185998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50366.828087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50810.550199 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50571.185998 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,184 +680,184 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58562641 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 129052068 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870588 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.638255 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501218 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34251.422255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33541.031501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33925.359621 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2060 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2735 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1076 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1076 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2060 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 58 # number of replacements -system.cpu.dcache.tagsinuse 1406.419520 # Cycle average of tags in use -system.cpu.dcache.total_refs 46792514 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25238.680690 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use +system.cpu.dcache.total_refs 46795714 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1861 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25145.466953 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1406.419520 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.343364 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.343364 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34391106 # 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number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22472 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46747641 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46747641 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46747641 # number of overall hits -system.cpu.dcache.overall_hits::total 46747641 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 46750832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46750832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46750832 # number of overall hits +system.cpu.dcache.overall_hits::total 46750832 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1904 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9656 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9656 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9656 # number of overall misses -system.cpu.dcache.overall_misses::total 9656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84169500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84169500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 293859496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 293859496 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9634 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9634 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9634 # number of overall misses +system.cpu.dcache.overall_misses::total 9634 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 93402000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 93402000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 306706496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 306706496 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 378028996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 378028996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 378028996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 378028996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34393010 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34393010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 400108496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 400108496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 400108496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 400108496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34396179 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34396179 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22468 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22468 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22474 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46757297 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46757297 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46757297 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46757297 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46760466 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46760466 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46760466 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46760466 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44206.670168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44206.670168 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37907.571723 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37907.571723 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49055.672269 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49055.672269 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39677.425097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39677.425097 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39149.647473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39149.647473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39149.647473 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 472 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41530.879801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41530.879801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41530.879801 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.307692 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1138 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1138 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6664 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6664 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1127 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7802 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7802 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7802 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7802 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1854 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1854 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1854 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1854 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36187000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36187000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 47523998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 47523998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83710998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 83710998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83710998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 83710998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7770 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7770 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7770 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7770 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 777 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 777 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1087 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1087 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41603000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50879498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 50879498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92482498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92482498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92482498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 92482498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47241.514360 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47241.514360 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43680.145221 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43680.145221 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45151.563107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45151.563107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53543.114543 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53543.114543 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46807.265869 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46807.265869 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49615.074034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49615.074034 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index daaac056b..ea454cb40 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.082648 # Number of seconds simulated -sim_ticks 82648140000 # Number of ticks simulated -final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.082836 # Number of seconds simulated +sim_ticks 82836235000 # Number of ticks simulated +final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59257 # Simulator instruction rate (inst/s) -host_op_rate 99320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37082179 # Simulator tick rate (ticks/s) -host_mem_usage 321776 # Number of bytes of host memory used -host_seconds 2228.78 # Real time elapsed on the host +host_inst_rate 72340 # Simulator instruction rate (inst/s) +host_op_rate 121249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45372545 # Simulator tick rate (ticks/s) +host_mem_usage 275820 # Number of bytes of host memory used +host_seconds 1825.69 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362961 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory -system.physmem.bytes_read::total 342144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5346 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2634397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4139766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2634397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2634397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4139766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5348 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory +system.physmem.bytes_read::total 342912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5358 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2636141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1503497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4139638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2636141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2636141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1503497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4139638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5362 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5502 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 342144 # Total number of bytes read from memory +system.physmem.cpureqs 5515 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342912 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 342144 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342912 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 368 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 306 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 260 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 352 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 369 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 295 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 153 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 82648109000 # Total gap between requests +system.physmem.totGap 82836206000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5348 # Categorize read packet sizes +system.physmem.readPktSize::6 5362 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -95,15 +95,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 154 # categorize neither packet sizes +system.physmem.neitherpktsize::6 153 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 4185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,164 +164,164 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16873822 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests -system.physmem.totBusLat 21392000 # Total cycles spent in databus access -system.physmem.totBankLat 84182000 # Total cycles spent in bank access -system.physmem.avgQLat 3155.16 # Average queueing delay per request -system.physmem.avgBankLat 15740.84 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22896.00 # Average memory access latency +system.physmem.totQLat 15727084 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests +system.physmem.totBusLat 26795000 # Total cycles spent in databus access +system.physmem.totBankLat 89663750 # Total cycles spent in bank access +system.physmem.avgQLat 2933.06 # Average queueing delay per request +system.physmem.avgBankLat 16722.07 # Average bank access latency per request +system.physmem.avgBusLat 4997.20 # Average bus latency per request +system.physmem.avgMemAccLat 24652.34 # Average memory access latency system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4742 # Number of row buffer hits during reads +system.physmem.readRowHits 4538 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15454021.88 # Average gap between requests -system.cpu.branchPred.lookups 19953215 # Number of BP lookups -system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits +system.physmem.avgGap 15448751.59 # Average gap between requests +system.cpu.branchPred.lookups 19976706 # Number of BP lookups +system.cpu.branchPred.condPredicted 19976706 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2014402 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 13812152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13105283 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.882267 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 165296281 # number of cpu cycles simulated +system.cpu.numCycles 165672471 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25870668 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219126869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19976706 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13105283 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 57628355 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17696017 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 66630701 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2007 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24475842 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426793 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.187647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.326502 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3450171 2.09% 73.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3573015 2.16% 75.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4309284 2.61% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2725915 1.65% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33580712 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 109520431 66.16% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3059143 1.85% 68.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2383042 1.44% 69.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2888379 1.74% 71.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3450462 2.08% 73.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3573116 2.16% 75.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4323051 2.61% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2727876 1.65% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33620676 20.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 165175969 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.120712 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324235 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38701150 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56465114 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 44698220 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9957565 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15353920 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 353610105 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 15353920 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 46165738 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14909579 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23078 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46524421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 42199233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 345243747 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 88 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17893684 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22177130 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 398936501 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 960723880 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 950976963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9746917 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 165546176 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.120580 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322651 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38775408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56644846 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 44737695 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9974174 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15414053 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354047911 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 15414053 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 46255302 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14979465 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23344 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46561207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42312805 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 345686471 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18031828 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22149425 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 50 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 399403706 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 962076305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 952204922 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9871383 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 139507897 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1674 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1664 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 90390787 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 86672801 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31756377 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 57758664 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18775058 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 333623093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3362 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 267451276 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 258403 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111810012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 230098900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2117 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 165175969 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.619190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505359 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 139975102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1676 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1665 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 90583210 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 86793756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 31811808 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 57862174 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18818230 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 334054188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3459 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267584091 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253989 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 112238541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 231222254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 165546176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.616371 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.504250 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44964626 27.22% 27.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46539597 28.18% 55.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32801785 19.86% 75.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19824720 12.00% 87.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13230335 8.01% 95.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4791341 2.90% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2351721 1.42% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 529174 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 142670 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45159771 27.28% 27.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46666031 28.19% 55.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32872103 19.86% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19858979 12.00% 87.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13194353 7.97% 95.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4779249 2.89% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2330620 1.41% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 541020 0.33% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 144050 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 165175969 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 165546176 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 137826 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2250902 84.86% 90.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 263908 9.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 132244 4.97% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2258982 84.96% 89.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 267651 10.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212134 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174151286 65.12% 65.57% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174232004 65.11% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1593879 0.60% 66.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1599138 0.60% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued @@ -347,84 +347,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 67229168 25.14% 91.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23264809 8.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67256463 25.13% 91.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23284342 8.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 267451276 # Type of FU issued -system.cpu.iq.rate 1.618011 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2652636 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009918 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 697648502 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 441157156 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 260237459 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5341058 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4570848 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2570585 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266205797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2685981 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19039823 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267584091 # Type of FU issued +system.cpu.iq.rate 1.615139 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2658877 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 698266747 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 441935949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260335869 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5360477 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4651988 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2579879 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266334819 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2696005 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19019917 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30023215 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29490 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 296813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11240660 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 30144170 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29191 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 297029 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11296091 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49425 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49411 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15353920 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 582358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 260686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 333626455 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 190123 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 86672801 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31756377 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 146774 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 31153 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 296813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1177159 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 916050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2093209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264577691 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 66245889 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2873585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 15414053 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 584332 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 268197 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 334057647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 187603 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 86793756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 31811808 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1663 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 154006 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31822 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 297029 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1177472 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 918811 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2096283 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264704604 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66268952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2879487 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 89117815 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597039 # Number of branches executed -system.cpu.iew.exec_stores 22871926 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 263630467 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 262808044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 212084858 # num instructions producing a value -system.cpu.iew.wb_consumers 375096623 # num instructions consuming a value +system.cpu.iew.exec_refs 89158933 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605846 # Number of branches executed +system.cpu.iew.exec_stores 22889981 # Number of stores executed +system.cpu.iew.exec_rate 1.597759 # Inst execution rate +system.cpu.iew.wb_sent 263752937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 262915748 # cumulative count of insts written-back +system.cpu.iew.wb_producers 212158955 # num instructions producing a value +system.cpu.iew.wb_consumers 375269860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.589921 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.565414 # average fanout of values written-back +system.cpu.iew.wb_rate 1.586961 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.565350 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 112301239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 112734910 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2011502 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.477506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.946000 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2014608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 150132123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.474454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.942401 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50722618 33.86% 33.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57116806 38.12% 71.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13820755 9.22% 81.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12019830 8.02% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4145175 2.77% 91.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2956577 1.97% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1072909 0.72% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 994916 0.66% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6972463 4.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50871002 33.88% 33.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57276171 38.15% 72.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13824598 9.21% 81.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12056402 8.03% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4136994 2.76% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2958422 1.97% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1072501 0.71% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 994968 0.66% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6941065 4.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 150132123 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -435,198 +435,198 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339551 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6972463 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6941065 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 476513786 # The number of ROB reads -system.cpu.rob.rob_writes 682717187 # The number of ROB writes -system.cpu.timesIdled 2881 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 120312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 477288929 # The number of ROB reads +system.cpu.rob.rob_writes 683644230 # The number of ROB writes +system.cpu.timesIdled 2956 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 126295 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 1.251570 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251570 # CPI: Total CPI of All Threads -system.cpu.ipc 0.798997 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 562635091 # number of integer regfile reads -system.cpu.int_regfile_writes 298739906 # number of integer regfile writes -system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads -system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes -system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads +system.cpu.cpi 1.254418 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.254418 # CPI: Total CPI of All Threads +system.cpu.ipc 0.797182 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.797182 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 562757952 # number of integer regfile reads +system.cpu.int_regfile_writes 298813122 # number of integer regfile writes +system.cpu.fp_regfile_reads 3531630 # number of floating regfile reads +system.cpu.fp_regfile_writes 2237821 # number of floating regfile writes +system.cpu.misc_regfile_reads 137110805 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4732 # number of replacements -system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use -system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. +system.cpu.icache.replacements 4901 # number of replacements +system.cpu.icache.tagsinuse 1627.835837 # Cycle average of tags in use +system.cpu.icache.total_refs 24466683 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6871 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3560.862029 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits -system.cpu.icache.overall_hits::total 24437101 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses -system.cpu.icache.overall_misses::total 8952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # 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Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.794842 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24466683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24466683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24466683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24466683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24466683 # number of overall hits +system.cpu.icache.overall_hits::total 24466683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9159 # number of overall misses +system.cpu.icache.overall_misses::total 9159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 269675497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 269675497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 269675497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 269675497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 269675497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24475842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24475842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24475842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24475842 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29443.770827 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.230769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,100 +635,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3402 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 386 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3788 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 154 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 154 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995519 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 55 # number of replacements -system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use -system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. +system.cpu.dcache.replacements 56 # number of replacements +system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use +system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits -system.cpu.dcache.overall_hits::total 67560798 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.345816 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117154000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117154000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 47090980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 47090980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 67606711 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67606711 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67606711 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67606711 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses @@ -737,48 +737,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50254.740834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50254.740834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45106.351981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45106.351981 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46730.753889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 14 # number of writebacks -system.cpu.dcache.writebacks::total 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 13 # number of writebacks +system.cpu.dcache.writebacks::total 13 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1715 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1715 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2139 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2139 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2139 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 98158500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98158500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 98158500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses @@ -787,14 +787,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57126.179245 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43111.953353 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 6b719babe..a5d2b415b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -197,7 +197,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -440,8 +440,8 @@ system.cpu0.num_fp_register_writes 150767 # nu system.cpu0.num_mem_refs 15124548 # number of memory refs system.cpu0.num_load_insts 9178366 # Number of load instructions system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.836560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.163440 # Number of busy cycles +system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2435d9264..178493c15 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -187,7 +187,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115688 # number of memory refs system.cpu.num_load_insts 9747503 # Number of load instructions system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606250.520791 # Number of idle cycles -system.cpu.num_busy_cycles 60054827.479209 # Number of busy cycles +system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles +system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983586 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2042707 # number of replacements +system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits +system.cpu.dcache.overall_hits::total 13655968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 0e2cc710f..e93e66fed 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.950814 # Number of seconds simulated -sim_ticks 1950813955500 # Number of ticks simulated -final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.952724 # Number of seconds simulated +sim_ticks 1952724269500 # Number of ticks simulated +final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720692 # Simulator instruction rate (inst/s) -host_op_rate 720692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23054537293 # Simulator tick rate (ticks/s) -host_mem_usage 378432 # Number of bytes of host memory used -host_seconds 84.62 # Real time elapsed on the host -sim_insts 60983017 # Number of instructions simulated -sim_ops 60983017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory +host_inst_rate 1678586 # Simulator instruction rate (inst/s) +host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53851852439 # Simulator tick rate (ticks/s) +host_mem_usage 333452 # Number of bytes of host memory used +host_seconds 36.26 # Real time elapsed on the host +sim_insts 60867235 # Number of instructions simulated +sim_ops 60867235 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory -system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory -system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448191 # Total number of read requests seen -system.physmem.writeReqs 120414 # Total number of write requests seen -system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28684224 # Total number of bytes read from memory -system.physmem.bytesWritten 7706496 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis +system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448125 # Total number of read requests seen +system.physmem.writeReqs 120294 # Total number of write requests seen +system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28680000 # Total number of bytes read from memory +system.physmem.bytesWritten 7698816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry -system.physmem.totGap 1950760240000 # Total gap between requests +system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry +system.physmem.totGap 1952670553500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448191 # Categorize read packet sizes +system.physmem.readPktSize::6 448125 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 120944 # categorize write packet sizes +system.physmem.writePktSize::6 121700 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,30 +116,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes +system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests -system.physmem.totBusLat 1792536000 # Total cycles spent in databus access -system.physmem.totBankLat 6288996000 # Total cycles spent in bank access -system.physmem.avgQLat 6509.40 # Average queueing delay per request -system.physmem.avgBankLat 14033.74 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24543.14 # Average memory access latency -system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests +system.physmem.totBusLat 2240285000 # Total cycles spent in databus access +system.physmem.totBankLat 6409700000 # Total cycles spent in bank access +system.physmem.avgQLat 10709.68 # Average queueing delay per request +system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30015.22 # Average memory access latency +system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.51 # Average write queue length over time -system.physmem.readRowHits 428061 # Number of row buffer hits during reads -system.physmem.writeRowHits 76773 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes -system.physmem.avgGap 3430782.78 # Average gap between requests -system.l2c.replacements 341335 # number of replacements -system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use -system.l2c.total_refs 2438054 # Total number of references to valid blocks. -system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55545.332470 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13479449779 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372964000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391135500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2145152500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673668500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2818821000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3518116500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691840000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4209956500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289728 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138411 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944836 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765590 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.869492 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956379 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975983 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966176 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476448 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.123527 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412501 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172821 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172821 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30843.988439 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65801.895833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31800.809651 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.130007 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.901213 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.493693 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10145.165336 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -503,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.562950 # Cycle average of tags in use +system.iocache.tagsinuse 0.569993 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -521,12 +521,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -545,17 +545,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7424685 # DTB read hits +system.cpu0.dtb.read_hits 7490982 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5011105 # DTB write hits +system.cpu0.dtb.write_hits 5068153 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12435790 # DTB hits +system.cpu0.dtb.data_hits 12559135 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3481701 # ITB hits +system.cpu0.itb.fetch_hits 3503456 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3485572 # ITB accesses +system.cpu0.itb.fetch_accesses 3507327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3900399041 # number of cpu cycles simulated +system.cpu0.numCycles 3904305293 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47350784 # Number of instructions committed -system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses -system.cpu0.num_func_calls 1188579 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43919786 # number of integer instructions -system.cpu0.num_fp_insts 206365 # number of float instructions -system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written -system.cpu0.num_mem_refs 12475691 # number of memory refs -system.cpu0.num_load_insts 7451626 # Number of load instructions -system.cpu0.num_store_insts 5024065 # Number of store instructions -system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles -system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles +system.cpu0.committedInsts 47706703 # Number of instructions committed +system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses +system.cpu0.num_func_calls 1201591 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44241786 # number of integer instructions +system.cpu0.num_fp_insts 211423 # number of float instructions +system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599388 # number of memory refs +system.cpu0.num_load_insts 7518173 # Number of load instructions +system.cpu0.num_store_insts 5081215 # Number of store instructions +system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles +system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed -system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed +system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147588 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.callpal::total 149953 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed +system.cpu0.kern.swap_context 3075 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 686544 # number of replacements -system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use -system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits -system.cpu0.icache.overall_hits::total 46672235 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses -system.cpu0.icache.overall_misses::total 687149 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency +system.cpu0.icache.replacements 699703 # number of replacements +system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use +system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits +system.cpu0.icache.overall_hits::total 47014995 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses +system.cpu0.icache.overall_misses::total 700308 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1171731 # number of replacements -system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986845 # 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number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses +system.cpu0.dcache.overall_misses::total 1191529 # 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number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks +system.cpu0.dcache.writebacks::total 680601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2500361 # DTB read hits +system.cpu1.dtb.read_hits 2417694 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1820984 # DTB write hits +system.cpu1.dtb.write_hits 1754404 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4321345 # DTB hits +system.cpu1.dtb.data_hits 4172098 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1990033 # ITB hits +system.cpu1.itb.fetch_hits 1961503 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991249 # ITB accesses +system.cpu1.itb.fetch_accesses 1962719 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3901627911 # number of cpu cycles simulated +system.cpu1.numCycles 3905448539 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13632233 # Number of instructions committed -system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses -system.cpu1.num_func_calls 426713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12571690 # number of integer instructions -system.cpu1.num_fp_insts 180459 # number of float instructions -system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written -system.cpu1.num_mem_refs 4345653 # number of memory refs -system.cpu1.num_load_insts 2515108 # Number of load instructions -system.cpu1.num_store_insts 1830545 # Number of store instructions -system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles +system.cpu1.committedInsts 13160532 # Number of instructions committed +system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses +system.cpu1.num_func_calls 411397 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12141335 # number of integer instructions +system.cpu1.num_fp_insts 171917 # number of float instructions +system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written +system.cpu1.num_mem_refs 4195541 # number of memory refs +system.cpu1.num_load_insts 2431931 # Number of load instructions +system.cpu1.num_store_insts 1763610 # Number of store instructions +system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed -system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed +system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73828 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches +system.cpu1.kern.callpal::total 71284 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 450 -system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2086 # number of times the context was actually changed -system.cpu1.icache.replacements 328646 # number of replacements -system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use -system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits -system.cpu1.icache.overall_hits::total 13306402 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses -system.cpu1.icache.overall_misses::total 329194 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1984 # number of times the context was actually changed +system.cpu1.icache.replacements 314891 # number of replacements +system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use +system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits +system.cpu1.icache.overall_hits::total 12848456 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses +system.cpu1.icache.overall_misses::total 315439 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 172801 # number of replacements -system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits -system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses -system.cpu1.dcache.overall_misses::total 188010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # 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average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency +system.cpu1.dcache.replacements 165415 # number of replacements +system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47962 # 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miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks -system.cpu1.dcache.writebacks::total 119125 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks +system.cpu1.dcache.writebacks::total 113605 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # 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mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e3ca77030..37fa2c1e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910582 # Number of seconds simulated -sim_ticks 1910582068000 # Number of ticks simulated -final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910548 # Number of seconds simulated +sim_ticks 1910547559000 # Number of ticks simulated +final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951839 # Simulator instruction rate (inst/s) -host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32401800424 # Simulator tick rate (ticks/s) -host_mem_usage 374212 # Number of bytes of host memory used -host_seconds 58.97 # Real time elapsed on the host -sim_insts 56125446 # Number of instructions simulated -sim_ops 56125446 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +host_inst_rate 1284259 # Simulator instruction rate (inst/s) +host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43720523895 # Simulator tick rate (ticks/s) +host_mem_usage 330356 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +sim_insts 56120911 # Number of instructions simulated +sim_ops 56120911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442975 # Total number of read requests seen -system.physmem.writeReqs 115503 # Total number of write requests seen -system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28350400 # Total number of bytes read from memory -system.physmem.bytesWritten 7392192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Total number of read requests seen +system.physmem.writeReqs 115693 # Total number of write requests seen +system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28361344 # Total number of bytes read from memory +system.physmem.bytesWritten 7404352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910535659000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::6 443146 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::6 117758 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 130 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests -system.physmem.totBusLat 1771696000 # Total cycles spent in databus access -system.physmem.totBankLat 6202518000 # Total cycles spent in bank access -system.physmem.avgQLat 6332.72 # Average queueing delay per request -system.physmem.avgBankLat 14003.57 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests +system.physmem.totBusLat 2215505000 # Total cycles spent in databus access +system.physmem.totBankLat 6296675000 # Total cycles spent in bank access +system.physmem.avgQLat 10647.84 # Average queueing delay per request +system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29858.31 # Average memory access latency system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.48 # Average write queue length over time -system.physmem.readRowHits 423327 # Number of row buffer hits during reads -system.physmem.writeRowHits 74914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes -system.physmem.avgGap 3421030.31 # Average gap between requests +system.physmem.avgWrQLen 11.47 # Average write queue length over time +system.physmem.readRowHits 415807 # Number of row buffer hits during reads +system.physmem.writeRowHits 89941 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 3418758.64 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342666 # Cycle average of tags in use +system.iocache.tagsinuse 1.342284 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055970 # DTB read hits +system.cpu.dtb.read_hits 9055197 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6351685 # DTB write hits +system.cpu.dtb.write_hits 6350929 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15407655 # DTB hits +system.cpu.dtb.data_hits 15406126 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974178 # ITB hits +system.cpu.itb.fetch_hits 4974131 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979184 # ITB accesses +system.cpu.itb.fetch_accesses 4979137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821164136 # number of cpu cycles simulated +system.cpu.numCycles 3821095118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125446 # Number of instructions committed -system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482010 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls -system.cpu.num_int_insts 51999916 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read -system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15460271 # number of memory refs -system.cpu.num_load_insts 9092827 # Number of load instructions -system.cpu.num_store_insts 6367444 # Number of store instructions -system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938806 # Percentage of idle cycles +system.cpu.committedInsts 56120911 # Number of instructions committed +system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1481756 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls +system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read +system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15458726 # number of memory refs +system.cpu.num_load_insts 9092044 # Number of load instructions +system.cpu.num_store_insts 6366682 # Number of store instructions +system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938773 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192878 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -470,51 +470,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927460 # number of replacements -system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use -system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits -system.cpu.icache.overall_hits::total 55209154 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses -system.cpu.icache.overall_misses::total 928131 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency +system.cpu.icache.replacements 927816 # number of replacements +system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use +system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits +system.cpu.icache.overall_hits::total 55204264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses +system.cpu.icache.overall_misses::total 928486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,126 +523,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928131 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928131 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928131 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928131 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928131 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928131 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10810056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10810056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10810056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10810056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10810056500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10810056500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11647.123628 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11647.123628 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928486 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928486 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928486 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928486 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928486 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928486 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10912126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10912126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10912126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10912126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10912126000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10912126000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016541 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016541 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016541 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11752.601547 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11752.601547 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 336061 # number of replacements -system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401224 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.094625 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 5214408002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55704.521339 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4784.646064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4834.680258 # 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Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.092390 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 5253905752 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 55746.369541 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4781.447334 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4792.532585 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.850622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.072959 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.073128 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.996709 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 915175 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814009 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729184 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187505 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187505 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 914821 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001682 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916503 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 914821 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001682 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916503 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # 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average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35628.402051 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35628.402051 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -718,79 +718,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389800 # number of replacements -system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use -system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1389814 # number of replacements +system.cpu.dcache.tagsinuse 511.980842 # Cycle average of tags in use +system.cpu.dcache.total_refs 14034828 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390326 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.094631 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.980842 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5847887 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # 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number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 5fe42fc21..839e0acab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -215,7 +215,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index bc1e2b029..9811be55f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -198,7 +198,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ebe1b98fa..13c85b6d1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182882 # Number of seconds simulated -sim_ticks 1182882156500 # Number of ticks simulated -final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.183003 # Number of seconds simulated +sim_ticks 1183003114000 # Number of ticks simulated +final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497131 # Simulator instruction rate (inst/s) -host_op_rate 633435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9569364300 # Simulator tick rate (ticks/s) -host_mem_usage 452888 # Number of bytes of host memory used -host_seconds 123.61 # Real time elapsed on the host -sim_insts 61450993 # Number of instructions simulated -sim_ops 78299715 # Number of ops (including micro ops) simulated +host_inst_rate 673901 # Simulator instruction rate (inst/s) +host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12970235901 # Simulator tick rate (ticks/s) +host_mem_usage 408748 # Number of bytes of host memory used +host_seconds 91.21 # Real time elapsed on the host +sim_insts 61465824 # Number of instructions simulated +sim_ops 78326377 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory -system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory +system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory +system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654451 # Total number of read requests seen -system.physmem.writeReqs 821128 # Total number of write requests seen -system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425884864 # Total number of bytes read from memory -system.physmem.bytesWritten 52552192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654023 # Total number of read requests seen +system.physmem.writeReqs 820738 # Total number of write requests seen +system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425857472 # Total number of bytes read from memory +system.physmem.bytesWritten 52527232 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182877668000 # Total gap between requests +system.physmem.totGap 1182998675500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159562 # Categorize read packet sizes +system.physmem.readPktSize::6 159134 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +125,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 64292 # categorize write packet sizes +system.physmem.writePktSize::6 63902 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +134,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests -system.physmem.totBusLat 26617276000 # Total cycles spent in databus access -system.physmem.totBankLat 8784524000 # Total cycles spent in bank access -system.physmem.avgQLat 18592.42 # Average queueing delay per request -system.physmem.avgBankLat 1320.12 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23912.55 # Average memory access latency -system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 15.12 # Average write queue length over time -system.physmem.readRowHits 6628163 # Number of row buffer hits during reads -system.physmem.writeRowHits 789308 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes -system.physmem.avgGap 158232.25 # Average gap between requests +system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests +system.physmem.totBusLat 33269555000 # Total cycles spent in databus access +system.physmem.totBankLat 9041986250 # Total cycles spent in bank access +system.physmem.avgQLat 22090.22 # Average queueing delay per request +system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28449.12 # Average memory access latency +system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 12.54 # Average write queue length over time +system.physmem.readRowHits 6611960 # Number of row buffer hits during reads +system.physmem.writeRowHits 800133 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes +system.physmem.avgGap 158265.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,237 +242,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69442 # number of replacements -system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use -system.l2c.total_refs 1672967 # Total number of references to valid blocks. -system.l2c.sampled_refs 134589 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.430191 # Average number of references to valid blocks. +system.l2c.replacements 69015 # number of replacements +system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use +system.l2c.total_refs 1678594 # Total number of references to valid blocks. +system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4237.001170 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742163 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.633866 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.365608 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613221 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056872 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064652 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031454 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809326 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4055 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1843 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 206158 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143311 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246376 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571308 # number of Writeback hits -system.l2c.Writeback_hits::total 571308 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1277 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1841 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56678 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52482 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109160 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1843 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 195793 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355536 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4055 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1843 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits -system.l2c.overall_hits::cpu0.data 262836 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5342 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1844 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464150 # number of overall hits -system.l2c.overall_hits::cpu1.data 195793 # number of overall hits -system.l2c.overall_hits::total 1355536 # number of overall hits +system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits +system.l2c.Writeback_hits::total 573205 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 534803 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070111 # DTB read hits -system.cpu0.dtb.read_misses 3764 # DTB read misses -system.cpu0.dtb.write_hits 5656042 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 5883553 # DTB read hits +system.cpu0.dtb.read_misses 2148 # DTB read misses +system.cpu0.dtb.write_hits 4842455 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073875 # DTB read accesses -system.cpu0.dtb.write_accesses 5656846 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5885701 # DTB read accesses +system.cpu0.dtb.write_accesses 4842860 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726153 # DTB hits -system.cpu0.dtb.misses 4568 # DTB misses -system.cpu0.dtb.accesses 12730721 # DTB accesses -system.cpu0.itb.inst_hits 29570310 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 10726008 # DTB hits +system.cpu0.dtb.misses 2553 # DTB misses +system.cpu0.dtb.accesses 10728561 # DTB accesses +system.cpu0.itb.inst_hits 24779849 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses -system.cpu0.itb.hits 29570310 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572515 # DTB accesses -system.cpu0.numCycles 2365764313 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses +system.cpu0.itb.hits 24779849 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24781199 # DTB accesses +system.cpu0.numCycles 2364565551 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872367 # Number of instructions committed -system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241715 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33098187 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394441 # number of memory refs -system.cpu0.num_load_insts 7407672 # Number of load instructions -system.cpu0.num_store_insts 5986769 # Number of store instructions -system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles -system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles +system.cpu0.committedInsts 24381823 # Number of instructions committed +system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 1070639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28075203 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read +system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 11318426 # number of memory refs +system.cpu0.num_load_insts 6163151 # Number of load instructions +system.cpu0.num_store_insts 5155275 # Number of store instructions +system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles +system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed -system.cpu0.icache.replacements 425445 # number of replacements -system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits -system.cpu0.icache.overall_hits::total 29144335 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses -system.cpu0.icache.overall_misses::total 425958 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency +system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed +system.cpu0.icache.replacements 354669 # number of replacements +system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use +system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits +system.cpu0.icache.overall_hits::total 24424650 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses +system.cpu0.icache.overall_misses::total 355182 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330355 # number of replacements -system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 453.331528 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.885413 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.885413 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6599943 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6599943 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5351121 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5351121 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147941 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147941 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149661 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149661 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11951064 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11951064 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11951064 # number of overall hits -system.cpu0.dcache.overall_hits::total 11951064 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227863 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227863 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141515 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141515 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9301 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9301 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369378 # 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Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # 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number of cycles access was blocked @@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks -system.cpu0.dcache.writebacks::total 306206 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # 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number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # 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average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # 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mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8310545 # DTB read hits -system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5827351 # DTB write hits -system.cpu1.dtb.write_misses 1434 # DTB write misses +system.cpu1.dtb.read_hits 9504194 # DTB read hits +system.cpu1.dtb.read_misses 5263 # DTB read misses +system.cpu1.dtb.write_hits 6646220 # DTB write hits +system.cpu1.dtb.write_misses 1833 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8314188 # DTB read accesses -system.cpu1.dtb.write_accesses 5828785 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9509457 # DTB read accesses +system.cpu1.dtb.write_accesses 6648053 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14137896 # DTB hits -system.cpu1.dtb.misses 5077 # DTB misses -system.cpu1.dtb.accesses 14142973 # DTB accesses -system.cpu1.itb.inst_hits 33189113 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 16150414 # DTB hits +system.cpu1.dtb.misses 7096 # DTB misses +system.cpu1.dtb.accesses 16157510 # DTB accesses +system.cpu1.itb.inst_hits 37994467 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses -system.cpu1.itb.hits 33189113 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33191284 # DTB accesses -system.cpu1.numCycles 2364318212 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses +system.cpu1.itb.hits 37994467 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 37997484 # DTB accesses +system.cpu1.numCycles 2366006228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578626 # Number of instructions committed -system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37313171 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14675641 # number of memory refs -system.cpu1.num_load_insts 8632449 # Number of load instructions -system.cpu1.num_store_insts 6043192 # Number of store instructions -system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles -system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles +system.cpu1.committedInsts 37084001 # Number of instructions committed +system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1133542 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42360540 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16764021 # number of memory refs +system.cpu1.num_load_insts 9884261 # Number of load instructions +system.cpu1.num_store_insts 6879760 # Number of store instructions +system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles +system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles +system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed -system.cpu1.icache.replacements 469194 # number of replacements -system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits -system.cpu1.icache.overall_hits::total 32719403 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses -system.cpu1.icache.overall_misses::total 469706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency +system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed +system.cpu1.icache.replacements 540342 # number of replacements +system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use +system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits +system.cpu1.icache.overall_hits::total 37453609 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses +system.cpu1.icache.overall_misses::total 540854 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # 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number of cycles access was blocked @@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks -system.cpu1.dcache.writebacks::total 265102 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b72126c20..73585121b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603635 # Number of seconds simulated -sim_ticks 2603634694000 # Number of ticks simulated -final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603665 # Number of seconds simulated +sim_ticks 2603664815000 # Number of ticks simulated +final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 413538 # Simulator instruction rate (inst/s) -host_op_rate 526220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17886148072 # Simulator tick rate (ticks/s) -host_mem_usage 448796 # Number of bytes of host memory used -host_seconds 145.57 # Real time elapsed on the host -sim_insts 60197457 # Number of instructions simulated -sim_ops 76600355 # Number of ops (including micro ops) simulated +host_inst_rate 536000 # Simulator instruction rate (inst/s) +host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23183028791 # Simulator tick rate (ticks/s) +host_mem_usage 404656 # Number of bytes of host memory used +host_seconds 112.31 # Real time elapsed on the host +sim_insts 60197643 # Number of instructions simulated +sim_ops 76600583 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory -system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494095 # Total number of read requests seen -system.physmem.writeReqs 811481 # Total number of write requests seen -system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991622080 # Total number of bytes read from memory -system.physmem.bytesWritten 51934784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603630334000 # Total gap between requests +system.physmem.totGap 2603660455000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +108,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57463 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +120,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,14 +153,14 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +169,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests -system.physmem.totBusLat 61975036000 # Total cycles spent in databus access -system.physmem.totBankLat 16863224000 # Total cycles spent in bank access -system.physmem.avgQLat 18619.82 # Average queueing delay per request -system.physmem.avgBankLat 1088.39 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23708.21 # Average memory access latency +system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests +system.physmem.totBusLat 77468765000 # Total cycles spent in databus access +system.physmem.totBankLat 17445216250 # Total cycles spent in bank access +system.physmem.avgQLat 22041.64 # Average queueing delay per request +system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28167.59 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 12.40 # Average write queue length over time -system.physmem.readRowHits 15451886 # Number of row buffer hits during reads -system.physmem.writeRowHits 785061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes -system.physmem.avgGap 159677.30 # Average gap between requests +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.13 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 15418905 # Number of row buffer hits during reads +system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes +system.physmem.avgGap 159679.22 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995645 # DTB read hits -system.cpu.dtb.read_misses 7331 # DTB read misses -system.cpu.dtb.write_hits 11230857 # DTB write hits +system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230865 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002976 # DTB read accesses -system.cpu.dtb.write_accesses 11233060 # DTB write accesses +system.cpu.dtb.read_accesses 15002999 # DTB read accesses +system.cpu.dtb.write_accesses 11233068 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226502 # DTB hits -system.cpu.dtb.misses 9534 # DTB misses -system.cpu.dtb.accesses 26236036 # DTB accesses -system.cpu.itb.inst_hits 61491397 # ITB inst hits +system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26236067 # DTB accesses +system.cpu.itb.inst_hits 61491584 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495868 # ITB inst accesses -system.cpu.itb.hits 61491397 # DTB hits +system.cpu.itb.inst_accesses 61496055 # ITB inst accesses +system.cpu.itb.hits 61491584 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495868 # DTB accesses -system.cpu.numCycles 5207269388 # number of cpu cycles simulated +system.cpu.itb.accesses 61496055 # DTB accesses +system.cpu.numCycles 5207329630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197457 # Number of instructions committed -system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses +system.cpu.committedInsts 60197643 # Number of instructions committed +system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139722 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868122 # number of integer instructions +system.cpu.num_func_calls 2139730 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868344 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written +system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393871 # number of memory refs -system.cpu.num_load_insts 15659652 # Number of load instructions -system.cpu.num_store_insts 11734219 # Number of store instructions -system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879373 # Percentage of idle cycles +system.cpu.num_mem_refs 27393912 # number of memory refs +system.cpu.num_load_insts 15659685 # Number of load instructions +system.cpu.num_store_insts 11734227 # Number of store instructions +system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879355 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855485 # number of replacements -system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use -system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits -system.cpu.icache.overall_hits::total 60635400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses -system.cpu.icache.overall_misses::total 855997 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses +system.cpu.icache.replacements 855486 # number of replacements +system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use +system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits +system.cpu.icache.overall_hits::total 60635586 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses +system.cpu.icache.overall_misses::total 855998 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +615,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627280 # number of replacements -system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655026 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627792 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.679719 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973048 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits +system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # 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number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits +system.cpu.dcache.overall_hits::total 23168189 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses +system.cpu.dcache.overall_misses::total 619303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027188 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027188 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026034 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026034 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026034 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026034 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.130145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.130145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32117.582132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +696,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596029 # number of writebacks -system.cpu.dcache.writebacks::total 596029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368781 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368781 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12008897500 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks +system.cpu.dcache.writebacks::total 596039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.130145 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30117.582132 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11575.425364 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19391.364480 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19391.364480 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 21a80bd51..9d3d17a68 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -211,7 +211,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 175418c2b..4cde41f9a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1071475 # Simulator instruction rate (inst/s) -host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27413112180 # Simulator tick rate (ticks/s) -host_mem_usage 626876 # Number of bytes of host memory used -host_seconds 186.48 # Real time elapsed on the host +host_inst_rate 1816388 # Simulator instruction rate (inst/s) +host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46471341970 # Simulator tick rate (ticks/s) +host_mem_usage 582576 # Number of bytes of host memory used +host_seconds 110.00 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated -sim_ops 409125923 # Number of ops (including micro ops) simulated +sim_ops 409125913 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -195,7 +195,7 @@ system.physmem.avgRdBW 0.00 # Av system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -264,22 +264,22 @@ system.cpu.numCycles 10224081964 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199810242 # Number of instructions committed -system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses +system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289914 # number of integer instructions +system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289904 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35624590 # number of memory refs system.cpu.num_load_insts 27216588 # Number of load instructions system.cpu.num_store_insts 8408002 # Number of store instructions -system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles -system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles +system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles +system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy @@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy @@ -471,7 +471,7 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. @@ -479,8 +479,8 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5387a3a4f..da7af1088 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,98 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191113 # Number of seconds simulated -sim_ticks 5191112864000 # Number of ticks simulated -final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.195162 # Number of seconds simulated +sim_ticks 5195162021000 # Number of ticks simulated +final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 663100 # Simulator instruction rate (inst/s) -host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26841102406 # Simulator tick rate (ticks/s) -host_mem_usage 658020 # Number of bytes of host memory used -host_seconds 193.40 # Real time elapsed on the host -sim_insts 128244620 # Number of instructions simulated -sim_ops 247214608 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory +host_inst_rate 973985 # Simulator instruction rate (inst/s) +host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39447094407 # Simulator tick rate (ticks/s) +host_mem_usage 612564 # Number of bytes of host memory used +host_seconds 131.70 # Real time elapsed on the host +sim_insts 128273348 # Number of instructions simulated +sim_ops 247275973 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory -system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory -system.physmem.bytes_written::total 8129280 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44568 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory +system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141037 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127020 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127020 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 549468 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2447457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565999 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 549468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4013456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198516 # Total number of read requests seen -system.physmem.writeReqs 127020 # Total number of write requests seen -system.physmem.cpureqs 331314 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12705024 # Total number of bytes read from memory -system.physmem.bytesWritten 8129280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12705024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8129280 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1599 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12028 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12411 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 11776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12663 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12788 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7719 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8225 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7712 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7893 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7991 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7528 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8281 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198400 # Total number of read requests seen +system.physmem.writeReqs 126924 # Total number of write requests seen +system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12697600 # Total number of bytes read from memory +system.physmem.bytesWritten 8123136 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5191112800500 # Total gap between requests +system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry +system.physmem.totGap 5195161957500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198516 # Categorize read packet sizes +system.physmem.readPktSize::6 198400 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -101,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 127020 # categorize write packet sizes +system.physmem.writePktSize::6 127557 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -110,30 +114,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1599 # categorize neither packet sizes +system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 158090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1081 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -146,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests -system.physmem.totBusLat 793712000 # Total cycles spent in databus access -system.physmem.totBankLat 2768514000 # Total cycles spent in bank access -system.physmem.avgQLat 14495.06 # Average queueing delay per request -system.physmem.avgBankLat 13952.23 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32447.29 # Average memory access latency -system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests +system.physmem.totBusLat 991710000 # Total cycles spent in databus access +system.physmem.totBankLat 2804230000 # Total cycles spent in bank access +system.physmem.avgQLat 20553.30 # Average queueing delay per request +system.physmem.avgBankLat 14138.36 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 39691.66 # Average memory access latency +system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.06 # Average write queue length over time -system.physmem.readRowHits 179831 # Number of row buffer hits during reads -system.physmem.writeRowHits 78085 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.47 # Row buffer hit rate for writes -system.physmem.avgGap 15946355.55 # Average gap between requests -system.iocache.replacements 47506 # number of replacements -system.iocache.tagsinuse 0.117830 # Cycle average of tags in use +system.physmem.avgWrQLen 12.66 # Average write queue length over time +system.physmem.readRowHits 175587 # Number of row buffer hits during reads +system.physmem.writeRowHits 94819 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.avgGap 15969193.66 # Average gap between requests +system.iocache.replacements 47509 # number of replacements +system.iocache.tagsinuse 0.124742 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47522 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47525 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044498925000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.117830 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007364 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007364 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 841 # number of ReadReq misses -system.iocache.ReadReq_misses::total 841 # number of ReadReq misses +system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47561 # number of demand (read+write) misses -system.iocache.demand_misses::total 47561 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47561 # number of overall misses -system.iocache.overall_misses::total 47561 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 133668932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 133668932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9598301160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9598301160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9731970092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9731970092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9731970092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9731970092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 841 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 841 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses +system.iocache.demand_misses::total 47564 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses +system.iocache.overall_misses::total 47564 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47561 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47561 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47561 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47561 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -241,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158940.466112 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 205443.089897 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 204620.804693 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78425 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10368 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.564140 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 841 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47561 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47561 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47561 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47561 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89906992 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89906992 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7166703132 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7256610124 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7256610124 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7256610124 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -283,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 152574.801287 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -304,75 +308,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10382225728 # number of cpu cycles simulated +system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128244620 # Number of instructions committed -system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses +system.cpu.committedInsts 128273348 # Number of instructions committed +system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls -system.cpu.num_int_insts 231949869 # number of integer instructions +system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls +system.cpu.num_int_insts 232011682 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read -system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22227095 # number of memory refs -system.cpu.num_load_insts 13866667 # Number of load instructions -system.cpu.num_store_insts 8360428 # Number of store instructions -system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942147 # Percentage of idle cycles +system.cpu.num_mem_refs 22232138 # number of memory refs +system.cpu.num_load_insts 13871783 # Number of load instructions +system.cpu.num_store_insts 8360355 # Number of store instructions +system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942191 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790930 # number of replacements -system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use -system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor +system.cpu.icache.replacements 791521 # number of replacements +system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use +system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits -system.cpu.icache.overall_hits::total 144455345 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses -system.cpu.icache.overall_misses::total 791449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.921076 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits +system.cpu.icache.overall_hits::total 144497694 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses +system.cpu.icache.overall_misses::total 792040 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,80 +385,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791449 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791449 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791449 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791449 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791449 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791449 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9288383000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9288383000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9288383000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9288383000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9288383000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076 # 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Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3675 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.094150 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164936292000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.069768 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191861 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7696 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7696 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3425 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7698 # 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number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 46136000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 46136000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.370419 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -463,78 +467,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 884 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 884 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4528 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4528 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4528 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37080000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37080000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37080000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.370419 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8189.045936 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8189.045936 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8189.045936 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8012 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.053256 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13052 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8025 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.626417 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162707625000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053256 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315829 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13068 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13068 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13068 # 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number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 98984000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 98984000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22262 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22262 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22262 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.412991 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.412991 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.412991 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7538 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,90 +547,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3347 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80596000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80596000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.412991 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.412991 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.412991 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.412991 # 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Average occupied blocks per requestor +system.cpu.dcache.replacements 1618787 # number of replacements +system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use +system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034928 # 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number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits +system.cpu.dcache.overall_hits::total 20023737 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621495 # 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average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -635,46 +639,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks -system.cpu.dcache.writebacks::total 1538028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315486 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 015bc1924..c8eb78d93 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409284500 # Number of ticks simulated -final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 200409293000 # Number of ticks simulated +final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13697441 # Simulator instruction rate (inst/s) -host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5245128514 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 38.21 # Real time elapsed on the host -sim_insts 523360203 # Number of instructions simulated -sim_ops 523360203 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory +host_inst_rate 19440889 # Simulator instruction rate (inst/s) +host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7408936081 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 27.05 # Real time elapsed on the host +sim_insts 525869186 # Number of instructions simulated +sim_ops 525869186 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory +testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -189,7 +189,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3909164 # DTB read hits +testsys.cpu.dtb.read_hits 3916928 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2312434 # DTB write hits +testsys.cpu.dtb.write_hits 2316846 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6221598 # DTB hits +testsys.cpu.dtb.data_hits 6233774 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4045775 # ITB hits +testsys.cpu.itb.fetch_hits 4052272 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses +testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 400807419 # number of cpu cycles simulated +testsys.cpu.numCycles 400815936 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 20218035 # Number of instructions committed -testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18800192 # number of integer instructions -testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6250795 # number of memory refs -testsys.cpu.num_load_insts 3936233 # Number of load instructions -testsys.cpu.num_store_insts 2314562 # Number of store instructions -testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles -testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles +testsys.cpu.committedInsts 20258165 # Number of instructions committed +testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses +testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses +testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18837392 # number of integer instructions +testsys.cpu.num_fp_insts 17313 # number of float instructions +testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written +testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read +testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written +testsys.cpu.num_mem_refs 6263009 # number of memory refs +testsys.cpu.num_load_insts 3944038 # Number of load instructions +testsys.cpu.num_store_insts 2318971 # Number of store instructions +testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles +testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl +testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -309,30 +309,30 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed -testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed +testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed +testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128057 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches +testsys.cpu.kern.callpal::total 128317 # number of callpals executed +testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 707 -testsys.cpu.kern.mode_good::user 702 -testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches +testsys.cpu.kern.mode_good::user 703 +testsys.cpu.kern.mode_good::idle 4 +testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 438 # number of times the context was actually changed +testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 437 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted @@ -343,9 +343,9 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) testsys.tsunami.ethernet.totPackets 13 # Total Packets @@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory +drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory +drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s) drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -560,7 +560,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 3721202 # DTB read hits +drivesys.cpu.dtb.read_hits 3729326 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.read_acv 30 # DTB read access violations drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 2081819 # DTB write hits +drivesys.cpu.dtb.write_hits 2086333 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 5803021 # DTB hits +drivesys.cpu.dtb.data_hits 5815659 # DTB hits drivesys.cpu.dtb.data_misses 569 # DTB misses drivesys.cpu.dtb.data_acv 40 # DTB access violations drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 4194101 # ITB hits +drivesys.cpu.itb.fetch_hits 4201097 # ITB hits drivesys.cpu.itb.fetch_misses 194 # ITB misses drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses +drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated +drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 19029878 # Number of instructions committed -drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses +drivesys.cpu.committedInsts 19071544 # Number of instructions committed +drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 17721251 # number of integer instructions +drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 17759891 # number of integer instructions drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 5824433 # number of memory refs -drivesys.cpu.num_load_insts 3742101 # Number of load instructions -drivesys.cpu.num_store_insts 2082332 # Number of store instructions -drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 5837119 # number of memory refs +drivesys.cpu.num_load_insts 3750273 # Number of load instructions +drivesys.cpu.num_store_insts 2086846 # Number of store instructions +drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl +drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -673,26 +673,26 @@ drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # nu drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed +drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 122686 # number of callpals executed +drivesys.cpu.kern.callpal::total 122978 # number of callpals executed drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches drivesys.cpu.kern.mode_good::kernel 143 drivesys.cpu.kern.mode_good::user 139 drivesys.cpu.kern.mode_good::idle 4 drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -704,9 +704,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets @@ -731,9 +731,9 @@ drivesys.tsunami.ethernet.totalRxDesc 8 # to drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -741,49 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- sim_seconds 0.000407 # Number of seconds simulated -sim_ticks 406952000 # Number of ticks simulated -final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 407365500 # Number of ticks simulated +final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7058170696 # Simulator instruction rate (inst/s) -host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5484794115 # Simulator tick rate (ticks/s) -host_mem_usage 514692 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -sim_insts 523432506 # Number of instructions simulated -sim_ops 523432506 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 12024534237 # Simulator instruction rate (inst/s) +host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9308365303 # Simulator tick rate (ticks/s) +host_mem_usage 472492 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 525940622 # Number of instructions simulated +sim_ops 525940622 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -933,7 +933,7 @@ testsys.physmem.avgRdBW 0.00 # Av testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -testsys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s testsys.physmem.busUtil 0.00 # Data bus utilization in percentage testsys.physmem.avgRdQLen 0.00 # Average read queue length over time testsys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -958,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 7069 # DTB read hits +testsys.cpu.dtb.read_hits 6900 # DTB read hits testsys.cpu.dtb.read_misses 0 # DTB read misses testsys.cpu.dtb.read_acv 0 # DTB read access violations testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 3933 # DTB write hits +testsys.cpu.dtb.write_hits 3839 # DTB write hits testsys.cpu.dtb.write_misses 0 # DTB write misses testsys.cpu.dtb.write_acv 0 # DTB write access violations testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 11002 # DTB hits +testsys.cpu.dtb.data_hits 10739 # DTB hits testsys.cpu.dtb.data_misses 0 # DTB misses testsys.cpu.dtb.data_acv 0 # DTB access violations testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 5992 # ITB hits +testsys.cpu.itb.fetch_hits 5847 # ITB hits testsys.cpu.itb.fetch_misses 0 # ITB misses testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 5992 # ITB accesses +testsys.cpu.itb.fetch_accesses 5847 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -986,58 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 821760 # number of cpu cycles simulated +testsys.cpu.numCycles 799188 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 36151 # Number of instructions committed -testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses +testsys.cpu.committedInsts 35284 # Number of instructions committed +testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 2388 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 33514 # number of integer instructions +testsys.cpu.num_func_calls 2330 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 32710 # number of integer instructions testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 11043 # number of memory refs -testsys.cpu.num_load_insts 7109 # Number of load instructions -testsys.cpu.num_store_insts 3934 # Number of store instructions -testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles -testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles +testsys.cpu.num_mem_refs 10779 # number of memory refs +testsys.cpu.num_load_insts 6939 # Number of load instructions +testsys.cpu.num_store_insts 3840 # Number of store instructions +testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles +testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl +testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed -testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 254 # number of callpals executed +testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed +testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed +testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 248 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 0 testsys.cpu.kern.mode_good::user 0 testsys.cpu.kern.mode_good::idle 0 @@ -1049,9 +1049,9 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1068,9 +1068,9 @@ testsys.tsunami.ethernet.totalRxDesc 0 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1078,34 +1078,34 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -1255,7 +1255,7 @@ drivesys.physmem.avgRdBW 0.00 # Av drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -drivesys.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time @@ -1308,7 +1308,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated +drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 36152 # Number of instructions committed @@ -1326,10 +1326,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu drivesys.cpu.num_mem_refs 11043 # number of memory refs drivesys.cpu.num_load_insts 7109 # Number of load instructions drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed @@ -1343,11 +1343,11 @@ drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # nu drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1371,9 +1371,9 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1392,7 +1392,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -1400,7 +1400,7 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index b21e4d084..9e62381ba 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18737000 # Number of ticks simulated -final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19476000 # Number of ticks simulated +final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42684 # Simulator instruction rate (inst/s) -host_op_rate 42679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125129111 # Simulator tick rate (ticks/s) -host_mem_usage 269636 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 78389 # Simulator instruction rate (inst/s) +host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238789679 # Simulator tick rate (ticks/s) +host_mem_usage 223680 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -37,21 +37,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 66 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18722500 # Total gap between requests +system.physmem.totGap 19461500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests -system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7910000 # Total cycles spent in bank access -system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16865.67 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24837.89 # Average memory access latency -system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2628216 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totBusLat 2345000 # Total cycles spent in databus access +system.physmem.totBankLat 8401250 # Total cycles spent in bank access +system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgBankLat 17913.11 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.62 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.01 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.69 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 401 # Number of row buffer hits during reads +system.physmem.readRowHits 377 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39920.04 # Average gap between requests +system.physmem.avgGap 41495.74 # Average gap between requests system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -202,14 +202,14 @@ system.cpu.dtb.read_hits 1183 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_hits 866 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.write_accesses 869 # DTB write accesses +system.cpu.dtb.data_hits 2049 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.dtb.data_accesses 2059 # DTB accesses system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -227,18 +227,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37475 # number of cpu cycles simulated +system.cpu.numCycles 38953 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2152 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). @@ -249,12 +249,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. -system.cpu.activity 19.677118 # Percentage of cycles cpu is active +system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7375 # Number of cycles cpu stages are processed. +system.cpu.activity 18.933073 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -266,72 +266,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use -system.cpu.icache.total_refs 561 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use +system.cpu.icache.total_refs 560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits -system.cpu.icache.overall_hits::total 561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses -system.cpu.icache.overall_misses::total 354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits +system.cpu.icache.overall_hits::total 560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses +system.cpu.icache.overall_misses::total 355 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -340,48 +340,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52524.834437 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -399,17 +399,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20888500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3558500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3558500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8903000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24447000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15544000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8903000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24447000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -432,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51641.196013 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56257.894737 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52748.737374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48746.575342 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52125.799574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51641.196013 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52994.047619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52125.799574 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,17 +462,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,27 +484,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.433203 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025496 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025496 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -521,14 +521,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5722500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5722500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15380500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15380500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21103000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21103000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21103000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -545,19 +545,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58994.845361 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58994.845361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43944.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43944.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47210.290828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47210.290828 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 178 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -577,14 +577,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3636000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9082000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -593,14 +593,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index a295cf48e..d7bf6a6b9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15802500 # Number of ticks simulated -final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16030500 # Number of ticks simulated +final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36566 # Simulator instruction rate (inst/s) -host_op_rate 36562 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90663114 # Simulator tick rate (ticks/s) -host_mem_usage 270656 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 76258 # Simulator instruction rate (inst/s) +host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191753794 # Simulator tick rate (ticks/s) +host_mem_usage 225728 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Total number of read requests seen +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31168 # Total number of bytes read from memory +system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31104 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15655000 # Total gap between requests +system.physmem.totGap 15817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 487 # Categorize read packet sizes +system.physmem.readPktSize::6 486 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3073487 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests -system.physmem.totBusLat 1948000 # Total cycles spent in databus access -system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 6311.06 # Average queueing delay per request -system.physmem.avgBankLat 16012.32 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26323.38 # Average memory access latency -system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2909986 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totBusLat 2430000 # Total cycles spent in databus access +system.physmem.totBankLat 8305000 # Total cycles spent in bank access +system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgBankLat 17088.48 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28076.10 # Average memory access latency +system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.81 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32145.79 # Average gap between requests -system.cpu.branchPred.lookups 2927 # Number of BP lookups -system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups -system.cpu.branchPred.BTBHits 757 # Number of BTB hits +system.physmem.avgGap 32545.27 # Average gap between requests +system.cpu.branchPred.lookups 2896 # Number of BP lookups +system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups +system.cpu.branchPred.BTBHits 746 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_hits 2071 # DTB read hits system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2118 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 29 # DTB write misses +system.cpu.dtb.read_accesses 2121 # DTB read accesses +system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1100 # DTB write accesses -system.cpu.dtb.data_hits 3139 # DTB hits -system.cpu.dtb.data_misses 79 # DTB misses +system.cpu.dtb.write_accesses 1099 # DTB write accesses +system.cpu.dtb.data_hits 3140 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3218 # DTB accesses -system.cpu.itb.fetch_hits 2370 # ITB hits -system.cpu.itb.fetch_misses 39 # ITB misses +system.cpu.dtb.data_accesses 3220 # DTB accesses +system.cpu.itb.fetch_hits 2349 # ITB hits +system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2409 # ITB accesses +system.cpu.itb.fetch_accesses 2387 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,236 +227,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31606 # number of cpu cycles simulated +system.cpu.numCycles 32062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2753 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2653 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2631 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10819 # Type of FU issued -system.cpu.iq.rate 0.342308 # Inst issue rate -system.cpu.iq.fu_busy_cnt 117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10806 # Type of FU issued +system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 87 # number of nop insts executed -system.cpu.iew.exec_refs 3231 # number of memory reference insts executed -system.cpu.iew.exec_branches 1614 # Number of branches executed -system.cpu.iew.exec_stores 1102 # Number of stores executed -system.cpu.iew.exec_rate 0.321679 # Inst execution rate -system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9733 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5145 # num instructions producing a value -system.cpu.iew.wb_consumers 6933 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3233 # number of memory reference insts executed +system.cpu.iew.exec_branches 1613 # Number of branches executed +system.cpu.iew.exec_stores 1101 # Number of stores executed +system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9710 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5134 # num instructions producing a value +system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,70 +467,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25881 # The number of ROB reads -system.cpu.rob.rob_writes 27599 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25928 # The number of ROB reads +system.cpu.rob.rob_writes 27481 # The number of ROB writes +system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads -system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12907 # number of integer regfile reads -system.cpu.int_regfile_writes 7365 # number of integer regfile writes +system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12888 # number of integer regfile reads +system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use -system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits -system.cpu.icache.overall_hits::total 1894 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses -system.cpu.icache.overall_misses::total 476 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits +system.cpu.icache.overall_hits::total 1869 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,109 +539,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 162 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # 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miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51388.090349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -650,68 +650,68 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # 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Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits -system.cpu.dcache.overall_hits::total 2264 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits +system.cpu.dcache.overall_hits::total 2262 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -720,43 +720,43 @@ system.cpu.dcache.demand_misses::cpu.data 528 # n system.cpu.dcache.demand_misses::total 528 # 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miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,30 +776,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 0c67bfe34..6b89534e6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9059000 # Number of ticks simulated -final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9350000 # Number of ticks simulated +final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18337 # Simulator instruction rate (inst/s) -host_op_rate 18335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69572663 # Simulator tick rate (ticks/s) -host_mem_usage 270376 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 146 # Simulator instruction rate (inst/s) +host_op_rate 146 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 570039 # Simulator tick rate (ticks/s) +host_mem_usage 224412 # Number of bytes of host memory used +host_seconds 16.40 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8990500 # Total gap between requests +system.physmem.totGap 9280500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1180771 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests -system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4662000 # Total cycles spent in bank access -system.physmem.avgQLat 4341.07 # Average queueing delay per request -system.physmem.avgBankLat 17139.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25480.78 # Average memory access latency -system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1329022 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totBusLat 1360000 # Total cycles spent in databus access +system.physmem.totBankLat 5183750 # Total cycles spent in bank access +system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgBankLat 19057.90 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.77 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.55 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.84 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 228 # Number of row buffer hits during reads +system.physmem.readRowHits 207 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33053.31 # Average gap between requests -system.cpu.branchPred.lookups 1180 # Number of BP lookups -system.cpu.branchPred.condPredicted 594 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 261 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 235 # Number of BTB hits +system.physmem.avgGap 34119.49 # Average gap between requests +system.cpu.branchPred.lookups 1154 # Number of BP lookups +system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.156328 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 717 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 708 # DTB read hits +system.cpu.dtb.read_misses 28 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 742 # DTB read accesses -system.cpu.dtb.write_hits 359 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 736 # DTB read accesses +system.cpu.dtb.write_hits 357 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 378 # DTB write accesses -system.cpu.dtb.data_hits 1076 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 377 # DTB write accesses +system.cpu.dtb.data_hits 1065 # DTB hits +system.cpu.dtb.data_misses 48 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1120 # DTB accesses -system.cpu.itb.fetch_hits 1063 # ITB hits +system.cpu.dtb.data_accesses 1113 # DTB accesses +system.cpu.itb.fetch_hits 1043 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1093 # ITB accesses +system.cpu.itb.fetch_accesses 1073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -227,237 +227,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18119 # number of cpu cycles simulated +system.cpu.numCycles 18701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1148 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1075 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1056 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4086 # Type of FU issued -system.cpu.iq.rate 0.225509 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4065 # Type of FU issued +system.cpu.iq.rate 0.217368 # Inst issue rate +system.cpu.iq.fu_busy_cnt 46 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 344 # number of nop insts executed -system.cpu.iew.exec_refs 1121 # number of memory reference insts executed -system.cpu.iew.exec_branches 656 # Number of branches executed -system.cpu.iew.exec_stores 378 # Number of stores executed -system.cpu.iew.exec_rate 0.214526 # Inst execution rate -system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3691 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1735 # num instructions producing a value -system.cpu.iew.wb_consumers 2218 # num instructions consuming a value +system.cpu.iew.exec_nop 339 # number of nop insts executed +system.cpu.iew.exec_refs 1114 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 377 # Number of stores executed +system.cpu.iew.exec_rate 0.205978 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3664 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1730 # num instructions producing a value +system.cpu.iew.wb_consumers 2229 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back +system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -468,119 +468,119 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11910 # The number of ROB reads -system.cpu.rob.rob_writes 11291 # The number of ROB writes -system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11838 # The number of ROB reads +system.cpu.rob.rob_writes 11181 # The number of ROB writes +system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4685 # number of integer regfile reads -system.cpu.int_regfile_writes 2864 # number of integer regfile writes +system.cpu.cpi 7.834520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.834520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127640 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127640 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2842 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use -system.cpu.icache.total_refs 813 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 90.926534 # Cycle average of tags in use +system.cpu.icache.total_refs 794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.245989 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits -system.cpu.icache.overall_hits::total 813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 90.926534 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044398 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044398 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 794 # number of overall hits +system.cpu.icache.overall_hits::total 794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses +system.cpu.icache.overall_misses::total 249 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12422499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12422499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12422499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12422499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12422499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.238734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.238734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49889.554217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49889.554217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9626999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9626999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9626999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9626999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9626999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9626999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51481.278075 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51481.278075 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.901566 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.245260 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.656305 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003720 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses @@ -592,17 +592,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9049000 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13026500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9439000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14434500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9439000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14434500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48390.374332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53532.786885 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49655.241935 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55166.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55166.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50141.544118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50141.544118 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50475.935829 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52526.209677 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53068.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53068.014706 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,17 +655,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -677,91 +677,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169184 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169184 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # 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average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49343.750000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54685.185185 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54685.185185 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51585.492228 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51585.492228 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 108 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 108 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -770,30 +770,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3648500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1433500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5082000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5082000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092145 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092145 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.088912 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.088912 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59811.475410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59788.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59788.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index cbe7a8e01..80cf199ee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22763 # Simulator instruction rate (inst/s) -host_op_rate 28403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66199618 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 51480 # Simulator instruction rate (inst/s) +host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153638426 # Simulator tick rate (ticks/s) +host_mem_usage 239936 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -282,50 +282,50 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -347,28 +347,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -404,50 +404,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -475,42 +475,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -523,117 +523,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -654,17 +654,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -687,17 +687,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -723,17 +723,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,109 +745,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -856,30 +856,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index a9f3432ad..13489057c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13354000 # Number of ticks simulated -final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13709000 # Number of ticks simulated +final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20035 # Simulator instruction rate (inst/s) -host_op_rate 24999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58267208 # Simulator tick rate (ticks/s) -host_mem_usage 285296 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 58002 # Simulator instruction rate (inst/s) +host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173086159 # Simulator tick rate (ticks/s) +host_mem_usage 238920 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 25216 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13296500 # Total gap between requests +system.physmem.totGap 13651500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2460894 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests -system.physmem.totBusLat 1576000 # Total cycles spent in databus access -system.physmem.totBankLat 6524000 # Total cycles spent in bank access -system.physmem.avgQLat 6245.92 # Average queueing delay per request -system.physmem.avgBankLat 16558.38 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2508144 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totBusLat 1970000 # Total cycles spent in databus access +system.physmem.totBankLat 7273750 # Total cycles spent in bank access +system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgBankLat 18461.29 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.37 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 319 # Number of row buffer hits during reads +system.physmem.readRowHits 294 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33747.46 # Average gap between requests +system.physmem.avgGap 34648.48 # Average gap between requests system.cpu.branchPred.lookups 2501 # Number of BP lookups system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect @@ -237,50 +237,50 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26709 # number of cpu cycles simulated +system.cpu.numCycles 27419 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2444 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2445 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2245 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename @@ -302,28 +302,28 @@ system.cpu.memDep0.conflictingLoads 37 # Nu system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -359,50 +359,50 @@ system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336516 # Inst issue rate +system.cpu.iq.FU_type_0::total 8986 # Type of FU issued +system.cpu.iq.rate 0.327729 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -430,42 +430,42 @@ system.cpu.iew.predictedTakenIncorrect 109 # Nu system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1443 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1444 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.320604 # Inst execution rate -system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8105 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.312302 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8106 # cumulative count of insts written-back system.cpu.iew.wb_producers 3904 # num instructions producing a value system.cpu.iew.wb_consumers 7842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle +system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -478,117 +478,117 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22955 # The number of ROB reads +system.cpu.rob.rob_reads 23072 # The number of ROB reads system.cpu.rob.rob_writes 23605 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39368 # number of integer regfile reads -system.cpu.int_regfile_writes 8018 # number of integer regfile writes +system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39366 # number of integer regfile reads +system.cpu.int_regfile_writes 8019 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2982 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use -system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use +system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits -system.cpu.icache.overall_hits::total 1597 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits +system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -609,17 +609,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -642,17 +642,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -678,17 +678,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,109 +700,109 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use -system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use +system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits -system.cpu.dcache.overall_hits::total 2373 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits +system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses -system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # 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number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -811,30 +811,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 7f0e6e36f..4baa76c40 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18578000 # Number of ticks simulated -final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19339000 # Number of ticks simulated +final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49489 # Simulator instruction rate (inst/s) -host_op_rate 49481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158085302 # Simulator tick rate (ticks/s) -host_mem_usage 270352 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 100636 # Simulator instruction rate (inst/s) +host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 334460805 # Simulator tick rate (ticks/s) +host_mem_usage 224316 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18503000 # Total gap between requests +system.physmem.totGap 19292000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2354454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests -system.physmem.totBusLat 1820000 # Total cycles spent in databus access -system.physmem.totBankLat 8484000 # Total cycles spent in bank access -system.physmem.avgQLat 5174.62 # Average queueing delay per request -system.physmem.avgBankLat 18646.15 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27820.78 # Average memory access latency -system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2650454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totBusLat 2275000 # Total cycles spent in databus access +system.physmem.totBankLat 9033750 # Total cycles spent in bank access +system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.68 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 11.76 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.72 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.readRowHits 334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40665.93 # Average gap between requests +system.physmem.avgGap 42400.00 # Average gap between requests system.cpu.branchPred.lookups 1154 # Number of BP lookups system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect @@ -213,7 +213,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 37157 # number of cpu cycles simulated +system.cpu.numCycles 38679 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). @@ -235,12 +235,12 @@ system.cpu.execution_unit.executions 3135 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5375 # Number of cycles cpu stages are processed. -system.cpu.activity 14.465646 # Percentage of cycles cpu is active +system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. +system.cpu.activity 13.899015 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -252,36 +252,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use +system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -294,12 +294,12 @@ system.cpu.icache.demand_misses::cpu.inst 346 # n system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses @@ -312,12 +312,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -338,36 +338,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -385,17 +385,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5062000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21184500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16983500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5162000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2560500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7722500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16983500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7722500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24706000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -418,17 +418,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53575.709779 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54815.594059 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50205.882353 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54298.901099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53575.709779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55960.144928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54298.901099 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,17 +448,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12118017 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982594 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16100611 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,27 +470,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45776.942529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39852.997525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.859083 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits @@ -507,14 +507,14 @@ system.cpu.dcache.demand_misses::cpu.data 444 # n system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -531,14 +531,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -563,14 +563,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -579,14 +579,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8a152a960..7feba62df 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16532500 # Number of ticks simulated -final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17026500 # Number of ticks simulated +final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36398 # Simulator instruction rate (inst/s) -host_op_rate 36393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116675957 # Simulator tick rate (ticks/s) -host_mem_usage 271376 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 76348 # Simulator instruction rate (inst/s) +host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 251939378 # Simulator tick rate (ticks/s) +host_mem_usage 226380 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 30592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 478 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30464 # Total number of bytes read from memory +system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16453500 # Total gap between requests +system.physmem.totGap 16967000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476 # Categorize read packet sizes +system.physmem.readPktSize::6 478 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,36 +164,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2530972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests -system.physmem.totBusLat 1904000 # Total cycles spent in databus access -system.physmem.totBankLat 8652000 # Total cycles spent in bank access -system.physmem.avgQLat 5317.17 # Average queueing delay per request -system.physmem.avgBankLat 18176.47 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27493.64 # Average memory access latency -system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2863474 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totBusLat 2390000 # Total cycles spent in databus access +system.physmem.totBankLat 9363750 # Total cycles spent in bank access +system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.04 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.86 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 376 # Number of row buffer hits during reads +system.physmem.readRowHits 351 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34566.18 # Average gap between requests -system.cpu.branchPred.lookups 2120 # Number of BP lookups -system.cpu.branchPred.condPredicted 1453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups -system.cpu.branchPred.BTBHits 517 # Number of BTB hits +system.physmem.avgGap 35495.82 # Average gap between requests +system.cpu.branchPred.lookups 2222 # Number of BP lookups +system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups +system.cpu.branchPred.BTBHits 508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.314355 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -213,235 +213,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 33066 # number of cpu cycles simulated +system.cpu.numCycles 34054 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3037 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3094 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2958 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8209 # Type of FU issued -system.cpu.iq.rate 0.248261 # Inst issue rate -system.cpu.iq.fu_busy_cnt 161 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8325 # Type of FU issued +system.cpu.iq.rate 0.244465 # Inst issue rate +system.cpu.iq.fu_busy_cnt 159 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1512 # number of nop insts executed -system.cpu.iew.exec_refs 3196 # number of memory reference insts executed -system.cpu.iew.exec_branches 1341 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.237374 # Inst execution rate -system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2925 # num instructions producing a value -system.cpu.iew.wb_consumers 4228 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_branches 1355 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.233042 # Inst execution rate +system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7471 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2950 # num instructions producing a value +system.cpu.iew.wb_consumers 4259 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,69 +453,69 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23666 # The number of ROB reads -system.cpu.rob.rob_writes 22238 # The number of ROB writes -system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23973 # The number of ROB reads +system.cpu.rob.rob_writes 22610 # The number of ROB writes +system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10670 # number of integer regfile reads -system.cpu.int_regfile_writes 5185 # number of integer regfile writes +system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads +system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10756 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 147 # number of misc regfile reads +system.cpu.misc_regfile_reads 150 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use -system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use +system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits -system.cpu.icache.overall_hits::total 1502 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits +system.cpu.icache.overall_hits::total 1566 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -523,109 +524,109 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 109 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 109 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 109 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.173422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50165.680473 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50165.680473 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use -system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use +system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits -system.cpu.dcache.overall_hits::total 2420 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits +system.cpu.dcache.overall_hits::total 2424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses -system.cpu.dcache.overall_misses::total 504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9019500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24118499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24118499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24118499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24118499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 2fa72cd37..ccc0289be 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14065500 # Number of ticks simulated -final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 14724500 # Number of ticks simulated +final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44313 # Simulator instruction rate (inst/s) -host_op_rate 44306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107578636 # Simulator tick rate (ticks/s) -host_mem_usage 267272 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 87376 # Simulator instruction rate (inst/s) +host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221965921 # Simulator tick rate (ticks/s) +host_mem_usage 222644 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1569798443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 459564182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2029362625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1569798443 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1569798443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 459564182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2029362625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 28544 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 42 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13958000 # Total gap between requests +system.physmem.totGap 14617000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,34 +164,34 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1923944 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests -system.physmem.totBusLat 1784000 # Total cycles spent in databus access -system.physmem.totBankLat 7378000 # Total cycles spent in bank access -system.physmem.avgQLat 4313.78 # Average queueing delay per request -system.physmem.avgBankLat 16542.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24856.38 # Average memory access latency -system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2286195 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totBusLat 2230000 # Total cycles spent in databus access +system.physmem.totBankLat 8263750 # Total cycles spent in bank access +system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgBankLat 18528.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.68 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 15.14 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.87 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 369 # Number of row buffer hits during reads +system.physmem.readRowHits 338 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31295.96 # Average gap between requests -system.cpu.branchPred.lookups 2247 # Number of BP lookups -system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted +system.physmem.avgGap 32773.54 # Average gap between requests +system.cpu.branchPred.lookups 2226 # Number of BP lookups +system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups -system.cpu.branchPred.BTBHits 602 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 599 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -213,234 +213,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 28132 # number of cpu cycles simulated +system.cpu.numCycles 29450 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9396 80.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 175 1.50% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.51% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.22% 84.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.95% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.13% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.20% 90.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.93% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1049 8.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11663 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079873 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.469856 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7468 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1305 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2099 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 156 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11753 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2083 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7658 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 585 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 451 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1983 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 277 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11310 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1969 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18197 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18142 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8959 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4243 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.768156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.499073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8296 71.13% 71.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1090 9.35% 80.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 795 6.82% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.25% 91.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.00% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 308 2.64% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 133 1.14% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 43 0.37% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.60% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 71 40.80% 45.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 95 54.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5501 61.40% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1805 20.15% 81.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1651 18.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8959 # Type of FU issued -system.cpu.iq.rate 0.318463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29881 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8164 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8907 # Type of FU issued +system.cpu.iq.rate 0.302445 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9099 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 783 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 370 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1829 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 330 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8539 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1683 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 420 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3224 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1541 # Number of stores executed -system.cpu.iew.exec_rate 0.303533 # Inst execution rate -system.cpu.iew.wb_sent 8307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8191 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4222 # num instructions producing a value -system.cpu.iew.wb_consumers 6683 # num instructions consuming a value +system.cpu.iew.exec_refs 3204 # number of memory reference insts executed +system.cpu.iew.exec_branches 1349 # Number of branches executed +system.cpu.iew.exec_stores 1531 # Number of stores executed +system.cpu.iew.exec_rate 0.288353 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8149 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4198 # num instructions producing a value +system.cpu.iew.wb_consumers 6619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.291163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631752 # average fanout of values written-back +system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.330367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8576 78.29% 78.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1000 9.13% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 620 5.66% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 265 2.42% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 172 1.57% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 106 0.97% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 68 0.62% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.41% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,118 +451,118 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21218 # The number of ROB reads -system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16469 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21024 # The number of ROB reads +system.cpu.rob.rob_writes 21246 # The number of ROB writes +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.857044 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.857044 # CPI: Total CPI of All Threads -system.cpu.ipc 0.205887 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.205887 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13537 # number of integer regfile reads -system.cpu.int_regfile_writes 7068 # number of integer regfile writes +system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads +system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13466 # number of integer regfile reads +system.cpu.int_regfile_writes 7036 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use -system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use +system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1375 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1375 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits -system.cpu.icache.overall_hits::total 1375 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits +system.cpu.icache.overall_hits::total 1361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses +system.cpu.icache.overall_misses::total 441 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006062 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -583,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -616,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # 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average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,91 +668,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use -system.cpu.dcache.total_refs 2190 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use +system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.470588 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.407702 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015480 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2190 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2190 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2190 # number of overall hits -system.cpu.dcache.overall_hits::total 2190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5222000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14128997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14128997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits +system.cpu.dcache.overall_hits::total 2181 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses +system.cpu.dcache.overall_misses::total 438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2625 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2625 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2625 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2625 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065864 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -761,30 +761,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 0a19f6727..a586f3039 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16286500 # Number of ticks simulated -final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16783500 # Number of ticks simulated +final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32843 # Simulator instruction rate (inst/s) -host_op_rate 32839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100387600 # Simulator tick rate (ticks/s) -host_mem_usage 278524 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 84096 # Simulator instruction rate (inst/s) +host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 264753473 # Simulator tick rate (ticks/s) +host_mem_usage 230292 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27072 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 62 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16235000 # Total gap between requests +system.physmem.totGap 16708000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2302422 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests -system.physmem.totBusLat 1692000 # Total cycles spent in databus access -system.physmem.totBankLat 7308000 # Total cycles spent in bank access -system.physmem.avgQLat 5443.08 # Average queueing delay per request -system.physmem.avgBankLat 17276.60 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26719.67 # Average memory access latency -system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2673172 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totBusLat 2115000 # Total cycles spent in databus access +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgBankLat 19406.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.39 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.69 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 12.60 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 336 # Number of row buffer hits during reads +system.physmem.readRowHits 300 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 38380.61 # Average gap between requests +system.physmem.avgGap 39498.82 # Average gap between requests system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -195,14 +195,14 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32574 # number of cpu cycles simulated +system.cpu.numCycles 33568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6247 # Number of cycles cpu stages are processed. -system.cpu.activity 19.177872 # Percentage of cycles cpu is active +system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 18.604028 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads -system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads +system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use +system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use system.cpu.icache.total_refs 895 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 362 # n system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -370,17 +370,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,27 +455,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.137936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020541 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020541 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -492,14 +492,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -516,19 +516,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -548,14 +548,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -564,14 +564,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 44632e460..b6a3a3279 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15014000 # Number of ticks simulated -final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15468000 # Number of ticks simulated +final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24822 # Simulator instruction rate (inst/s) -host_op_rate 44962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69258779 # Simulator tick rate (ticks/s) -host_mem_usage 286624 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 31666 # Simulator instruction rate (inst/s) +host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91020367 # Simulator tick rate (ticks/s) +host_mem_usage 241544 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -19,39 +19,39 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28736 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14993500 # Total gap between requests +system.physmem.totGap 15452000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450 # Categorize read packet sizes +system.physmem.readPktSize::6 451 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,266 +164,266 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1656450 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests -system.physmem.totBusLat 1800000 # Total cycles spent in databus access -system.physmem.totBankLat 8568000 # Total cycles spent in bank access -system.physmem.avgQLat 3681.00 # Average queueing delay per request -system.physmem.avgBankLat 19040.00 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26721.00 # Average memory access latency -system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 1899951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totBusLat 2255000 # Total cycles spent in databus access +system.physmem.totBankLat 9006250 # Total cycles spent in bank access +system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgBankLat 19969.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.96 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 14.51 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 352 # Number of row buffer hits during reads +system.physmem.readRowHits 333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33318.89 # Average gap between requests -system.cpu.branchPred.lookups 3018 # Number of BP lookups -system.cpu.branchPred.condPredicted 3018 # Number of conditional branches predicted +system.physmem.avgGap 34261.64 # Average gap between requests +system.cpu.branchPred.lookups 2995 # Number of BP lookups +system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2500 # Number of BTB lookups -system.cpu.branchPred.BTBHits 796 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups +system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.840000 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30029 # number of cpu cycles simulated +system.cpu.numCycles 30937 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 171 0.92% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 265 1.43% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3547 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24452 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3325 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22970 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3523 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25107 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55203 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 55187 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14046 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1757 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20458 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17350 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13877 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.933649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.794423 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1385 7.45% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1043 5.61% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13964 80.48% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1899 10.95% 91.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1483 8.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17350 # Type of FU issued -system.cpu.iq.rate 0.577775 # Inst issue rate -system.cpu.iq.fu_busy_cnt 178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53666 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16004 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17307 # Type of FU issued +system.cpu.iq.rate 0.559427 # Inst issue rate +system.cpu.iq.fu_busy_cnt 175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17520 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20493 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1757 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16426 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3141 # number of memory reference insts executed -system.cpu.iew.exec_branches 1630 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.547005 # Inst execution rate -system.cpu.iew.wb_sent 16198 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16008 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10179 # num instructions producing a value -system.cpu.iew.wb_consumers 15729 # num instructions consuming a value +system.cpu.iew.exec_refs 3145 # number of memory reference insts executed +system.cpu.iew.exec_branches 1625 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.529398 # Inst execution rate +system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15953 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10136 # num instructions producing a value +system.cpu.iew.wb_consumers 15661 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.533085 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647149 # average fanout of values written-back +system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10746 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.581747 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458276 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13224 78.94% 78.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1319 7.87% 86.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 595 3.55% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -436,71 +436,71 @@ system.cpu.commit.int_insts 9652 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 37024 # The number of ROB reads -system.cpu.rob.rob_writes 42843 # The number of ROB writes -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36893 # The number of ROB reads +system.cpu.rob.rob_writes 42622 # The number of ROB writes +system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads -system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28877 # number of integer regfile reads -system.cpu.int_regfile_writes 17233 # number of integer regfile writes +system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28821 # number of integer regfile reads +system.cpu.int_regfile_writes 17168 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7157 # number of misc regfile reads +system.cpu.misc_regfile_reads 7143 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use -system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use +system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits -system.cpu.icache.overall_hits::total 1482 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits +system.cpu.icache.overall_hits::total 1475 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses system.cpu.icache.overall_misses::total 399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -516,36 +516,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 304 system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -553,60 +553,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 72 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses -system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -616,59 +616,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.643836 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.496642 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020385 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020385 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits @@ -677,51 +677,51 @@ system.cpu.dcache.demand_hits::cpu.data 2284 # nu system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits system.cpu.dcache.overall_hits::total 2284 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # 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number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -731,38 +731,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 55 system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 18c747e94..329680740 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19857000 # Number of ticks simulated -final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24473000 # Number of ticks simulated +final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38427 # Simulator instruction rate (inst/s) -host_op_rate 38425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59863252 # Simulator tick rate (ticks/s) -host_mem_usage 271256 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 4068 # Simulator instruction rate (inst/s) +host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7811345 # Simulator tick rate (ticks/s) +host_mem_usage 226312 # Number of bytes of host memory used +host_seconds 3.13 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory +system.physmem.bytes_read::total 62080 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 972 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2004733847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1128065670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3132799517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2004733847 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2004733847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1128065670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3132799517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 972 # Total number of read requests seen +system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 970 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 970 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 972 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62208 # Total number of bytes read from memory +system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62080 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 122 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 76 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19816500 # Total gap between requests +system.physmem.totGap 24326500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 972 # Categorize read packet sizes +system.physmem.readPktSize::6 970 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,56 +164,56 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 11651972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 34145972 # Sum of mem lat for all requests -system.physmem.totBusLat 3888000 # Total cycles spent in databus access -system.physmem.totBankLat 18606000 # Total cycles spent in bank access -system.physmem.avgQLat 11987.63 # Average queueing delay per request -system.physmem.avgBankLat 19141.98 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35129.60 # Average memory access latency -system.physmem.avgRdBW 3132.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 22646466 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totBusLat 4850000 # Total cycles spent in databus access +system.physmem.totBankLat 25973750 # Total cycles spent in bank access +system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgBankLat 26777.06 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3132.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.58 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.72 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 19.82 # Data bus utilization in percentage +system.physmem.avgRdQLen 2.18 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 733 # Number of row buffer hits during reads +system.physmem.readRowHits 450 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 20387.35 # Average gap between requests -system.cpu.branchPred.lookups 6348 # Number of BP lookups -system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.physmem.avgGap 25078.87 # Average gap between requests +system.cpu.branchPred.lookups 6101 # Number of BP lookups +system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1023 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4359 # DTB read hits -system.cpu.dtb.read_misses 96 # DTB read misses +system.cpu.dtb.read_hits 4461 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4455 # DTB read accesses -system.cpu.dtb.write_hits 2014 # DTB write hits -system.cpu.dtb.write_misses 72 # DTB write misses +system.cpu.dtb.read_accesses 4561 # DTB read accesses +system.cpu.dtb.write_hits 2022 # DTB write hits +system.cpu.dtb.write_misses 83 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2086 # DTB write accesses -system.cpu.dtb.data_hits 6373 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2105 # DTB write accesses +system.cpu.dtb.data_hits 6483 # DTB hits +system.cpu.dtb.data_misses 183 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6541 # DTB accesses -system.cpu.itb.fetch_hits 5250 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 6666 # DTB accesses +system.cpu.itb.fetch_hits 4836 # ITB hits +system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5307 # ITB accesses +system.cpu.itb.fetch_accesses 4885 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -228,350 +228,351 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 39715 # number of cpu cycles simulated +system.cpu.numCycles 48947 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1772 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5994 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1779 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5250 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 858 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.345161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.748208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20301 77.20% 77.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 545 2.07% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 388 1.48% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 414 1.57% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 431 1.64% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 401 1.53% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 440 1.67% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 561 2.13% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2814 10.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.159839 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.890621 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37128 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5161 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 465 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2623 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 533 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 326 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31237 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 663 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2623 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3807 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1133 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28851 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35513 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4956 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4731 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12529 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 6010 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2907 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2775 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1297 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25429 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 70 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21088 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11668 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7282 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 36 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.801978 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.371425 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17201 65.42% 65.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3228 12.28% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2604 9.90% 87.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1566 5.96% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 907 3.45% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 493 1.87% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 226 0.86% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.21% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 117 60.31% 65.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66 34.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6973 65.93% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2492 23.56% 89.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 10.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10576 # Type of FU issued +system.cpu.iq.FU_type_0::total 10607 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7011 66.70% 66.71% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.74% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2403 22.86% 89.60% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1093 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10512 # Type of FU issued +system.cpu.iq.FU_type_1::total 10268 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13984 66.31% 66.33% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 66.34% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 66.34% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4895 23.21% 89.57% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2199 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21088 # Type of FU issued -system.cpu.iq.rate 0.530983 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004458 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004742 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009200 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 68733 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37173 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18381 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.FU_type::total 20875 # Type of FU issued +system.cpu.iq.rate 0.426482 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21256 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1724 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 355 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1592 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 432 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 238 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2623 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5682 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2660 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 70 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 31 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 235 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1060 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1295 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 19629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2279 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2190 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4469 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1459 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 110 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::0 98 # number of nop insts executed +system.cpu.iew.exec_nop::1 81 # number of nop insts executed system.cpu.iew.exec_nop::total 179 # number of nop insts executed -system.cpu.iew.exec_refs::0 3341 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3226 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6567 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1545 # Number of branches executed -system.cpu.iew.exec_branches::1 1563 # Number of branches executed -system.cpu.iew.exec_branches::total 3108 # Number of branches executed -system.cpu.iew.exec_stores::0 1062 # Number of stores executed -system.cpu.iew.exec_stores::1 1036 # Number of stores executed -system.cpu.iew.exec_stores::total 2098 # Number of stores executed -system.cpu.iew.exec_rate 0.494247 # Inst execution rate -system.cpu.iew.wb_sent::0 9363 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9308 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18671 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9223 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9178 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18401 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4724 # num instructions producing a value -system.cpu.iew.wb_producers::1 4736 # num instructions producing a value -system.cpu.iew.wb_producers::total 9460 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6156 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6184 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12340 # num instructions consuming a value +system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1527 # Number of branches executed +system.cpu.iew.exec_branches::1 1521 # Number of branches executed +system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_stores::0 1066 # Number of stores executed +system.cpu.iew.exec_stores::1 1051 # Number of stores executed +system.cpu.iew.exec_stores::total 2117 # Number of stores executed +system.cpu.iew.exec_rate 0.401046 # Inst execution rate +system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4725 # num instructions producing a value +system.cpu.iew.wb_producers::1 4632 # num instructions producing a value +system.cpu.iew.wb_producers::total 9357 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.232230 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.231097 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.463326 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.767381 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.765847 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.766613 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12926 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1134 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487413 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275738 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20568 78.45% 78.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2989 11.40% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1062 4.05% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 514 1.96% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 342 1.30% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 0.91% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 201 0.77% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.27% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26218 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -602,191 +603,191 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 123093 # The number of ROB reads -system.cpu.rob.rob_writes 54044 # The number of ROB writes -system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 126869 # The number of ROB reads +system.cpu.rob.rob_writes 53172 # The number of ROB writes +system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 6.232737 # CPI: Cycles Per Instruction -system.cpu.cpi::1 6.231759 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.116124 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.160443 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.160468 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.320911 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24691 # number of integer regfile reads -system.cpu.int_regfile_writes 13868 # number of integer regfile writes +system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24701 # number of integer regfile reads +system.cpu.int_regfile_writes 13755 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 7 # number of replacements +system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 7 # number of replacements -system.cpu.icache.tagsinuse 306.891389 # Cycle average of tags in use -system.cpu.icache.total_refs 4214 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.742400 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use +system.cpu.icache.total_refs 3780 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 306.891389 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.149849 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.149849 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4214 # number of overall hits -system.cpu.icache.overall_hits::total 4214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses -system.cpu.icache.overall_misses::total 1030 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 56718997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 56718997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 56718997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 56718997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 56718997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196415 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196415 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196415 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196415 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196415 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.987379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55066.987379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.987379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55066.987379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2360 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits +system.cpu.icache.overall_hits::total 3780 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses +system.cpu.icache.overall_misses::total 1049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78577996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78577996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78577996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217229 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217229 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217229 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217229 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217229 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.217229 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74907.527169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74907.527169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74907.527169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74907.527169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3158 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.848485 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38021997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 38021997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38021997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 38021997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38021997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 38021997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119184 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.119184 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119184 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.119184 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60835.195200 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60835.195200 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60835.195200 # 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number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48453998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48453998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48453998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48453998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48453998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48453998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129219 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits -system.cpu.dcache.overall_hits::total 4387 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses -system.cpu.dcache.overall_misses::total 1035 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4338 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4338 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4338 # number of overall hits +system.cpu.dcache.overall_hits::total 4338 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 320 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 320 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1028 # number of overall misses +system.cpu.dcache.overall_misses::total 1028 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53389967 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53389967 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 79612467 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 79612467 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 79612467 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 79612467 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3636 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3636 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5366 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5366 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.088009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.191577 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191577 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191577 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191577 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81945.312500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75409.557910 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3353b4aad..3cd467a4b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22838500 # Number of ticks simulated -final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23146500 # Number of ticks simulated +final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21741 # Simulator instruction rate (inst/s) -host_op_rate 21740 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32746771 # Simulator tick rate (ticks/s) -host_mem_usage 278448 # Number of bytes of host memory used -host_seconds 0.70 # Real time elapsed on the host +host_inst_rate 62448 # Simulator instruction rate (inst/s) +host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95315643 # Simulator tick rate (ticks/s) +host_mem_usage 230224 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 835081113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 386715415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1221796528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 835081113 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 835081113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 386715415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1221796528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 27904 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 76 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 22805000 # Total gap between requests +system.physmem.totGap 23113000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,41 +164,41 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2325934 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests -system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7266000 # Total cycles spent in bank access -system.physmem.avgQLat 5334.71 # Average queueing delay per request -system.physmem.avgBankLat 16665.14 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25999.85 # Average memory access latency -system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 2156686 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totBusLat 2180000 # Total cycles spent in databus access +system.physmem.totBankLat 7727500 # Total cycles spent in bank access +system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgBankLat 17723.62 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.64 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.50 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 9.42 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 359 # Number of row buffer hits during reads +system.physmem.readRowHits 339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52305.05 # Average gap between requests -system.cpu.branchPred.lookups 5147 # Number of BP lookups +system.physmem.avgGap 53011.47 # Average gap between requests +system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2720 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 45678 # number of cpu cycles simulated +system.cpu.numCycles 46294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File @@ -217,12 +217,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17569 # Number of cycles cpu stages are processed. -system.cpu.activity 38.462717 # Percentage of cycles cpu is active +system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. +system.cpu.activity 37.948762 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -234,36 +234,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.012663 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.012663 # CPI: Total CPI of All Threads -system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads +system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use +system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -276,12 +276,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -294,12 +294,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49523.622047 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,36 +320,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15157500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15157500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15157500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15157500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 204.083022 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.933146 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.149876 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -367,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14874500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17720500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14874500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -400,17 +400,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49747.491639 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53698.113208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50342.329545 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50678.489703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49747.491639 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52695.652174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50678.489703 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,17 +430,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11105481 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13287049 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11105481 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16669113 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11105481 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16669113 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,27 +452,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37142.076923 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37747.298295 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.519804 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.519804 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -491,14 +491,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3301000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3301000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22564500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22564500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22564500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -517,19 +517,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56913.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56913.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45648.104265 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45648.104265 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47009.375000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47009.375000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4514000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7414500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7414500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7414500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -565,14 +565,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54726.415094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53105.882353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 368690106..cd86d7e47 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23180500 # Number of ticks simulated -final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23775500 # Number of ticks simulated +final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20805 # Simulator instruction rate (inst/s) -host_op_rate 20805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33406458 # Simulator tick rate (ticks/s) -host_mem_usage 278444 # Number of bytes of host memory used -host_seconds 0.69 # Real time elapsed on the host +host_inst_rate 69212 # Simulator instruction rate (inst/s) +host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113962469 # Simulator tick rate (ticks/s) +host_mem_usage 232268 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30912 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 4 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 80 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23120500 # Total gap between requests +system.physmem.totGap 23715500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,121 +164,121 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3040483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests -system.physmem.totBusLat 1932000 # Total cycles spent in databus access -system.physmem.totBankLat 8008000 # Total cycles spent in bank access -system.physmem.avgQLat 6295.00 # Average queueing delay per request -system.physmem.avgBankLat 16579.71 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26874.71 # Average memory access latency -system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4632480 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totBusLat 2415000 # Total cycles spent in databus access +system.physmem.totBankLat 8566250 # Total cycles spent in bank access +system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgBankLat 17735.51 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.56 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 10.16 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.66 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 369 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47868.53 # Average gap between requests -system.cpu.branchPred.lookups 6759 # Number of BP lookups -system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted +system.physmem.avgGap 49100.41 # Average gap between requests +system.cpu.branchPred.lookups 6770 # Number of BP lookups +system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2448 # Number of BTB hits +system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2447 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46362 # number of cpu cycles simulated +system.cpu.numCycles 47552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8405 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8008 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 128 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24166 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49969 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available @@ -314,69 +314,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21285 # Type of FU issued -system.cpu.iq.rate 0.459104 # Inst issue rate +system.cpu.iq.FU_type_0::total 21278 # Type of FU issued +system.cpu.iq.rate 0.447468 # Inst issue rate system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -384,43 +384,43 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1139 # number of nop insts executed -system.cpu.iew.exec_refs 5276 # number of memory reference insts executed -system.cpu.iew.exec_branches 4247 # Number of branches executed -system.cpu.iew.exec_stores 2055 # Number of stores executed -system.cpu.iew.exec_rate 0.435853 # Inst execution rate -system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit +system.cpu.iew.exec_nop 1136 # number of nop insts executed +system.cpu.iew.exec_refs 5272 # number of memory reference insts executed +system.cpu.iew.exec_branches 4246 # Number of branches executed +system.cpu.iew.exec_stores 2053 # Number of stores executed +system.cpu.iew.exec_rate 0.424882 # Inst execution rate +system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit system.cpu.iew.wb_count 19647 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9210 # num instructions producing a value -system.cpu.iew.wb_consumers 11373 # num instructions consuming a value +system.cpu.iew.wb_producers 9208 # num instructions producing a value +system.cpu.iew.wb_consumers 11364 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 324 1.06% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.21% 99.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,66 +433,66 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54162 # The number of ROB reads -system.cpu.rob.rob_writes 50836 # The number of ROB writes +system.cpu.rob.rob_reads 54359 # The number of ROB reads +system.cpu.rob.rob_writes 50813 # The number of ROB writes system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads -system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32290 # number of integer regfile reads +system.cpu.cpi 3.293987 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads +system.cpu.ipc 0.303583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32289 # number of integer regfile reads system.cpu.int_regfile_writes 17967 # number of integer regfile writes -system.cpu.misc_regfile_reads 6967 # number of misc regfile reads +system.cpu.misc_regfile_reads 6962 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use -system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 190.534927 # Cycle average of tags in use +system.cpu.icache.total_refs 4850 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.349112 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.093489 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4845 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4845 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4845 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4845 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4845 # number of overall hits -system.cpu.icache.overall_hits::total 4845 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses -system.cpu.icache.overall_misses::total 493 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23383000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23383000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23383000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5338 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5338 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5338 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5338 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5338 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092357 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092357 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092357 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092357 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092357 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47430.020284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47430.020284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47430.020284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47430.020284 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 190.534927 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093035 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.093035 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4850 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4850 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4850 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4850 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4850 # number of overall hits +system.cpu.icache.overall_hits::total 4850 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 491 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 491 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 491 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 491 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 491 # number of overall misses +system.cpu.icache.overall_misses::total 491 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24328000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24328000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24328000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24328000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24328000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5341 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5341 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5341 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5341 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5341 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49547.861507 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49547.861507 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49547.861507 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49547.861507 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,48 +501,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 155 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 155 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 155 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 155 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 153 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17616000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17616000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17616000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17616000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063284 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063284 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063284 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52118.343195 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 225.767373 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006890 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_misses::total 483 # nu system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16755500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20527500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4421500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16755500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8193500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24949000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16755500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8193500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24949000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17258000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4829500 # 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number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -593,17 +593,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995876 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49867.559524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58937.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51318.750000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53271.084337 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51363.095238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75460.937500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55218.750000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62174.698795 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56414.078675 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51363.095238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67959.183673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56414.078675 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,17 +623,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18906136 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,95 +645,95 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37288.726190 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46563.468750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38772.685000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40928.457831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37288.726190 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43381.795918 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39143.138716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.943036 # Cycle average of tags in use -system.cpu.dcache.total_refs 4019 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use +system.cpu.dcache.total_refs 4017 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.340136 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.326531 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.943036 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 99.563734 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024308 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2978 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits -system.cpu.dcache.overall_hits::total 4013 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4011 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4011 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4011 # number of overall hits +system.cpu.dcache.overall_hits::total 4011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6943000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6943000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19544474 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19544474 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26487474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26487474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26487474 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3110 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses +system.cpu.dcache.overall_misses::total 540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8999000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8999000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21053474 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21053474 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30052474 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30052474 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30052474 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3109 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3109 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041801 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041801 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4551 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4551 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042136 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118409 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118409 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118409 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118409 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53407.692308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53407.692308 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47786 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49141.881262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49141.881262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.118655 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118655 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118655 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118655 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68694.656489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68694.656489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51475.486553 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51475.486553 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55652.729630 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55652.729630 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 429 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.321429 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -742,30 +742,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3f4fe5ffb..3dd8cecd5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,87 +1,87 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104832500 # Number of ticks simulated -final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000106 # Number of seconds simulated +sim_ticks 105801500 # Number of ticks simulated +final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81452 # Simulator instruction rate (inst/s) -host_op_rate 81452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8250764 # Simulator tick rate (ticks/s) -host_mem_usage 293492 # Number of bytes of host memory used -host_seconds 12.71 # Real time elapsed on the host -sim_insts 1034907 # Number of instructions simulated -sim_ops 1034907 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory +host_inst_rate 99938 # Simulator instruction rate (inst/s) +host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10207562 # Simulator tick rate (ticks/s) +host_mem_usage 247464 # Number of bytes of host memory used +host_seconds 10.37 # Real time elapsed on the host +sim_insts 1035849 # Number of instructions simulated +sim_ops 1035849 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28416 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 81 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 658 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 659 # Total number of read requests seen +system.physmem.num_reads::total 660 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 42112 # Total number of bytes read from memory +system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 42112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 72 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 19 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 53 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 60 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 78 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 44 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -100,14 +100,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 104804500 # Total gap between requests +system.physmem.totGap 105773500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 659 # Categorize read packet sizes +system.physmem.readPktSize::6 661 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,14 +125,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 72 # categorize neither packet sizes +system.physmem.neitherpktsize::6 71 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -194,336 +194,336 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2976655 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests -system.physmem.totBusLat 2636000 # Total cycles spent in databus access -system.physmem.totBankLat 12138000 # Total cycles spent in bank access -system.physmem.avgQLat 4516.93 # Average queueing delay per request -system.physmem.avgBankLat 18418.82 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26935.74 # Average memory access latency -system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s +system.physmem.totQLat 4077160 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totBusLat 3305000 # Total cycles spent in databus access +system.physmem.totBankLat 13310000 # Total cycles spent in bank access +system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgBankLat 20136.16 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 506 # Number of row buffer hits during reads +system.physmem.readRowHits 465 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads +system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 159035.66 # Average gap between requests -system.cpu0.branchPred.lookups 82004 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits +system.physmem.avgGap 160020.42 # Average gap between requests +system.cpu0.branchPred.lookups 82232 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 209666 # number of cpu cycles simulated +system.cpu0.numCycles 211604 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 483730 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 329027 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 958899 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 958899 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 315995 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.66% 49.11% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued -system.cpu0.iq.rate 1.905664 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued +system.cpu0.iq.rate 1.891623 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2133 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1389 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2438 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 389 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 478542 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 300 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 153720 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77689 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 806 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 35 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75469 # number of nop insts executed -system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79152 # Number of branches executed -system.cpu0.iew.exec_stores 77032 # Number of stores executed -system.cpu0.iew.exec_rate 1.900537 # Inst execution rate -system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 235728 # num instructions producing a value -system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value +system.cpu0.iew.exec_nop 75651 # number of nop insts executed +system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79264 # Number of branches executed +system.cpu0.iew.exec_stores 77169 # Number of stores executed +system.cpu0.iew.exec_rate 1.886439 # Inst execution rate +system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 236156 # num instructions producing a value +system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 466344 # Number of instructions committed -system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 467088 # Number of instructions committed +system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 227887 # Number of memory references committed -system.cpu0.commit.loads 151587 # Number of loads committed +system.cpu0.commit.refs 228259 # Number of memory references committed +system.cpu0.commit.loads 151835 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78187 # Number of branches committed +system.cpu0.commit.branches 78311 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 314326 # Number of committed integer instructions. +system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 667504 # The number of ROB reads -system.cpu0.rob.rob_writes 959472 # The number of ROB writes -system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 391341 # Number of Instructions Simulated -system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated -system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 712766 # number of integer regfile reads -system.cpu0.int_regfile_writes 321389 # number of integer regfile writes +system.cpu0.rob.rob_reads 669667 # The number of ROB reads +system.cpu0.rob.rob_writes 961765 # The number of ROB writes +system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 391961 # Number of Instructions Simulated +system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated +system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 714059 # number of integer regfile reads +system.cpu0.int_regfile_writes 321926 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads +system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use -system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. +system.cpu0.icache.replacements 298 # number of replacements +system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use +system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5129 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5129 # number of overall hits -system.cpu0.icache.overall_hits::total 5129 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 742 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 742 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 742 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses -system.cpu0.icache.overall_misses::total 742 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5871 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5871 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5871 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.126384 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits +system.cpu0.icache.overall_hits::total 5162 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses +system.cpu0.icache.overall_misses::total 744 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,468 +538,469 @@ system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35855.084746 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35855.084746 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 35855.084746 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits -system.cpu0.dcache.overall_hits::total 153639 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 550 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits +system.cpu0.dcache.overall_hits::total 153944 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1018 # number of overall misses +system.cpu0.dcache.overall_misses::total 1018 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11909000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24675495 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 605500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 605500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36584495 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36584495 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36584495 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006602 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006602 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006569 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 384 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 384 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 661 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 661 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 661 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 194 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002328 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52905 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits +system.cpu1.branchPred.lookups 58098 # Number of BP lookups +system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 174086 # number of cpu cycles simulated +system.cpu1.numCycles 174790 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 68 23.05% 28.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued -system.cpu1.iq.rate 1.404111 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued +system.cpu1.iq.rate 1.564203 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1432 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40453 # number of nop insts executed -system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49718 # Number of branches executed -system.cpu1.iew.exec_stores 39064 # Number of stores executed -system.cpu1.iew.exec_rate 1.397453 # Inst execution rate -system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 138076 # num instructions producing a value -system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value +system.cpu1.iew.exec_nop 45600 # number of nop insts executed +system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed +system.cpu1.iew.exec_branches 54914 # Number of branches executed +system.cpu1.iew.exec_stores 45718 # Number of stores executed +system.cpu1.iew.exec_rate 1.557349 # Inst execution rate +system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 156621 # num instructions producing a value +system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 276703 # Number of instructions committed -system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 310743 # Number of instructions committed +system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 119194 # Number of memory references committed -system.cpu1.commit.loads 80803 # Number of loads committed -system.cpu1.commit.membars 4532 # Number of memory barriers committed -system.cpu1.commit.branches 48886 # Number of branches committed +system.cpu1.commit.refs 137689 # Number of memory references committed +system.cpu1.commit.loads 92644 # Number of loads committed +system.cpu1.commit.membars 3055 # Number of memory barriers committed +system.cpu1.commit.branches 54067 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. +system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 448873 # The number of ROB reads -system.cpu1.rob.rob_writes 580482 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 232494 # Number of Instructions Simulated -system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated -system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 422524 # number of integer regfile reads -system.cpu1.int_regfile_writes 197153 # number of integer regfile writes +system.cpu1.rob.rob_reads 483263 # The number of ROB reads +system.cpu1.rob.rob_writes 648465 # The number of ROB writes +system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 262828 # Number of Instructions Simulated +system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated +system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 478110 # number of integer regfile reads +system.cpu1.int_regfile_writes 222397 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads +system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use -system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use +system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 18178 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 18178 # number of overall hits -system.cpu1.icache.overall_hits::total 18178 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits +system.cpu1.icache.overall_hits::total 15102 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 18660 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 18660 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 18660 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1020,94 +1021,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # 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Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 85442 # 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number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 52421 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 44839 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 44839 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 97260 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 97260 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 97260 # number of overall hits +system.cpu1.dcache.overall_hits::total 97260 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 438 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 141 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # 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number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 97839 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 97839 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008286 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003135 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005918 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005918 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005918 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005918 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1116,365 +1117,365 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 252 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 252 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 284 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 284 # 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number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.791045 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003024 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 43658 # Number of BP lookups -system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits +system.cpu2.branchPred.lookups 45099 # Number of BP lookups +system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 173761 # number of cpu cycles simulated +system.cpu2.numCycles 174459 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 732 0.43% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24119 14.02% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1119 0.65% 97.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 764 0.44% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 231751 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 158064 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 425055 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 425055 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145196 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12868 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1106 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 17601 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61347 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27349 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 30218 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22307 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 186544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3303 1.92% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1178 0.68% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96218 50.38% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 68109 35.66% 86.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued -system.cpu2.iq.rate 1.099165 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued +system.cpu2.iq.rate 1.143380 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191279 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22028 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2518 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1460 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 904 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226591 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 328 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61347 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27349 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1066 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 31084 # number of nop insts executed -system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40244 # Number of branches executed -system.cpu2.iew.exec_stores 26584 # Number of stores executed -system.cpu2.iew.exec_rate 1.092414 # Inst execution rate -system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 103581 # num instructions producing a value -system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value +system.cpu2.iew.exec_nop 32635 # number of nop insts executed +system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed +system.cpu2.iew.exec_branches 41831 # Number of branches executed +system.cpu2.iew.exec_stores 28461 # Number of stores executed +system.cpu2.iew.exec_rate 1.136726 # Inst execution rate +system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 108943 # num instructions producing a value +system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1555 0.95% 84.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22612 13.83% 98.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 481 0.29% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1011 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213870 # Number of instructions committed -system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 223981 # Number of instructions committed +system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84718 # Number of memory references committed -system.cpu2.commit.loads 58829 # Number of loads committed -system.cpu2.commit.membars 7592 # Number of memory barriers committed -system.cpu2.commit.branches 39438 # Number of branches committed +system.cpu2.commit.refs 90122 # Number of memory references committed +system.cpu2.commit.loads 62324 # Number of loads committed +system.cpu2.commit.membars 7244 # Number of memory barriers committed +system.cpu2.commit.branches 41003 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146274 # Number of committed integer instructions. +system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 388660 # The number of ROB reads -system.cpu2.rob.rob_writes 455572 # The number of ROB writes -system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176057 # Number of Instructions Simulated -system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated -system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 319023 # number of integer regfile reads -system.cpu2.int_regfile_writes 150022 # number of integer regfile writes +system.cpu2.rob.rob_reads 398976 # The number of ROB reads +system.cpu2.rob.rob_writes 475157 # The number of ROB writes +system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 184944 # Number of Instructions Simulated +system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated +system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 335090 # number of integer regfile reads +system.cpu2.int_regfile_writes 157371 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads +system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use -system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use +system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 24566 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 24566 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 24566 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 24566 # number of overall hits -system.cpu2.icache.overall_hits::total 24566 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 475 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 475 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses -system.cpu2.icache.overall_misses::total 475 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 25041 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 25041 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 25041 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.018969 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits +system.cpu2.icache.overall_hits::total 23791 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses +system.cpu2.icache.overall_misses::total 478 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,106 +1484,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 46 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 46 # 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number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use -system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37788 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25681 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25681 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63469 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63469 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63469 # 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number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # 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miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.786667 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits +system.cpu2.dcache.overall_hits::total 66937 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses +system.cpu2.dcache.overall_misses::total 540 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1591,365 +1592,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 227 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 32 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 259 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 259 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003913 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.786667 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 53689 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits +system.cpu3.branchPred.lookups 47073 # Number of BP lookups +system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 173451 # number of cpu cycles simulated +system.cpu3.numCycles 174149 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 66 23.00% 26.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued -system.cpu3.iq.rate 1.425578 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued +system.cpu3.iq.rate 1.206438 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41144 # number of nop insts executed -system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50378 # Number of branches executed -system.cpu3.iew.exec_stores 39506 # Number of stores executed -system.cpu3.iew.exec_rate 1.418798 # Inst execution rate -system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 139611 # num instructions producing a value -system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value +system.cpu3.iew.exec_nop 34512 # number of nop insts executed +system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43690 # Number of branches executed +system.cpu3.iew.exec_stores 30979 # Number of stores executed +system.cpu3.iew.exec_rate 1.199743 # Inst execution rate +system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 115832 # num instructions producing a value +system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280126 # Number of instructions committed -system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236445 # Number of instructions committed +system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 120655 # Number of memory references committed -system.cpu3.commit.loads 81860 # Number of loads committed -system.cpu3.commit.membars 4779 # Number of memory barriers committed -system.cpu3.commit.branches 49541 # Number of branches committed +system.cpu3.commit.refs 96940 # Number of memory references committed +system.cpu3.commit.loads 66666 # Number of loads committed +system.cpu3.commit.membars 6656 # Number of memory barriers committed +system.cpu3.commit.branches 42889 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. +system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 454770 # The number of ROB reads -system.cpu3.rob.rob_writes 587696 # The number of ROB writes -system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 235015 # Number of Instructions Simulated -system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated -system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 427046 # number of integer regfile reads -system.cpu3.int_regfile_writes 198986 # number of integer regfile writes +system.cpu3.rob.rob_reads 411444 # The number of ROB reads +system.cpu3.rob.rob_writes 500477 # The number of ROB writes +system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196116 # Number of Instructions Simulated +system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated +system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355696 # number of integer regfile reads +system.cpu3.int_regfile_writes 166589 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use -system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use +system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 18731 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 18731 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 18731 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 18731 # number of overall hits -system.cpu3.icache.overall_hits::total 18731 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 474 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 474 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses -system.cpu3.icache.overall_misses::total 474 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19205 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19205 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19205 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.024681 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits +system.cpu3.icache.overall_hits::total 22614 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses +system.cpu3.icache.overall_misses::total 477 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1958,106 +1959,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 428 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # 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number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4992500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4992500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4992500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.018579 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018579 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.018579 # 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Cycle average of tags in use -system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 24.557568 # Cycle average of tags in use +system.cpu3.dcache.total_refs 36284 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1295.857143 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # 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Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.047964 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41265 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41265 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30070 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30070 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 71335 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 71335 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 71335 # number of overall hits +system.cpu3.dcache.overall_hits::total 71335 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 376 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 376 # 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number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71841 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71841 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71841 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71841 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009030 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004305 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797297 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007043 # 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average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14666.007905 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14666.007905 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2066,288 +2067,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 273 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 273 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # 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average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9244.274809 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9244.274809 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 218 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 30 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 248 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 100 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 258 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 258 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 258 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1328000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1243000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 428000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2571000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2571000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003794 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003311 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797297 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003591 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003591 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8405.063291 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12430 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7254.237288 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.291959 # Cycle average of tags in use -system.l2c.total_refs 1448 # Total number of references to valid blocks. -system.l2c.sampled_refs 525 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. +system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.total_refs 1445 # Total number of references to valid blocks. +system.l2c.sampled_refs 527 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000969 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004422 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000942 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000035 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000067 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 418 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 424 # 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average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index eb01eb1c6..e7866c92f 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 18434818132 # Simulator tick rate (ticks/s) -host_mem_usage 219256 # Number of bytes of host memory used -host_seconds 5.42 # Real time elapsed on the host +host_tick_rate 29045358432 # Simulator tick rate (ticks/s) +host_mem_usage 222412 # Number of bytes of host memory used +host_seconds 3.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -25,21 +25,21 @@ system.physmem.bytesConsumedWr 0 # by system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 211200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 210200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -86,18 +86,18 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 3267797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -152,25 +152,25 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2980562702 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 63351670702 # Sum of mem lat for all requests -system.physmem.totBusLat 13333600000 # Total cycles spent in databus access -system.physmem.totBankLat 47037508000 # Total cycles spent in bank access -system.physmem.avgQLat 894.15 # Average queueing delay per request -system.physmem.avgBankLat 14110.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19005.12 # Average memory access latency +system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totBusLat 16667000000 # Total cycles spent in databus access +system.physmem.totBankLat 46722610000 # Total cycles spent in bank access +system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgBankLat 14016.50 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 20851.17 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 13.33 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 16.67 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.70 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3281300 # Number of row buffer hits during reads +system.physmem.readRowHits 3229200 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 98.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 29999.40 # Average gap between requests system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets @@ -278,20 +278,20 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 19061.873685 # Read request-response latency -system.monitor.readLatencyHist::gmean 18381.352509 # Read request-response latency -system.monitor.readLatencyHist::stdev 11230.520439 # Read request-response latency -system.monitor.readLatencyHist::0-32767 3267631 98.03% 98.03% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 52364 1.57% 99.60% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 2680 0.08% 99.68% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 2415 0.07% 99.75% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 2133 0.06% 99.81% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 1602 0.05% 99.86% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 1620 0.05% 99.91% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 1066 0.03% 99.94% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 802 0.02% 99.97% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 812 0.02% 99.99% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 274 0.01% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency +system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency |