diff options
| -rw-r--r-- | SConscript | 1 | ||||
| -rw-r--r-- | mem/physical.hh | 4 | ||||
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 2 |
3 files changed, 3 insertions, 4 deletions
diff --git a/SConscript b/SConscript index 078b1e831..1c13a9307 100644 --- a/SConscript +++ b/SConscript @@ -91,6 +91,7 @@ base_sources = Split(''' cpu/static_inst.cc cpu/sampler/sampler.cc + mem/memory.cc mem/page_table.cc mem/physical.cc mem/port.cc diff --git a/mem/physical.hh b/mem/physical.hh index fb2d0d743..90515d7d1 100644 --- a/mem/physical.hh +++ b/mem/physical.hh @@ -70,9 +70,9 @@ class PhysicalMemory : public Memory std::map<std::string, MemoryPort*> memoryPortList; - Port * PhysicalMemory::getPort(const char *if_name); + virtual Port * getPort(const char *if_name); - Port * addPort(std::string portName); + virtual Port * addPort(std::string portName); int numPorts; diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index fac452285..e5e43022f 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -2,8 +2,6 @@ from m5 import * class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB("Data TLB") |