1068 files changed, 2105 insertions, 3213 deletions

diff --git a/SConstruct b/SConstruct
index 0630cbd79..4ea8ad788 100755
--- a/SConstruct
+++ b/SConstruct
@@ -794,7 +794,6 @@ all_isa_list.sort()
 
 sticky_vars.AddVariables(
     EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
-    BoolVariable('FULL_SYSTEM', 'Full-system support', False),
     ListVariable('CPU_MODELS', 'CPU models',
                  sorted(n for n,m in CpuModel.dict.iteritems() if m.default),
                  sorted(CpuModel.list)),
@@ -818,10 +817,9 @@ sticky_vars.AddVariables(
     )
 
 # These variables get exported to #defines in config/*.hh (see src/SConscript).
-export_vars += ['FULL_SYSTEM', 'USE_FENV',
-                'NO_FAST_ALLOC', 'FORCE_FAST_ALLOC', 'FAST_ALLOC_STATS',
-                'SS_COMPATIBLE_FP', 'USE_CHECKER', 'TARGET_ISA', 'CP_ANNOTATE',
-                'USE_POSIX_CLOCK' ]
+export_vars += ['USE_FENV', 'NO_FAST_ALLOC', 'FORCE_FAST_ALLOC',
+                'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', 'USE_CHECKER',
+                'TARGET_ISA', 'CP_ANNOTATE', 'USE_POSIX_CLOCK' ]
 
 ###################################################
 #
diff --git a/build_opts/ALPHA_FS b/build_opts/ALPHA
index ffe532690..384394091 100644
--- a/build_opts/ALPHA_FS
+++ b/build_opts/ALPHA
@@ -1,4 +1,4 @@
 TARGET_ISA = 'alpha'
-FULL_SYSTEM = 1
+SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MI_example'
diff --git a/build_opts/ALPHA_SE_MESI_CMP_directory b/build_opts/ALPHA_MESI_CMP_directory
index c55731b30..32eeb0d11 100644
--- a/build_opts/ALPHA_SE_MESI_CMP_directory
+++ b/build_opts/ALPHA_MESI_CMP_directory
@@ -1,4 +1,3 @@
-FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MESI_CMP_directory'
diff --git a/build_opts/ALPHA_SE_MOESI_CMP_directory b/build_opts/ALPHA_MOESI_CMP_directory
index 5edc7688b..be42e636c 100644
--- a/build_opts/ALPHA_SE_MOESI_CMP_directory
+++ b/build_opts/ALPHA_MOESI_CMP_directory
@@ -1,4 +1,3 @@
-FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MOESI_CMP_directory'
diff --git a/build_opts/ALPHA_SE_MOESI_CMP_token b/build_opts/ALPHA_MOESI_CMP_token
index f69c2c48c..0c94391fa 100644
--- a/build_opts/ALPHA_SE_MOESI_CMP_token
+++ b/build_opts/ALPHA_MOESI_CMP_token
@@ -1,4 +1,3 @@
-FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MOESI_CMP_token'
diff --git a/build_opts/ALPHA_SE_MOESI_hammer b/build_opts/ALPHA_MOESI_hammer
index f21ca5e5d..99e8f685b 100644
--- a/build_opts/ALPHA_SE_MOESI_hammer
+++ b/build_opts/ALPHA_MOESI_hammer
@@ -1,4 +1,3 @@
-FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MOESI_hammer'
diff --git a/build_opts/ALPHA_SE_Network_test b/build_opts/ALPHA_Network_test
index 77426d349..90bec0c2f 100644
--- a/build_opts/ALPHA_SE_Network_test
+++ b/build_opts/ALPHA_Network_test
@@ -1,4 +1,3 @@
-FULL_SYSTEM = 0
 SS_COMPATIBLE_FP = 1
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'Network_test'
diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE
deleted file mode 100644
index b21fec4cb..000000000
--- a/build_opts/ALPHA_SE
+++ /dev/null
@@ -1,4 +0,0 @@
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MI_example'
diff --git a/build_opts/ARM_FS b/build_opts/ARM
index f6b2d9e21..9c27c0d27 100644
--- a/build_opts/ARM_FS
+++ b/build_opts/ARM
@@ -1,4 +1,3 @@
 TARGET_ISA = 'arm'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-FULL_SYSTEM = 1
 PROTOCOL = 'MI_example'
diff --git a/build_opts/ARM_SE b/build_opts/ARM_SE
deleted file mode 100644
index 1d89b87a3..000000000
--- a/build_opts/ARM_SE
+++ /dev/null
@@ -1,4 +0,0 @@
-TARGET_ISA = 'arm'
-FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-PROTOCOL = 'MI_example'
diff --git a/build_opts/MIPS_SE b/build_opts/MIPS
index 085557898..82a9d6243 100644
--- a/build_opts/MIPS_SE
+++ b/build_opts/MIPS
@@ -1,4 +1,3 @@
 TARGET_ISA = 'mips'
-FULL_SYSTEM = 0
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
 PROTOCOL = 'MI_example'
diff --git a/build_opts/POWER_SE b/build_opts/POWER
index 13e175ebc..672046cee 100644
--- a/build_opts/POWER_SE
+++ b/build_opts/POWER
@@ -1,4 +1,3 @@
 TARGET_ISA = 'power'
-FULL_SYSTEM = 0
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
 PROTOCOL = 'MI_example'
diff --git a/build_opts/SPARC_SE b/build_opts/SPARC
index a76d7a826..e992b8cd9 100644
--- a/build_opts/SPARC_SE
+++ b/build_opts/SPARC
@@ -1,4 +1,3 @@
 TARGET_ISA = 'sparc'
 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-FULL_SYSTEM = 0
 PROTOCOL = 'MI_example'
diff --git a/build_opts/SPARC_FS b/build_opts/SPARC_FS
deleted file mode 100644
index f1dd81481..000000000
--- a/build_opts/SPARC_FS
+++ /dev/null
@@ -1,4 +0,0 @@
-TARGET_ISA = 'sparc'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
-FULL_SYSTEM = 1
-PROTOCOL = 'MI_example'
diff --git a/build_opts/X86_FS b/build_opts/X86
index ddec6186d..64d163c5a 100644
--- a/build_opts/X86_FS
+++ b/build_opts/X86
@@ -1,4 +1,3 @@
 TARGET_ISA = 'x86'
 CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
-FULL_SYSTEM = 1
 PROTOCOL = 'MI_example'
diff --git a/build_opts/X86_SE b/build_opts/X86_SE
deleted file mode 100644
index 14f350712..000000000
--- a/build_opts/X86_SE
+++ /dev/null
@@ -1,4 +0,0 @@
-TARGET_ISA = 'x86'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-FULL_SYSTEM = 0
-PROTOCOL = 'MI_example'
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6154f9877..80379f6a3 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -552,8 +552,8 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
     return self
 
 
-def makeDualRoot(testSystem, driveSystem, dumpfile):
-    self = Root()
+def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
+    self = Root(full_system = full_system)
     self.testsys = testSystem
     self.drivesys = driveSystem
     self.etherlink = EtherLink()
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 193f8d487..0ae287e77 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -124,8 +124,7 @@ def run(options, root, testsys, cpu_class):
             if options.fast_forward:
                 testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
             switch_cpus[i].system =  testsys
-            if not buildEnv['FULL_SYSTEM']:
-                switch_cpus[i].workload = testsys.cpu[i].workload
+            switch_cpus[i].workload = testsys.cpu[i].workload
             switch_cpus[i].clock = testsys.cpu[0].clock
             # simulation period
             if options.maxinsts:
@@ -148,9 +147,8 @@ def run(options, root, testsys, cpu_class):
         for i in xrange(np):
             switch_cpus[i].system =  testsys
             switch_cpus_1[i].system =  testsys
-            if not buildEnv['FULL_SYSTEM']:
-                switch_cpus[i].workload = testsys.cpu[i].workload
-                switch_cpus_1[i].workload = testsys.cpu[i].workload
+            switch_cpus[i].workload = testsys.cpu[i].workload
+            switch_cpus_1[i].workload = testsys.cpu[i].workload
             switch_cpus[i].clock = testsys.cpu[0].clock
             switch_cpus_1[i].clock = testsys.cpu[0].clock
 
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 08484559a..4456212c9 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -47,9 +47,6 @@ from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import addToPath, fatal
 
-if not buildEnv['FULL_SYSTEM']:
-    fatal("This script requires full-system mode (*_FS).")
-
 addToPath('../common')
 
 from FSConfig import *
@@ -198,9 +195,9 @@ if len(bm) == 2:
         drive_sys.kernel = binary(options.kernel)
 
     drive_sys.init_param = options.init_param
-    root = makeDualRoot(test_sys, drive_sys, options.etherdump)
+    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:
-    root = Root(system=test_sys)
+    root = Root(full_system=True, system=test_sys)
 else:
     print "Error I don't know how to create more than 2 systems."
     sys.exit(1)
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 24a49a9b3..b2cedc8f5 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -172,7 +172,7 @@ make_level(treespec, prototypes, system.physmem, "port")
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 if options.atomic:
     root.system.mem_mode = 'atomic'
 else:
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 55b1c85e6..28c7dde55 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -38,9 +38,6 @@ addToPath('../ruby')
 
 import Ruby
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -111,7 +108,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index a7d0a26cd..d7fc45bde 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -40,9 +40,6 @@ from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import addToPath, fatal
 
-if not buildEnv['FULL_SYSTEM']:
-    fatal("This script requires full-system mode (*_FS).")
-
 addToPath('../common')
 addToPath('../ruby')
 
@@ -136,6 +133,6 @@ for (i, cpu) in enumerate(system.cpu):
         cpu.interrupts.pio = system.piobus.port
         cpu.interrupts.int_port = system.piobus.port
 
-root = Root(system = system)
+root = Root(full_system = True, system = system)
 
 Simulation.run(options, root, system, FutureClass)
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 6b1a46776..5b693f3f6 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -38,9 +38,6 @@ addToPath('../ruby')
 
 import Ruby
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -162,7 +159,7 @@ for (i, dma) in enumerate(dmas):
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index cd221ec7e..79e6365af 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -37,9 +37,6 @@ addToPath('../common')
 addToPath('../ruby')
 import Ruby
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -121,7 +118,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 7655e32fd..4074b08f1 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -38,9 +38,6 @@ addToPath('../ruby')
 
 import Ruby
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -131,7 +128,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/se.py b/configs/example/se.py
index 572364482..1edd99e9b 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -52,9 +52,6 @@ from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import addToPath, fatal
 
-if buildEnv['FULL_SYSTEM']:
-    fatal("This script requires syscall emulation mode (*_SE).")
-
 addToPath('../common')
 addToPath('../ruby')
 
@@ -200,6 +197,6 @@ for i in xrange(np):
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 Simulation.run(options, root, system, FutureClass)
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index 0877ac00a..bbe7fe844 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -51,8 +51,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
     #
     # The Garnet tester protocol does not support fs nor dma
     #
-    if buildEnv['FULL_SYSTEM']:
-        panic("This script requires system-emulation mode (*_SE).")
     assert(piobus == None)
     assert(dma_devices == [])
     
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index e8c471eaa..4a9446794 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -239,7 +239,7 @@ for cluster in clusters:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 200eb191d..8a9b815e6 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -225,7 +225,7 @@ for cpu in cpus:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks
diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index f6d9eb4c6..fcbe81edd 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -27,6 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
+from m5.proxy import *
 from System import System
 
 class AlphaSystem(System):
@@ -42,6 +43,9 @@ class LinuxAlphaSystem(AlphaSystem):
     system_type = 34
     system_rev = 1 << 10
 
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                         "boot processor frequency")
+
 class FreebsdAlphaSystem(AlphaSystem):
     type = 'FreebsdAlphaSystem'
     system_type = 34
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index e3701d2a4..7e683364a 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -34,40 +34,33 @@ Import('*')
 if env['TARGET_ISA'] == 'alpha':
     Source('ev5.cc')
     Source('faults.cc')
+    Source('freebsd/system.cc')
+    Source('idle_event.cc')
+    Source('interrupts.cc')
     Source('ipr.cc')
     Source('isa.cc')
+    Source('kernel_stats.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
+    Source('osfpal.cc')
     Source('pagetable.cc')
+    Source('process.cc')
     Source('regredir.cc')
     Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
     Source('tlb.cc')
+    Source('tru64/process.cc')
+    Source('tru64/system.cc')
+    Source('tru64/tru64.cc')
     Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('AlphaInterrupts.py')
+    SimObject('AlphaSystem.py')
     SimObject('AlphaTLB.py')
 
-    if env['FULL_SYSTEM']:
-        SimObject('AlphaInterrupts.py')
-        SimObject('AlphaSystem.py')
-
-        Source('idle_event.cc')
-        Source('interrupts.cc')
-        Source('kernel_stats.cc')
-        Source('osfpal.cc')
-        Source('stacktrace.cc')
-        Source('system.cc')
-        Source('vtophys.cc')
-
-        Source('freebsd/system.cc')
-        Source('linux/system.cc')
-        Source('tru64/system.cc')
-
-    else:
-        Source('process.cc')
-
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-
-        Source('tru64/tru64.cc')
-        Source('tru64/process.cc')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 6259f8fc2..4dcc58ffe 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -36,7 +36,6 @@
 #include "arch/alpha/tlb.hh"
 #include "base/cp_annotate.hh"
 #include "base/debug.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
@@ -44,8 +43,6 @@
 
 namespace AlphaISA {
 
-#if FULL_SYSTEM
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Machine dependent functions
@@ -76,8 +73,6 @@ zeroRegisters(CPU *cpu)
     cpu->thread->setFloatReg(ZeroReg, 0.0);
 }
 
-#endif
-
 ////////////////////////////////////////////////////////////////////////
 //
 //
@@ -201,10 +196,8 @@ ISA::readIpr(int idx, ThreadContext *tc)
     return retval;
 }
 
-#ifdef DEBUG
 // Cause the simulator to break when changing to the following IPL
 int break_ipl = -1;
-#endif
 
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
@@ -260,10 +253,8 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
       case IPR_PALtemp23:
         // write entire quad w/ no side-effect
-#if FULL_SYSTEM
         if (tc->getKernelStats())
             tc->getKernelStats()->context(ipr[idx], val, tc);
-#endif
         ipr[idx] = val;
         break;
 
@@ -291,14 +282,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-#if FULL_SYSTEM
         if (tc->getKernelStats())
             tc->getKernelStats()->swpipl(ipr[idx]);
-#endif
         break;
 
       case IPR_DTB_CM:
-#if FULL_SYSTEM
         if (val & 0x18) {
             if (tc->getKernelStats())
                 tc->getKernelStats()->mode(Kernel::user, tc);
@@ -306,7 +294,6 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
             if (tc->getKernelStats())
                 tc->getKernelStats()->mode(Kernel::kernel, tc);
         }
-#endif
 
       case IPR_ICM:
         // only write two mode bits - processor mode
@@ -483,8 +470,6 @@ copyIprs(ThreadContext *src, ThreadContext *dest)
 
 } // namespace AlphaISA
 
-#if FULL_SYSTEM
-
 using namespace AlphaISA;
 
 Fault
@@ -534,5 +519,3 @@ SimpleThread::simPalCheck(int palFunc)
 
     return true;
 }
-
-#endif // FULL_SYSTEM
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index c66c6f8ab..e4a5c9223 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -35,11 +35,9 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
 
 namespace AlphaISA {
 
@@ -107,12 +105,12 @@ FaultName IntegerOverflowFault::_name = "intover";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
-#if FULL_SYSTEM
-
 void
 AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     countStat()++;
 
     PCState pc = tc->pcState();
@@ -135,32 +133,36 @@ void
 ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     panic("Arithmetic traps are unimplemented!");
 }
 
 void
 DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    // Set fault address and flags.  Even though we're modeling an
-    // EV5, we use the EV6 technique of not latching fault registers
-    // on VPTE loads (instead of locking the registers until IPR_VA is
-    // read, like the EV5).  The EV6 approach is cleaner and seems to
-    // work with EV5 PAL code, but not the other way around.
-    if (!tc->misspeculating() &&
-        reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
-        // set VA register with faulting address
-        tc->setMiscRegNoEffect(IPR_VA, vaddr);
-
-        // set MM_STAT register flags
-        MachInst machInst = inst->machInst;
-        tc->setMiscRegNoEffect(IPR_MM_STAT,
-            (((Opcode(machInst) & 0x3f) << 11) |
-             ((Ra(machInst) & 0x1f) << 6) |
-             (flags & 0x3f)));
-
-        // set VA_FORM register with faulting formatted address
-        tc->setMiscRegNoEffect(IPR_VA_FORM,
-            tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+    if (FullSystem) {
+        // Set fault address and flags.  Even though we're modeling an
+        // EV5, we use the EV6 technique of not latching fault registers
+        // on VPTE loads (instead of locking the registers until IPR_VA is
+        // read, like the EV5).  The EV6 approach is cleaner and seems to
+        // work with EV5 PAL code, but not the other way around.
+        if (!tc->misspeculating() &&
+            reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+            // set VA register with faulting address
+            tc->setMiscRegNoEffect(IPR_VA, vaddr);
+
+            // set MM_STAT register flags
+            MachInst machInst = inst->machInst;
+            tc->setMiscRegNoEffect(IPR_MM_STAT,
+                (((Opcode(machInst) & 0x3f) << 11) |
+                 ((Ra(machInst) & 0x1f) << 6) |
+                 (flags & 0x3f)));
+
+            // set VA_FORM register with faulting formatted address
+            tc->setMiscRegNoEffect(IPR_VA_FORM,
+                tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+        }
     }
 
     AlphaFault::invoke(tc);
@@ -169,20 +171,25 @@ DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (!tc->misspeculating()) {
-        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
-        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+    if (FullSystem) {
+        if (!tc->misspeculating()) {
+            tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+            tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+                tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+        }
     }
 
     AlphaFault::invoke(tc);
 }
 
-#else
-
 void
 ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        ItbFault::invoke(tc);
+        return;
+    }
+
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
     bool success = p->pTable->lookup(pc, entry);
@@ -197,6 +204,11 @@ ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        DtbFault::invoke(tc, inst);
+        return;
+    }
+
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
     bool success = p->pTable->lookup(vaddr, entry);
@@ -211,7 +223,5 @@ NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
     }
 }
 
-#endif
-
 } // namespace AlphaISA
 
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 3da97ccb4..7eddd14eb 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -33,7 +33,6 @@
 #define __ARCH_ALPHA_FAULTS_HH__
 
 #include "arch/alpha/pagetable.hh"
-#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 
@@ -49,10 +48,8 @@ class AlphaFault : public FaultBase
     virtual bool skipFaultingInstruction() {return false;}
     virtual bool setRestartAddress() {return true;}
   public:
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
 };
@@ -111,10 +108,8 @@ class ArithmeticFault : public AlphaFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class InterruptFault : public AlphaFault
@@ -147,10 +142,8 @@ class DtbFault : public AlphaFault
     FaultName name() const = 0;
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class NDtbMissFault : public DtbFault
@@ -167,10 +160,8 @@ class NDtbMissFault : public DtbFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class PDtbMissFault : public DtbFault
@@ -247,10 +238,8 @@ class ItbFault : public AlphaFault
     FaultName name() const = 0;
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class ItbPageFault : public ItbFault
@@ -265,10 +254,8 @@ class ItbPageFault : public ItbFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class ItbAcvFault : public ItbFault
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 106290784..4bbf83cce 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
             0x6c: decode RA {
                 31: decode IMM {
                     1: decode INTIMM {
-                        // return EV5 for FULL_SYSTEM and EV6 otherwise
-                        1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+                        // return EV5 for FullSystem and EV6 otherwise
+                        1: implver({{ Rc = FullSystem ? 1 : 2 }});
                     }
                 }
             }
@@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
                  * the parser to understand that.
                  */
                 uint64_t unused_var M5_VAR_USED = Rb;
-                Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+                Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
             }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
         }
 
-        0xe000: decode FULL_SYSTEM {
+        0xe000: decode FullSystem {
             0: FailUnimpl::rc_se();
             default: BasicOperate::rc({{
                 Ra = IntrFlag;
                 IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
         }
-        0xf000: decode FULL_SYSTEM {
+        0xf000: decode FullSystem {
             0: FailUnimpl::rs_se();
             default: BasicOperate::rs({{
                 Ra = IntrFlag;
@@ -821,43 +821,41 @@ decode OPCODE default Unknown::unknown() {
         }
     }
 
-#if FULL_SYSTEM
-    0x00: CallPal::call_pal({{
-        if (!palValid ||
-            (palPriv
-             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
-            // invalid pal function code, or attempt to do privileged
-            // PAL call in non-kernel mode
-            fault = new UnimplementedOpcodeFault;
-        } else {
-            // check to see if simulator wants to do something special
-            // on this PAL call (including maybe suppress it)
-            bool dopal = xc->simPalCheck(palFunc);
-
-            if (dopal) {
-                xc->setMiscReg(IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+    0x00: decode FullSystem {
+        0: decode PALFUNC {
+            format EmulatedCallPal {
+                0x00: halt ({{
+                    exitSimLoop("halt instruction encountered");
+                }}, IsNonSpeculative);
+                0x83: callsys({{
+                    xc->syscall(R0);
+                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+                // Read uniq reg into ABI return value register (r0)
+                0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
+                // Write uniq reg with value from ABI arg register (r16)
+                0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
             }
         }
-    }}, IsNonSpeculative);
-#else
-    0x00: decode PALFUNC {
-        format EmulatedCallPal {
-            0x00: halt ({{
-                exitSimLoop("halt instruction encountered");
-            }}, IsNonSpeculative);
-            0x83: callsys({{
-                xc->syscall(R0);
-            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
-            // Read uniq reg into ABI return value register (r0)
-            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
-            // Write uniq reg with value from ABI arg register (r16)
-            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
-        }
+        default: CallPal::call_pal({{
+            if (!palValid ||
+                (palPriv
+                 && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
+                // invalid pal function code, or attempt to do privileged
+                // PAL call in non-kernel mode
+                fault = new UnimplementedOpcodeFault;
+            } else {
+                // check to see if simulator wants to do something special
+                // on this PAL call (including maybe suppress it)
+                bool dopal = xc->simPalCheck(palFunc);
+
+                if (dopal) {
+                    xc->setMiscReg(IPR_EXC_ADDR, NPC);
+                    NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
+                }
+            }
+        }}, IsNonSpeculative);
     }
-#endif
 
-#if FULL_SYSTEM
     0x1b: decode PALMODE {
         0: OpcdecFault::hw_st_quad();
         1: decode HW_LDST_QUAD {
@@ -924,8 +922,6 @@ decode OPCODE default Unknown::unknown() {
         }
     }
 
-#endif
-
     format BasicOperate {
         // M5 special opcodes use the reserved 0x01 opcode space
         0x01: decode M5FUNC {
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e3a6b18ab..5821ebcc5 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -45,7 +45,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;  // dummy... this ipr access should not fault
-        if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+        if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 796c5e38e..e87a184c3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -64,6 +64,7 @@ output decoder {{
 #include "config/ss_compatible_fp.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
+#include "sim/full_system.hh"
 
 using namespace AlphaISA;
 }};
@@ -81,6 +82,7 @@ output exec {{
 #include "cpu/exetrace.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/full_system.hh"
 #include "sim/pseudo_inst.hh"
 #include "sim/sim_exit.hh"
 
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 852de5554..97cb845bf 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -36,7 +36,6 @@ namespace LittleEndianGuest {}
 
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst_fwd.hh"
 
 namespace AlphaISA {
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 19a2a6ac3..6f3cf6b32 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -49,7 +49,6 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Thread.hh"
-#include "dev/platform.hh"
 #include "kern/linux/events.hh"
 #include "kern/linux/printk.hh"
 #include "mem/physical.hh"
@@ -176,7 +175,7 @@ LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
     Addr addr = 0;
     if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
         Tick cpuFreq = tc->getCpuPtr()->frequency();
-        Tick intrFreq = platform->intrFrequency();
+        assert(intrFreq);
         FSTranslatingPortProxy* vp;
 
         vp = tc->getVirtProxy();
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index e2fda39a8..5436a27b2 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -134,6 +134,8 @@ class LinuxAlphaSystem : public AlphaSystem
     virtual void initState();
 
     void setDelayLoop(ThreadContext *tc);
+
+    const Params *params() const { return (const Params *)_params; }
 };
 
 #endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
index 59df93bef..b9091d5b6 100644
--- a/src/arch/alpha/pagetable.hh
+++ b/src/arch/alpha/pagetable.hh
@@ -34,7 +34,6 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "arch/alpha/utility.hh"
-#include "config/full_system.hh"
 
 namespace AlphaISA {
 
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index a8788051f..a08cddaec 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -34,7 +34,7 @@
 #include "arch/alpha/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
 
 class ThreadContext;
 
@@ -83,9 +83,8 @@ class Predecoder
     {
         ext_inst = inst;
         emiIsReady = true;
-#if FULL_SYSTEM
-        ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
-#endif
+        if (FullSystem)
+            ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
     }
 
     bool
diff --git a/src/arch/alpha/regredir.cc b/src/arch/alpha/regredir.cc
index 991138f11..861ded4d1 100644
--- a/src/arch/alpha/regredir.cc
+++ b/src/arch/alpha/regredir.cc
@@ -31,22 +31,13 @@
  */
 
 #include "arch/alpha/regredir.hh"
-#include "config/full_system.hh"
 
 namespace AlphaISA {
 
-#if FULL_SYSTEM
 const int reg_redir[NumIntRegs] = {
     /*  0 */ 0, 1, 2, 3, 4, 5, 6, 7,
     /*  8 */ 32, 33, 34, 35, 36, 37, 38, 15,
     /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
     /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-#else
-const int reg_redir[NumIntRegs] = {
-    /*  0 */ 0, 1, 2, 3, 4, 5, 6, 7,
-    /*  8 */ 8, 9, 10, 11, 12, 13, 14, 15,
-    /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
-    /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 };
-#endif
 
 } // namespace AlphaISA
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc
index cd9c8910d..aa120686c 100644
--- a/src/arch/alpha/remote_gdb.cc
+++ b/src/arch/alpha/remote_gdb.cc
@@ -121,15 +121,12 @@
 
 #include <string>
 
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/alpha/vtophys.hh"
-#endif
 
 #include "arch/alpha/kgdb.h"
 #include "arch/alpha/regredir.hh"
 #include "arch/alpha/remote_gdb.hh"
 #include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
 #include "base/intmath.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
@@ -142,6 +139,7 @@
 #include "mem/physical.hh"
 #include "mem/port.hh"
 #include "sim/system.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace AlphaISA;
@@ -158,9 +156,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-#if !FULL_SYSTEM
-    panic("acc function needs to be rewritten for SE mode\n");
-#else
+    if (!FullSystem)
+        panic("acc function needs to be rewritten for SE mode\n");
+
     Addr last_va;
 
     va = TruncPage(va);
@@ -173,8 +171,8 @@ RemoteGDB::acc(Addr va, size_t len)
                         "%#x < K0SEG + size\n", va);
                 return true;
             } else {
-                DPRINTF(GDBAcc, "acc:   Mapping invalid %#x > K0SEG + size\n",
-                        va);
+                DPRINTF(GDBAcc, "acc:   Mapping invalid %#x "
+                        "> K0SEG + size\n", va);
                 return false;
             }
         }
@@ -202,7 +200,6 @@ RemoteGDB::acc(Addr va, size_t len)
 
     DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
     return true;
-#endif
 }
 
 /*
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index c7a646893..656ab4d6f 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -45,7 +45,7 @@
 using namespace AlphaISA;
 
 AlphaSystem::AlphaSystem(Params *p)
-    : System(p)
+    : System(p), intrFreq(0)
 {
     consoleSymtab = new SymbolTable;
     palSymtab = new SymbolTable;
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index 0c725c3dc..0e809cb94 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -85,6 +85,8 @@ class AlphaSystem : public System
 #endif
 
   protected:
+    Tick intrFreq;
+
     const Params *params() const { return (const Params *)_params; }
 
     /** Add a function-based event to PALcode. */
@@ -104,6 +106,9 @@ class AlphaSystem : public System
     }
 
     virtual Addr fixFuncEventAddr(Addr addr);
+
+  public:
+    void setIntrFreq(Tick freq) { intrFreq = freq; }
 };
 
 #endif // __ARCH_ALPHA_SYSTEM_HH__
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index b211c4923..623eafb8a 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -42,6 +42,7 @@
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
 #include "debug/TLB.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -370,7 +371,7 @@ Fault
 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
-    if (FULL_SYSTEM && PcPAL(req->getPC()))
+    if (FullSystem && PcPAL(req->getPC()))
         req->setFlags(Request::PHYSICAL);
 
     if (PcPAL(req->getPC())) {
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index 4de77ffd4..1bac650a0 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -30,18 +30,20 @@
  */
 
 #include "arch/alpha/utility.hh"
-
-#if FULL_SYSTEM
 #include "arch/alpha/vtophys.hh"
 #include "mem/fs_translating_port_proxy.hh"
-#endif
+#include "sim/full_system.hh"
 
 namespace AlphaISA {
 
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
+    if (!FullSystem) {
+        panic("getArgument() is Full system only\n");
+        M5_DUMMY_RETURN;
+    }
+
     const int NumArgumentRegs = 6;
     if (number < NumArgumentRegs) {
         if (fp)
@@ -55,10 +57,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
                            (number-NumArgumentRegs) * sizeof(uint64_t));
         return arg;
     }
-#else
-    panic("getArgument() is Full system only\n");
-    M5_DUMMY_RETURN;
-#endif
 }
 
 void
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index c0c985c34..a9b5c4cba 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -36,7 +36,6 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "arch/alpha/ev5.hh"
@@ -96,9 +95,7 @@ RoundPage(Addr addr)
 { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
 
 void initIPRs(ThreadContext *tc, int cpuId);
-#if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId);
-#endif
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index f0d23445f..fc6f51d84 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -37,26 +37,22 @@
 #
 # Authors: Ali Saidi
 
-from m5.defines import buildEnv
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+from MemObject import MemObject
 
-if buildEnv['FULL_SYSTEM']:
-    from MemObject import MemObject
-
-    class ArmTableWalker(MemObject):
-        type = 'ArmTableWalker'
-        cxx_class = 'ArmISA::TableWalker'
-        port = Port("Port for TableWalker to do walk the translation with")
-        sys = Param.System(Parent.any, "system object parameter")
-        min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
-        max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
+class ArmTableWalker(MemObject):
+    type = 'ArmTableWalker'
+    cxx_class = 'ArmISA::TableWalker'
+    port = Port("Port for TableWalker to do walk the translation with")
+    sys = Param.System(Parent.any, "system object parameter")
+    min_backoff = Param.Tick(0, "Minimum backoff delay after failed send")
+    max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send")
 
 
 class ArmTLB(SimObject):
     type = 'ArmTLB'
     cxx_class = 'ArmISA::TLB'
     size = Param.Int(64, "TLB size")
-    if buildEnv['FULL_SYSTEM']:
-       walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
+    walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index a907e52fb..171c04718 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -54,35 +54,32 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
     Source('miscregs.cc')
-    Source('predecoder.cc')
     Source('nativetrace.cc')
+    Source('predecoder.cc')
+    Source('process.cc')
+    Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
+    Source('table_walker.cc')
     Source('tlb.cc')
     Source('utility.cc')
-    Source('remote_gdb.cc')
+    Source('vtophys.cc')
 
+    SimObject('ArmInterrupts.py')
     SimObject('ArmNativeTrace.py')
+    SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
 
     DebugFlag('Arm')
     DebugFlag('TLBVerbose')
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('Predecoder', "Instructions returned by the predecoder")
-    if env['FULL_SYSTEM']:
-        Source('interrupts.cc')
-        Source('stacktrace.cc')
-        Source('system.cc')
-        Source('vtophys.cc')
-        Source('linux/system.cc')
-        Source('table_walker.cc')
-        
-        SimObject('ArmInterrupts.py')
-        SimObject('ArmSystem.py')
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 68c5fa0e8..061392f59 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -47,6 +47,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Faults.hh"
+#include "sim/full_system.hh"
 
 namespace ArmISA
 {
@@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc)
 
 }
 
-#if FULL_SYSTEM
-
 void 
 ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // ARM ARM B1.6.3
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
     countStat()++;
 
     SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
@@ -165,16 +166,21 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    tc->getCpuPtr()->clearInterrupts();
-    tc->clearArchRegs();
+    if (FullSystem) {
+        tc->getCpuPtr()->clearInterrupts();
+        tc->clearArchRegs();
+    }
     ArmFault::invoke(tc, inst);
 }
 
-#else
-
 void
 UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        ArmFault::invoke(tc, inst);
+        return;
+    }
+
     // If the mnemonic isn't defined this has to be an unknown instruction.
     assert(unknown || mnemonic != NULL);
     if (disabled) {
@@ -192,6 +198,11 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        ArmFault::invoke(tc, inst);
+        return;
+    }
+
     // As of now, there isn't a 32 bit thumb version of this instruction.
     assert(!machInst.bigThumb);
     uint32_t callNum;
@@ -205,8 +216,6 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
     tc->pcState(pc);
 }
 
-#endif // FULL_SYSTEM
-
 template<class T>
 void
 AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
@@ -245,13 +254,14 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
 void
 ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
     DPRINTF(Faults, "Invoking ArmSev Fault\n");
-#if FULL_SYSTEM
+    if (!FullSystem)
+        return;
+
     // Set sev_mailbox to 1, clear the pending interrupt from remote
     // SEV execution and let pipeline continue as pcState is still
     // valid.
     tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
     tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
-#endif
 }
 
 // return via SUBS pc, lr, xxx; rfe, movs, ldm
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 2d025cc94..9858e52ef 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -48,8 +48,8 @@
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
 
@@ -108,10 +108,8 @@ class ArmFault : public FaultBase
         FaultStat count;
     };
 
-#if FULL_SYSTEM
     void invoke(ThreadContext *tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     virtual FaultStat& countStat() = 0;
     virtual FaultOffset offset() = 0;
     virtual OperatingMode nextMode() = 0;
@@ -139,19 +137,14 @@ class ArmFaultVals : public ArmFault
 };
 
 class Reset : public ArmFaultVals<Reset>
-#if FULL_SYSTEM
 {
   public:
     void invoke(ThreadContext *tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
-#else
-{};
-#endif //FULL_SYSTEM
 
 class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
 {
-#if !FULL_SYSTEM
   protected:
     ExtMachInst machInst;
     bool unknown;
@@ -167,25 +160,27 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
         mnemonic(_mnemonic), disabled(_disabled)
     {
     }
+    UndefinedInstruction() :
+        machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
+    {}
 
     void invoke(ThreadContext *tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class SupervisorCall : public ArmFaultVals<SupervisorCall>
 {
-#if !FULL_SYSTEM
   protected:
     ExtMachInst machInst;
 
   public:
     SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
     {}
+    SupervisorCall() : machInst(0)
+    {}
 
     void invoke(ThreadContext *tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 template <class T>
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index fa850190f..d65555822 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -46,6 +46,7 @@
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "sim/full_system.hh"
 
 namespace ArmISA
 {
@@ -294,11 +295,11 @@ class ArmStaticInst : public StaticInst
     inline Fault
     disabledFault() const
     {
-#if FULL_SYSTEM
+        if (FullSystem) {
             return new UndefinedInstruction();
-#else
+        } else {
             return new UndefinedInstruction(machInst, false, mnemonic, true);
-#endif
+        }
     }
 };
 }
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 03a585001..ffe5f45e3 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1103,7 +1103,6 @@ def format ArmMisc() {{
                 switch (IMM) {
                   case 0x0:
                     return new NopInst(machInst);
-#if FULL_SYSTEM
                   case 0x1:
                     return new YieldInst(machInst);
                   case 0x2:
@@ -1112,7 +1111,6 @@ def format ArmMisc() {{
                     return new WfiInst(machInst);
                   case 0x4:
                     return new SevInst(machInst);
-#endif
                   default:
                     return new Unknown(machInst);
                 }
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa
index f532d828b..3b08acad7 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -42,35 +42,27 @@ def format M5ops() {{
     {
         const uint32_t m5func = bits(machInst, 23, 16);
         switch(m5func) {
-#if FULL_SYSTEM
             case 0x00: return new Arm(machInst);
             case 0x01: return new Quiesce(machInst);
             case 0x02: return new QuiesceNs(machInst);
             case 0x03: return new QuiesceCycles(machInst);
             case 0x04: return new QuiesceTime(machInst);
-#endif
             case 0x07: return new Rpns(machInst);
             case 0x09: return new WakeCPU(machInst);
             case 0x10: return new Deprecated_ivlb(machInst);
             case 0x11: return new Deprecated_ivle(machInst);
             case 0x20: return new Deprecated_exit (machInst);
             case 0x21: return new M5exit(machInst);
-#if FULL_SYSTEM
             case 0x31: return new Loadsymbol(machInst);
             case 0x30: return new Initparam(machInst);
-#endif
             case 0x40: return new Resetstats(machInst);
             case 0x41: return new Dumpstats(machInst);
             case 0x42: return new Dumpresetstats(machInst);
             case 0x43: return new M5checkpoint(machInst);
-#if FULL_SYSTEM
             case 0x50: return new M5readfile(machInst);
-#endif
             case 0x51: return new M5break(machInst);
             case 0x52: return new M5switchcpu(machInst);
-#if FULL_SYSTEM
             case 0x53: return new M5addsymbol(machInst);
-#endif
             case 0x54: return new M5panic(machInst);
             case 0x5a: return new M5workbegin(machInst);
             case 0x5b: return new M5workend(machInst);
diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa
index a0e0afd32..1c9a4b402 100644
--- a/src/arch/arm/isa/formats/unimp.isa
+++ b/src/arch/arm/isa/formats/unimp.isa
@@ -147,11 +147,10 @@ output exec {{
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(machInst, false, mnemonic);
-#endif
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(machInst, false, mnemonic);
     }
 
     Fault
diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa
index 8a94d1ebd..1ff6ef9e4 100644
--- a/src/arch/arm/isa/insts/div.isa
+++ b/src/arch/arm/isa/insts/div.isa
@@ -41,11 +41,10 @@ let {{
     sdivCode = '''
     if (Op2_sw == 0) {
         if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
         Dest_sw = 0;
     } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
@@ -65,11 +64,10 @@ let {{
     udivCode = '''
     if (Op2_uw == 0) {
         if (((SCTLR)Sctlr).dz) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
         Dest_uw = 0;
     } else {
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index f20908d4f..da2e10886 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -190,13 +190,9 @@ let {{
     exec_output += PredOpExecute.subst(loadsymbolIop)
 
     initparamCode = '''
-#if FULL_SYSTEM
     uint64_t ip_val  = PseudoInst::initParam(xc->tcBase());
     R0 = bits(ip_val, 31, 0);
     R1 = bits(ip_val, 63, 32);
-#else
-    PseudoInst::panicFsOnlyPseudoInst("initparam");
-#endif
     '''
 
     initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 870f037d0..b671843cf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,11 +40,11 @@
 let {{
 
     svcCode = '''
-#if FULL_SYSTEM
-    fault = new SupervisorCall;
-#else
-    fault = new SupervisorCall(machInst);
-#endif
+    if (FullSystem) {
+        fault = new SupervisorCall;
+    } else {
+        fault = new SupervisorCall(machInst);
+    }
     '''
 
     svcIop = InstObjParams("svc", "Svc", "PredOp",
@@ -502,7 +502,6 @@ let {{
     exec_output += PredOpExecute.subst(yieldIop)
 
     wfeCode = '''
-#if FULL_SYSTEM
     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
     if (SevMailbox == 1) {
         SevMailbox = 0;
@@ -512,14 +511,11 @@ let {{
     } else {
         PseudoInst::quiesce(xc->tcBase());
     }
-#endif
     '''
     wfePredFixUpCode = '''
-#if FULL_SYSTEM
     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
     // and SEV interrupts
     SevMailbox = 1;
-#endif
     '''
     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
             { "code" : wfeCode,
@@ -531,14 +527,12 @@ let {{
     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 
     wfiCode = '''
-#if FULL_SYSTEM
     // WFI doesn't sleep if interrupts are pending (masked or not)
     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
         PseudoInst::quiesceSkip(xc->tcBase());
     } else {
         PseudoInst::quiesce(xc->tcBase());
     }
-#endif
     '''
     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
             { "code" : wfiCode, "predicate_test" : predicateTest },
@@ -548,7 +542,6 @@ let {{
     exec_output += QuiescePredOpExecute.subst(wfiIop)
 
     sevCode = '''
-#if FULL_SYSTEM
     SevMailbox = 1;
     System *sys = xc->tcBase()->getSystemPtr();
     for (int x = 0; x < sys->numContexts(); x++) {
@@ -561,7 +554,6 @@ let {{
             oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
         }
     }
-#endif
     '''
     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
             { "code" : sevCode, "predicate_test" : predicateTest },
@@ -578,11 +570,10 @@ let {{
     decoder_output += BasicConstructor.subst(itIop)
     exec_output += PredOpExecute.subst(itIop)
     unknownCode = '''
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(machInst, true);
-#endif
+    if (FullSystem)
+        return new UndefinedInstruction;
+    else
+        return new UndefinedInstruction(machInst, true);
     '''
     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
                                { "code": unknownCode,
@@ -635,12 +626,12 @@ let {{
 
     mrc15code = '''
     CPSR cpsr = Cpsr;
-    if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(false, mnemonic);
-#endif
+    if (cpsr.mode == MODE_USER) {
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(false, mnemonic);
+    }
     Dest = MiscOp1;
     '''
 
@@ -654,12 +645,12 @@ let {{
 
     mcr15code = '''
     CPSR cpsr = Cpsr;
-    if (cpsr.mode == MODE_USER)
-#if FULL_SYSTEM
-        return new UndefinedInstruction;
-#else
-        return new UndefinedInstruction(false, mnemonic);
-#endif
+    if (cpsr.mode == MODE_USER) {
+        if (FullSystem)
+            return new UndefinedInstruction;
+        else
+            return new UndefinedInstruction(false, mnemonic);
+    }
     MiscDest = Op1;
     '''
     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index dd0d49a5c..b1ad1eeb3 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -872,11 +872,10 @@ let {{
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
                 Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -927,11 +926,10 @@ let {{
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < eCount; i++) {
                 Element srcElem1 = gtoh(srcReg1.elements[i]);
@@ -980,11 +978,10 @@ let {{
             readDestCode = 'destReg = destRegs[i];'
         eWalkCode += '''
         if (imm < 0 && imm >= eCount) {
-#if FULL_SYSTEM
-            fault = new UndefinedInstruction;
-#else
-            fault = new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                fault = new UndefinedInstruction;
+            else
+                fault = new UndefinedInstruction(false, mnemonic);
         } else {
             for (unsigned i = 0; i < rCount; i++) {
                 FloatReg srcReg1 = srcRegs1[i];
@@ -3296,14 +3293,14 @@ let {{
                 destReg.elements[i] = srcReg1.elements[index];
             } else {
                 index -= eCount;
-                if (index >= eCount)
-#if FULL_SYSTEM
-                    fault = new UndefinedInstruction;
-#else
-                    fault = new UndefinedInstruction(false, mnemonic);
-#endif
-                else
+                if (index >= eCount) {
+                    if (FullSystem)
+                        fault = new UndefinedInstruction;
+                    else
+                        fault = new UndefinedInstruction(false, mnemonic);
+                } else {
                     destReg.elements[i] = srcReg2.elements[index];
+                }
             }
         }
     '''
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index f319e75aa..b42a1c4b2 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -73,11 +73,10 @@ let {{
 
     swpPreAccCode = '''
         if (!((SCTLR)Sctlr).sw) {
-#if FULL_SYSTEM
-            return new UndefinedInstruction;
-#else
-            return new UndefinedInstruction(false, mnemonic);
-#endif
+            if (FullSystem)
+                return new UndefinedInstruction;
+            else
+                return new UndefinedInstruction(false, mnemonic);
         }
     '''
 
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 6d84fbf7b..2c86d3d84 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -46,7 +46,6 @@
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 #include "arch/arm/vtophys.hh"
-#include "config/full_system.hh"
 #include "sim/serialize.hh"
 
 namespace ArmISA {
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 223ff4c69..528e19acf 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -134,11 +134,6 @@
 
 #include <string>
 
-#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "arch/arm/vtophys.hh"
-#endif
-
 #include "arch/arm/pagetable.hh"
 #include "arch/arm/registers.hh"
 #include "arch/arm/remote_gdb.hh"
@@ -157,6 +152,7 @@
 #include "mem/page_table.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -173,28 +169,28 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-#if FULL_SYSTEM
-    Addr last_va;
-    va       = truncPage(va);
-    last_va  = roundPage(va + len);
-
-    do  {
-        if (virtvalid(context, va)) {
-            return true;
-        }
-        va += PageBytes;
-    } while (va < last_va);
-
-    DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
-    return true;
-#else
-    TlbEntry entry;
-    //Check to make sure the first byte is mapped into the processes address
-    //space.
-    if (context->getProcessPtr()->pTable->lookup(va, entry))
+    if (FullSystem) {
+        Addr last_va;
+        va       = truncPage(va);
+        last_va  = roundPage(va + len);
+
+        do  {
+            if (virtvalid(context, va)) {
+                return true;
+            }
+            va += PageBytes;
+        } while (va < last_va);
+
+        DPRINTF(GDBAcc, "acc:   %#x mapping is valid\n", va);
         return true;
-    return false;
-#endif
+    } else {
+        TlbEntry entry;
+        //Check to make sure the first byte is mapped into the processes address
+        //space.
+        if (context->getProcessPtr()->pTable->lookup(va, entry))
+            return true;
+        return false;
+    }
 }
 
 /*
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a03e445cf..b19ad5265 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -47,6 +47,8 @@
 
 #include "arch/arm/faults.hh"
 #include "arch/arm/pagetable.hh"
+#include "arch/arm/system.hh"
+#include "arch/arm/table_walker.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/arm/utility.hh"
 #include "base/inifile.hh"
@@ -58,29 +60,20 @@
 #include "debug/TLBVerbose.hh"
 #include "mem/page_table.hh"
 #include "params/ArmTLB.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
-#if FULL_SYSTEM
-#include "arch/arm/system.hh"
-#include "arch/arm/table_walker.hh"
-#endif
-
 using namespace std;
 using namespace ArmISA;
 
 TLB::TLB(const Params *p)
-    : BaseTLB(p), size(p->size)
-#if FULL_SYSTEM
-      , tableWalker(p->walker)
-#endif
-    , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
+    : BaseTLB(p), size(p->size) , tableWalker(p->walker),
+    rangeMRU(1), bootUncacheability(false), miscRegValid(false)
 {
     table = new TlbEntry[size];
     memset(table, 0, sizeof(TlbEntry) * size);
 
-#if FULL_SYSTEM
     tableWalker->setTlb(this);
-#endif
 }
 
 TLB::~TLB()
@@ -404,7 +397,6 @@ TLB::regStats()
     accesses = readAccesses + writeAccesses + instAccesses;
 }
 
-#if !FULL_SYSTEM
 Fault
 TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
         Translation *translation, bool &delay, bool timing)
@@ -436,8 +428,6 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
     return NoFault;
 }
 
-#else // FULL_SYSTEM
-
 Fault
 TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
 {
@@ -578,7 +568,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
         }
     }
 
-
     if (!bootUncacheability &&
             ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
         req->setFlags(Request::UNCACHEABLE);
@@ -684,18 +673,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
     return NoFault;
 }
 
-#endif
-
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
     bool delay = false;
     Fault fault;
-#if FULL_SYSTEM
-    fault = translateFs(req, tc, mode, NULL, delay, false);
-#else
-    fault = translateSe(req, tc, mode, NULL, delay, false);
-#endif
+    if (FullSystem)
+        fault = translateFs(req, tc, mode, NULL, delay, false);
+    else
+        fault = translateSe(req, tc, mode, NULL, delay, false);
     assert(!delay);
     return fault;
 }
@@ -707,11 +693,10 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     assert(translation);
     bool delay = false;
     Fault fault;
-#if FULL_SYSTEM
-    fault = translateFs(req, tc, mode, translation, delay, true);
-#else
-    fault = translateSe(req, tc, mode, translation, delay, true);
-#endif
+    if (FullSystem)
+        fault = translateFs(req, tc, mode, translation, delay, true);
+    else
+        fault = translateSe(req, tc, mode, translation, delay, true);
     DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
             NoFault);
     if (!delay)
@@ -724,11 +709,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 Port*
 TLB::getPort()
 {
-#if FULL_SYSTEM
     return tableWalker->getPort("port");
-#else
-    return NULL;
-#endif
 }
 
 
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 3464e42b3..0bf13fe83 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -89,9 +89,7 @@ class TLB : public BaseTLB
 
     uint32_t _attr;     // Memory attributes for last accessed TLB entry
 
-#if FULL_SYSTEM
     TableWalker *tableWalker;
-#endif
 
     /** Lookup an entry in the TLB
      * @param vpn virtual address
@@ -195,13 +193,10 @@ class TLB : public BaseTLB
         return _attr;
     }
 
-#if FULL_SYSTEM
     Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
-#else
     Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
             Translation *translation, bool &delay, bool timing);
-#endif
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     Fault translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 98195ab04..ac81c7db6 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -40,15 +40,12 @@
 
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/tlb.hh"
 #include "arch/arm/utility.hh"
-#include "cpu/thread_context.hh"
-
-#if FULL_SYSTEM
 #include "arch/arm/vtophys.hh"
+#include "cpu/thread_context.hh"
 #include "mem/fs_translating_port_proxy.hh"
-#endif
-
-#include "arch/arm/tlb.hh"
+#include "sim/full_system.hh"
 
 namespace ArmISA {
 
@@ -66,20 +63,24 @@ initCPU(ThreadContext *tc, int cpuId)
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
+    if (!FullSystem) {
+        panic("getArgument() only implemented for full system mode.\n");
+        M5_DUMMY_RETURN
+    }
+
     if (size == (uint16_t)(-1))
         size = ArmISA::MachineBytes;
     if (fp)
         panic("getArgument(): Floating point arguments not implemented\n");
 
     if (number < NumArgumentRegs) {
-        // If the argument is 64 bits, it must be in an even regiser number
-        // Increment the number here if it isn't even
+        // If the argument is 64 bits, it must be in an even regiser
+        // number. Increment the number here if it isn't even.
         if (size == sizeof(uint64_t)) {
             if ((number % 2) != 0)
                 number++;
-            // Read the two halves of the data
-            // number is inc here to get the second half of the 64 bit reg
+            // Read the two halves of the data. Number is inc here to
+            // get the second half of the 64 bit reg.
             uint64_t tmp;
             tmp = tc->readIntReg(number++);
             tmp |= tc->readIntReg(number) << 32;
@@ -105,10 +106,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
         }
         return arg;
     }
-#else
-    panic("getArgument() only implemented for FULL_SYSTEM\n");
-    M5_DUMMY_RETURN
-#endif
 }
 
 void
diff --git a/src/arch/mips/BISystem.py b/src/arch/mips/BISystem.py
index a6e4091f2..d5e02485e 100755
--- a/src/arch/mips/BISystem.py
+++ b/src/arch/mips/BISystem.py
@@ -32,10 +32,9 @@ from m5.defines import buildEnv
 
 from System import *
 
-if buildEnv['FULL_SYSTEM']:
-    class BareIronMipsSystem(MipsSystem):
-        type = 'BareIronMipsSystem'
-        system_type = 34
-        system_rev = 1 << 10
-        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+    type = 'BareIronMipsSystem'
+    system_type = 34
+    system_rev = 1 << 10
+    hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
 
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index fc4f1efa3..4a0851eba 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -43,16 +43,18 @@ class MipsSystem(System):
     system_rev = Param.UInt64("Revision of system we are emulating")
     load_addr_mask = 0xffffffffff
 
-if buildEnv['FULL_SYSTEM']:
-    class LinuxMipsSystem(MipsSystem):
-        type = 'LinuxMipsSystem'
-        system_type = 34
-        system_rev = 1 << 10
-
-    class BareIronMipsSystem(MipsSystem):
-        type = 'BareIronMipsSystem'
-        bare_iron = True
-        system_type = 34
-        system_rev = 1 << 10
-        hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class LinuxMipsSystem(MipsSystem):
+    type = 'LinuxMipsSystem'
+    system_type = 34
+    system_rev = 1 << 10
+
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                         "boot processor frequency")
+
+class BareIronMipsSystem(MipsSystem):
+    type = 'BareIronMipsSystem'
+    bare_iron = True
+    system_type = 34
+    system_rev = 1 << 10
+    hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
 
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 9fc2b71ff..7e2d4b806 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -33,32 +33,29 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'mips':
+    Source('bare_iron/system.cc')
+    Source('dsp.cc')
     Source('faults.cc')
+    Source('idle_event.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
-    Source('tlb.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/system.cc')
     Source('pagetable.cc')
-    Source('utility.cc')
-    Source('dsp.cc')
+    Source('process.cc')
     Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
+    Source('tlb.cc')
+    Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('MipsInterrupts.py')
+    SimObject('MipsSystem.py')
     SimObject('MipsTLB.py')
-    DebugFlag('MipsPRA')
 
-    if env['FULL_SYSTEM']:
-        SimObject('MipsSystem.py')
-        SimObject('MipsInterrupts.py')
-        Source('idle_event.cc')
-        Source('mips_core_specific.cc')
-        Source('vtophys.cc')
-        Source('system.cc')
-        Source('stacktrace.cc')
-        Source('linux/system.cc')
-        Source('interrupts.cc')
-        Source('bare_iron/system.cc')
-    else:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
+    DebugFlag('MipsPRA')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index 49698eec6..3f6c6866e 100755
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -32,7 +32,6 @@
 #include "arch/mips/isa_traits.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/serialize.hh"
 
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index f13431714..0e9424f38 100755
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -35,7 +35,6 @@
 #include "arch/mips/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 
 class ThreadContext;
 
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 00471aece..3076e0afe 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -39,11 +39,8 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
 
 namespace MipsISA
 {
@@ -136,7 +133,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
 void
 MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (FULL_SYSTEM) {
+    if (FullSystem) {
         DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
         setExceptionState(tc, code());
         tc->pcState(vect(tc));
@@ -148,7 +145,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    if (FULL_SYSTEM) {
+    if (FullSystem) {
         DPRINTF(MipsPRA, "%s encountered.\n", name());
         /* All reset activity must be invoked from here */
         Addr handler = vect(tc);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 76d4fff23..b90c38e99 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -40,6 +40,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 namespace MipsISA
 {
@@ -165,7 +166,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
         MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
             cause.ce = coProcID;
             tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
@@ -200,7 +201,7 @@ class AddressFault : public MipsFault<T>
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
         MipsFault<T>::invoke(tc, inst);
-        if (FULL_SYSTEM)
+        if (FullSystem)
             tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
     }
 };
@@ -252,7 +253,7 @@ class TlbFault : public AddressFault<T>
     invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr)
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
             Addr vect = this->vect(tc);
             setTlbExceptionState(tc, this->code());
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 096aa628f..f4221ab2c 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,6 +36,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 8ebfa66bf..034133f96 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format BasicOp {
                     0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                     0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
-                    0x4: decode FULL_SYSTEM {
+                    0x4: decode FullSystem {
                         0: syscall_se({{ xc->syscall(R2); }},
                                 IsSerializeAfter, IsNonSpeculative);
                         default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x0: add({{
                             IntReg result;
                             Rd = result = Rs + Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, Rt)) {
                                 fault = new IntegerOverflowFault();
                             }
@@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x2: sub({{
                             IntReg result;
                             Rd = result = Rs - Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, ~Rt)) {
                                 fault = new IntegerOverflowFault();
                             }
@@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: addi({{
                 IntReg result;
                 Rt = result = Rs + imm;
-                if (FULL_SYSTEM &&
+                if (FullSystem &&
                         findOverflow(32, result, Rs, imm)) {
                     fault = new IntegerOverflowFault();
                 }
@@ -2431,7 +2431,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     }
                 }
                 0x3: decode OP default FailUnimpl::rdhwr() {
-                    0x0: decode FULL_SYSTEM {
+                    0x0: decode FullSystem {
                         0: decode RD {
                             29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
                         }
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..d8e5eb111 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -88,14 +88,14 @@ def template CP0Execute {{
 
                 if (isCoprocessorEnabled(xc, 0)) {
                     %(code)s;
+
+                    if(fault == NoFault)
+                    {
+                        %(op_wb)s;
+                    }
                 } else {
                     fault = new CoprocessorUnusableFault(0);
                 }
-
-                if(fault == NoFault)
-                {
-                    %(op_wb)s;
-                }
                 return fault;
         }
 }};
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
             %(op_decl)s;
             %(op_rd)s;
 
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 if (isCoprocessor0Enabled(xc)) {
                     if(isMMUTLB(xc)){
                         %(code)s;
@@ -176,7 +176,7 @@ output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
         {
-            if (!FULL_SYSTEM)
+            if (!FullSystem)
                 return true;
 
             MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
         bool inline
         isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
         {
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
                 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
                 // In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
         isMMUTLB(%(CPU_exec_context)s *xc)
         {
             MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
-            return FULL_SYSTEM && (Config & 0x380) == 0x80;
+            return FullSystem && (Config & 0x380) == 0x80;
         }
 }};
 
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
     bool
     isDspEnabled(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
     }
 }};
 
@@ -151,7 +151,7 @@ output exec {{
     bool
     isDspPresent(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
     }
 }};
 
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
-                if (FULL_SYSTEM)
+                if (FullSystem)
                     fpResetCauseBits(xc);
                 %(op_decl)s;
                 %(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
                     bool invalid_op = false;
-                    if (FULL_SYSTEM) {
+                    if (FullSystem) {
                         invalid_op =
                             fpInvalidOp((FPOp*)this, xc, Fd, traceData);
                     }
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
     CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 0))
                 return new CoprocessorUnusableFault(0);
             else
@@ -210,7 +210,7 @@ output exec {{
     CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 1))
                 return new CoprocessorUnusableFault(1);
             else
@@ -227,7 +227,7 @@ output exec {{
     CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 2))
                 return new CoprocessorUnusableFault(2);
             else
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 4ce03b1c2..d2e9c797e 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -60,6 +60,7 @@ output decoder {{
 #include "base/cprintf.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
+#include "sim/full_system.hh"
 #if defined(linux)
 #include <fenv.h>
 #endif
@@ -92,6 +93,7 @@ output exec {{
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5cef45523..f2a748da9 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -34,10 +34,8 @@
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
-#include "arch/mips/mips_core_specific.hh"
 #include "arch/mips/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst_fwd.hh"
 
 namespace LittleEndianGuest {}
diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc
index 7cfa043e2..f97426f85 100644
--- a/src/arch/mips/linux/system.cc
+++ b/src/arch/mips/linux/system.cc
@@ -47,6 +47,7 @@
 #include "base/loader/symtab.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
 #include "dev/platform.hh"
 #include "kern/linux/events.hh"
 #include "kern/linux/printk.hh"
@@ -62,106 +63,17 @@ using namespace Linux;
 LinuxMipsSystem::LinuxMipsSystem(Params *p)
     : MipsSystem(p)
 {
-    Addr addr = 0;
-
-    /**
-     * The symbol swapper_pg_dir marks the beginning of the kernel and
-     * the location of bootloader passed arguments
-     */
-    if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) {
-        panic("Could not determine start location of kernel");
-    }
-
-    /**
-     * Since we aren't using a bootloader, we have to copy the
-     * kernel arguments directly into the kernel's memory.
-     */
-    virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
-                params()->boot_osflags.length()+1);
-
-    /**
-     * find the address of the est_cycle_freq variable and insert it
-     * so we don't through the lengthly process of trying to
-     * calculated it by using the PIT, RTC, etc.
-     */
-    if (kernelSymtab->findAddress("est_cycle_freq", addr))
-        virtPort.write(addr, (uint64_t)(SimClock::Frequency /
-                    p->boot_cpu_frequency));
-
-    /**
-     * EV5 only supports 127 ASNs so we are going to tell the kernel that the
-     * paritiuclar EV6 we have only supports 127 asns.
-     * @todo At some point we should change ev5.hh and the palcode to support
-     * 255 ASNs.
-     */
-    if (kernelSymtab->findAddress("dp264_mv", addr))
-        virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
-    else
-        panic("could not find dp264_mv\n");
-
-#ifndef NDEBUG
-    kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
-    if (!kernelPanicEvent)
-        panic("could not find kernel symbol \'panic\'");
-
-#endif
-
-    /**
-     * Any time ide_delay_50ms, calibarte_delay or
-     * determine_cpu_caches is called just skip the
-     * function. Currently determine_cpu_caches only is used put
-     * information in proc, however if that changes in the future we
-     * will have to fill in the cache size variables appropriately.
-     */
-
-    skipIdeDelay50msEvent =
-        addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms");
-    skipDelayLoopEvent =
-        addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay");
-    skipCacheProbeEvent =
-        addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches");
-    debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
-    idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle");
-
-    // Disable for now as it runs into panic() calls in VPTr methods
-    // (see sim/vptr.hh).  Once those bugs are fixed, we can
-    // re-enable, but we should find a better way to turn it on than
-    // using DTRACE(Thread), since looking at a trace flag at tick 0
-    // leads to non-intuitive behavior with --trace-start.
-    if (false && kernelSymtab->findAddress("mips_switch_to", addr)) {
-        printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo",
-                                               addr + sizeof(MachInst) * 6);
-    } else {
-        printThreadEvent = NULL;
-    }
 }
 
 LinuxMipsSystem::~LinuxMipsSystem()
 {
-#ifndef NDEBUG
-    delete kernelPanicEvent;
-#endif
-    delete skipIdeDelay50msEvent;
-    delete skipDelayLoopEvent;
-    delete skipCacheProbeEvent;
-    delete debugPrintkEvent;
-    delete idleStartEvent;
-    delete printThreadEvent;
 }
 
 
 void
 LinuxMipsSystem::setDelayLoop(ThreadContext *tc)
 {
-    Addr addr = 0;
-    if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
-        Tick cpuFreq = tc->getCpuPtr()->frequency();
-        Tick intrFreq = platform->intrFrequency();
-        FSTranslatingPortProxy* vp;
-
-        vp = tc->getVirtProxy();
-        vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
-    }
+    panic("setDelayLoop not implemented.\n");
 }
 
 
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cd269f1af..8678eb7e4 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -34,34 +34,14 @@
 #ifndef __ARCH_MIPS_PAGETABLE_H__
 #define __ARCH_MIPS_PAGETABLE_H__
 
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
 
 namespace MipsISA {
 
 struct VAddr
 {
-    static const int ImplBits = 43;
-    static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
-    static const Addr UnImplMask = ~ImplMask;
-
-    VAddr(Addr a) : addr(a) {}
-    Addr addr;
-    operator Addr() const { return addr; }
-    const VAddr &operator=(Addr a) { addr = a; return *this; }
-
-    Addr vpn() const { return (addr & ImplMask) >> PageShift; }
-    Addr page() const { return addr & Page_Mask; }
-    Addr offset() const { return addr & PageOffset; }
-
-    Addr level3() const
-    { return MipsISA::PteAddr(addr >> PageShift); }
-    Addr level2() const
-    { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
-    Addr level1() const
-    { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
 };
 
 // ITB/DTB page table entry
@@ -98,6 +78,33 @@ struct PTE
     void unserialize(Checkpoint *cp, const std::string &section);
 };
 
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+    Addr _pageStart;
+    TlbEntry() {}
+    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+    Addr pageStart()
+    {
+        return _pageStart;
+    }
+
+    void
+    updateVaddr(Addr new_vaddr) {}
+
+    void serialize(std::ostream &os)
+    {
+        SERIALIZE_SCALAR(_pageStart);
+    }
+
+    void unserialize(Checkpoint *cp, const std::string &section)
+    {
+        UNSERIALIZE_SCALAR(_pageStart);
+    }
+
+};
+
 };
 #endif // __ARCH_MIPS_PAGETABLE_H__
 
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 1fd157758..656cb8cbb 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -137,12 +137,12 @@
 
 #include "arch/mips/remote_gdb.hh"
 #include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
 #include "cpu/decode.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
 #include "mem/page_table.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace MipsISA;
@@ -158,13 +158,13 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-#if FULL_SYSTEM
-    panic("acc not implemented for MIPS FS!");
-#endif
     TlbEntry entry;
     //Check to make sure the first byte is mapped into the processes address
     //space.
-    return context->getProcessPtr()->pTable->lookup(va, entry);
+    if (FullSystem)
+        panic("acc not implemented for MIPS FS!");
+    else
+        return context->getProcessPtr()->pTable->lookup(va, entry);
 }
 
 /*
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index ced60b88e..d4548b4bb 100644
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -37,6 +37,7 @@
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "mem/fs_translating_port_proxy.hh"
 #include "sim/system.hh"
 
 using namespace std;
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index c1735b740..f0d4c250e 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -45,77 +45,12 @@ using namespace LittleEndianGuest;
 
 MipsSystem::MipsSystem(Params *p) : System(p)
 {
-
-#if FULL_SYSTEM
-    if (p->bare_iron == true) {
-        hexFile = new HexFile(params()->hex_file_name);
-        if (!hexFile->loadSections(functionalPort))
-            panic("Could not load hex file\n");
-    }
-
-    Addr addr = 0;
-
-    consoleSymtab = new SymbolTable;
-
-
-    /**
-     * Load the console code into memory
-     */
-    //    Load Console Code
-    console = createObjectFile(params()->console);
-
-    warn("console code is located at: %s\n", params()->console);
-
-    if (console == NULL)
-        fatal("Could not load console file %s", params()->console);
-    //Load program sections into memory
-    console->loadSections(functionalPort, loadAddrMask);
-
-    //load symbols
-    if (!console->loadGlobalSymbols(consoleSymtab))
-        panic("could not load console symbols\n");
-
-    if (!console->loadGlobalSymbols(debugSymbolTable))
-        panic("could not load console symbols\n");
-
-
-#ifndef NDEBUG
-    consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
-#endif
-
-    /**
-     * Copy the osflags (kernel arguments) into the consoles
-     * memory. (Presently Linux does not use the console service
-     * routine to get these command line arguments, but Tru64 and
-     * others do.)
-     */
-    if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
-        warn("writing addr starting from %#x", addr);
-        virtPort->writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
-                strlen(params()->boot_osflags.c_str()));
-    }
-
-    /**
-     * Set the hardware reset parameter block system type and revision
-     * information to Tsunami.
-     */
-    if (consoleSymtab->findAddress("m5_rpb", addr)) {
-        uint64_t data;
-        data = htog(params()->system_type);
-        virtPort->write(addr + 0x50, data);
-        data = htog(params()->system_rev);
-        virtPort->write(addr + 0x58, data);
-    } else {
-        panic("could not find hwrpb\n");
-    }
-#endif
 }
 
 MipsSystem::~MipsSystem()
 {
 }
 
-#if FULL_SYSTEM
 Addr
 MipsSystem::fixFuncEventAddr(Addr addr)
 {
@@ -126,8 +61,6 @@ void
 MipsSystem::setMipsAccess(Addr access)
 {}
 
-#endif
-
 bool
 MipsSystem::breakpoint()
 {
diff --git a/src/arch/mips/system.hh b/src/arch/mips/system.hh
index 128f36581..fcaceadcd 100755
--- a/src/arch/mips/system.hh
+++ b/src/arch/mips/system.hh
@@ -66,7 +66,6 @@ class MipsSystem : public System
      */
     void setMipsAccess(Addr access);
 
-#if FULL_SYSTEM
     /** console symbol table */
     SymbolTable *consoleSymtab;
 
@@ -75,7 +74,6 @@ class MipsSystem : public System
 
     /** Used by some Bare Iron Configurations */
     HexFile *hexFile;
-#endif
 
 #ifndef NDEBUG
   /** Event to halt the simulator if the console calls panic() */
@@ -85,9 +83,7 @@ class MipsSystem : public System
   protected:
     const Params *params() const { return (const Params *)_params; }
 
-
-#if FULL_SYSTEM
-  /** Add a function-based event to the console code. */
+    /** Add a function-based event to the console code. */
     template <class T>
     T *
     addConsoleFuncEvent(const char *lbl)
@@ -96,7 +92,6 @@ class MipsSystem : public System
     }
 
     virtual Addr fixFuncEventAddr(Addr addr);
-#endif
 
 };
 
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index b3ed09621..cd6d47d1e 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -295,7 +295,9 @@ TLB::regStats()
 Fault
 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
-#if !FULL_SYSTEM
+    if (FullSystem)
+        panic("translateInst not implemented in MIPS.\n");
+
     Process * p = tc->getProcessPtr();
 
     Fault fault = p->pTable->translate(req);
@@ -303,93 +305,13 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
         return fault;
 
     return NoFault;
-#else
-    Addr vaddr = req->getVaddr();
-
-    bool misaligned = (req->getSize() - 1) & vaddr;
-
-    if (IsKSeg0(vaddr)) {
-        // Address will not be translated through TLB, set response, and go!
-        req->setPaddr(KSeg02Phys(vaddr));
-        if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
-                misaligned) {
-            return new AddressErrorFault(vaddr, false);
-        }
-    } else if(IsKSeg1(vaddr)) {
-        // Address will not be translated through TLB, set response, and go!
-        req->setPaddr(KSeg02Phys(vaddr));
-    } else {
-      /* 
-       * This is an optimization - smallPages is updated every time a TLB
-       * operation is performed. That way, we don't need to look at
-       * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
-       */
-      Addr VPN;
-      if (smallPages == 1) {
-        VPN = (vaddr >> 11);
-      } else {
-        VPN = ((vaddr >> 11) & 0xFFFFFFFC);
-      }
-      uint8_t Asid = req->getAsid();
-      if (misaligned) {
-          // Unaligned address!
-          return new AddressErrorFault(vaddr, false);
-      }
-      PTE *pte = lookup(VPN,Asid);
-      if (pte != NULL) {
-          // Ok, found something
-          /* Check for valid bits */
-          int EvenOdd;
-          bool Valid;
-          if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) {
-              // Check even bits
-              Valid = pte->V0;
-              EvenOdd = 0;
-          } else {
-              // Check odd bits
-              Valid = pte->V1;
-              EvenOdd = 1;
-          }
-
-          if (Valid == false) {
-              return new TlbInvalidFault(Asid, vaddr, VPN, false);
-          } else {
-              // Ok, this is really a match, set paddr
-              Addr PAddr;
-              if (EvenOdd == 0) {
-                PAddr = pte->PFN0;
-              } else {
-                PAddr = pte->PFN1;
-              }
-              PAddr >>= (pte->AddrShiftAmount - 12);
-              PAddr <<= pte->AddrShiftAmount;
-              PAddr |= (vaddr & pte->OffsetMask);
-              req->setPaddr(PAddr);
-            }
-        } else {
-            // Didn't find any match, return a TLB Refill Exception
-            return new TlbRefillFault(Asid, vaddr, VPN, false);
-        }
-    }
-    return checkCacheability(req);
-#endif
 }
 
 Fault
 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 {
-#if !FULL_SYSTEM
-    //@TODO: This should actually use TLB instead of going directly
-    //       to the page table in syscall mode.
-    /**
-     * Check for alignment faults
-     */
-    if (req->getVaddr() & (req->getSize() - 1)) {
-        DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
-                req->getSize());
-        return new AddressErrorFault(req->getVaddr(), write);
-    }
-
+    if (FullSystem)
+        panic("translateData not implemented in MIPS.\n");
 
     Process * p = tc->getProcessPtr();
 
@@ -398,79 +320,6 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
         return fault;
 
     return NoFault;
-#else
-    Addr vaddr = req->getVaddr();
-
-    bool misaligned = (req->getSize() - 1) & vaddr;
-
-    if (IsKSeg0(vaddr)) {
-        // Address will not be translated through TLB, set response, and go!
-        req->setPaddr(KSeg02Phys(vaddr));
-        if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
-                misaligned) {
-            return new AddressErrorFault(vaddr, true);
-        }
-    } else if(IsKSeg1(vaddr)) {
-      // Address will not be translated through TLB, set response, and go!
-      req->setPaddr(KSeg02Phys(vaddr));
-    } else {
-        /* 
-         * This is an optimization - smallPages is updated every time a TLB
-         * operation is performed. That way, we don't need to look at
-         * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
-         */
-        Addr VPN = (vaddr >> 11) & 0xFFFFFFFC;
-        if (smallPages == 1) {
-            VPN = vaddr >> 11;
-        }
-        uint8_t Asid = req->getAsid();
-        PTE *pte = lookup(VPN, Asid);
-        if (misaligned) {
-            return new AddressErrorFault(vaddr, true);
-        }
-        if (pte != NULL) {
-            // Ok, found something
-            /* Check for valid bits */
-            int EvenOdd;
-            bool Valid;
-            bool Dirty;
-            if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) {
-                // Check even bits
-                Valid = pte->V0;
-                Dirty = pte->D0;
-                EvenOdd = 0;
-            } else {
-                // Check odd bits
-                Valid = pte->V1;
-                Dirty = pte->D1;
-                EvenOdd = 1;
-            }
-
-            if (Valid == false) {
-                return new TlbInvalidFault(Asid, vaddr, VPN, write);
-            } else {
-                // Ok, this is really a match, set paddr
-                if (!Dirty && write) {
-                    return new TlbModifiedFault(Asid, vaddr, VPN);
-                }
-                Addr PAddr;
-                if (EvenOdd == 0) {
-                    PAddr = pte->PFN0;
-                } else {
-                    PAddr = pte->PFN1;
-                }
-                PAddr >>= (pte->AddrShiftAmount - 12);
-                PAddr <<= pte->AddrShiftAmount;
-                PAddr |= (vaddr & pte->OffsetMask);
-                req->setPaddr(PAddr);
-            }
-        } else {
-            // Didn't find any match, return a TLB Refill Exception
-            return new TlbRefillFault(Asid, vaddr, VPN, write);
-        }
-    }
-    return checkCacheability(req);
-#endif
 }
 
 Fault
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4b1456862..834431536 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -55,33 +55,6 @@ class ThreadContext;
    simply create an ITLB and DTLB that will point to the real TLB */
 namespace MipsISA {
 
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
-    Addr _pageStart;
-    TlbEntry() {}
-    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
-    Addr pageStart()
-    {
-        return _pageStart;
-    }
-
-    void
-    updateVaddr(Addr new_vaddr) {}
-    
-    void serialize(std::ostream &os)
-    {
-        SERIALIZE_SCALAR(_pageStart);
-    }
-
-    void unserialize(Checkpoint *cp, const std::string &section)
-    {
-        UNSERIALIZE_SCALAR(_pageStart);
-    }
-
-};
-
 class TLB : public BaseTLB
 {
   protected:
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index fc6e9e2f9..65432b4ea 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -31,19 +31,15 @@
 #include <cmath>
 
 #include "arch/mips/isa_traits.hh"
+#include "arch/mips/registers.hh"
 #include "arch/mips/utility.hh"
+#include "arch/mips/vtophys.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "sim/serialize.hh"
-
-#if FULL_SYSTEM
-#include "arch/mips/registers.hh"
-#include "arch/mips/vtophys.hh"
 #include "mem/fs_translating_port_proxy.hh"
-#endif
+#include "sim/serialize.hh"
 
 
 using namespace MipsISA;
@@ -54,23 +50,8 @@ namespace MipsISA {
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
-    if (number < 4) {
-        if (fp)
-            return tc->readFloatRegBits(FirstArgumentReg + number);
-        else
-            return tc->readIntReg(FirstArgumentReg + number);
-    } else {
-        Addr sp = tc->readIntReg(StackPointerReg);
-        FSTranslatingPortProxy* vp = tc->getVirtProxy();
-        uint64_t arg = vp->read<uint64_t>(sp +
-                (number - 4) * sizeof(uint64_t));
-        return arg;
-    }
-#else
-    panic("getArgument() is Full system only\n");
+    panic("getArgument() not implemented\n");
     M5_DUMMY_RETURN
-#endif
 }
 
 uint64_t
@@ -254,6 +235,10 @@ startupCPU(ThreadContext *tc, int cpuId)
 }
 
 void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
     panic("Copy Regs Not Implemented Yet\n");
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a2995b098..876066203 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -37,7 +37,6 @@
 #include "arch/mips/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
@@ -108,6 +107,7 @@ RoundPage(Addr addr)
 // CPU Utility
 //
 void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index 08e1a1e1c..60d9bc1ba 100755
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -37,7 +37,7 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "debug/VtoPhys.hh"
 
 using namespace std;
 using namespace MipsISA;
@@ -45,25 +45,13 @@ using namespace MipsISA;
 Addr
 MipsISA::vtophys(Addr vaddr)
 {
-    Addr paddr = 0;
-    if (MipsISA::IsUSeg(vaddr))
-        DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
-    else if (MipsISA::IsKSeg0(vaddr))
-        paddr = MipsISA::KSeg02Phys(vaddr);
-    else if(MipsISA::IsKSeg1(vaddr))
-        paddr = MipsISA::KSeg12Phys(vaddr);
-    else
-        panic("vtophys: ptbr is not set on "
-                "virtual lookup for vaddr %#x", vaddr);
-
-    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
-    return paddr;
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
+    return 0;
 }
 
 Addr
 MipsISA::vtophys(ThreadContext *tc, Addr addr)
 {
-  fatal("VTOPHYS: Unimplemented on MIPS\n");
+    fatal("VTOPHYS: Unimplemented on MIPS\n");
 }
 
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 5ecc30b1f..37a7378a8 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -41,24 +41,6 @@ class ThreadContext;
 class FunctionalPort;
 
 namespace MipsISA {
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-    // User Virtual
-    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
-    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
-
-    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
-
-    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
-
-    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
-
-    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
-
-    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
-
-
     Addr vtophys(Addr vaddr);
     Addr vtophys(ThreadContext *tc, Addr vaddr);
 
diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py
new file mode 100644
index 000000000..82d614077
--- /dev/null
+++ b/src/arch/power/PowerInterrupts.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+    type = 'PowerInterrupts'
+    cxx_class = 'PowerISA::Interrupts'
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index f96f12757..7f893ca37 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -40,17 +40,20 @@ if env['TARGET_ISA'] == 'power':
     Source('insts/floating.cc')
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
     Source('pagetable.cc')
+    Source('process.cc')
+    Source('stacktrace.cc')
     Source('tlb.cc')
     Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('PowerInterrupts.py')
     SimObject('PowerTLB.py')
-    DebugFlag('Power')
 
-    if not env['FULL_SYSTEM']:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
+    DebugFlag('Power')
 
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/power/interrupts.cc
index 31d47c842..c9ef36824 100755..100644
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/power/interrupts.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002, 2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Google
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,22 +25,13 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Nathan Binkert
- *          Steve Reinhardt
+ * Authors: Gabe Black
  */
 
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
+#include "arch/power/interrupts.hh"
 
-#if FULL_SYSTEM
-
-////////////////////////////////////////////////////////////////////////
-//
-//  Machine dependent functions
-//
-void
-MipsISA::initCPU(ThreadContext *tc, int cpuId)
-{}
-
-#endif // FULL_SYSTEM || BARE_IRON
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+    return new PowerISA::Interrupts(this);
+}
diff --git a/src/arch/power/interrupts.hh b/src/arch/power/interrupts.hh
new file mode 100644
index 000000000..9c11c8e8a
--- /dev/null
+++ b/src/arch/power/interrupts.hh
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+  private:
+    BaseCPU * cpu;
+
+  public:
+    typedef PowerInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p), cpu(NULL)
+    {}
+
+    void
+    setCPU(BaseCPU * _cpu)
+    {
+        cpu = _cpu;
+    }
+
+    void
+    post(int int_num, int index)
+    {
+        panic("Interrupts::post not implemented.\n");
+    }
+
+    void
+    clear(int int_num, int index)
+    {
+        panic("Interrupts::clear not implemented.\n");
+    }
+
+    void
+    clearAll()
+    {
+        panic("Interrupts::clearAll not implemented.\n");
+    }
+
+    bool
+    checkInterrupts(ThreadContext *tc) const
+    {
+        panic("Interrupts::checkInterrupts not implemented.\n");
+    }
+
+    Fault
+    getInterrupt(ThreadContext *tc)
+    {
+        panic("Interrupts::getInterrupt not implemented.\n");
+    }
+
+    void
+    updateIntrInfo(ThreadContext *tc)
+    {
+        panic("Interrupts::updateIntrInfo not implemented.\n");
+    }
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_INTERRUPT_HH__
+
diff --git a/src/arch/power/kernel_stats.hh b/src/arch/power/kernel_stats.hh
new file mode 100644
index 000000000..b4d9a69b6
--- /dev/null
+++ b/src/arch/power/kernel_stats.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_KERNEL_STATS_HH__
+#define __ARCH_POWER_KERNEL_STATS_HH__
+
+#include "kern/kernel_stats.hh"
+
+namespace PowerISA {
+namespace Kernel {
+
+enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num };
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
+{
+  public:
+    Statistics(System *system) : ::Kernel::Statistics(system)
+    {}
+};
+
+} // namespace PowerISA::Kernel
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_KERNEL_STATS_HH__
diff --git a/src/arch/power/pagetable.hh b/src/arch/power/pagetable.hh
index a5f18eba9..3097aa526 100644
--- a/src/arch/power/pagetable.hh
+++ b/src/arch/power/pagetable.hh
@@ -41,7 +41,6 @@
 #include "arch/power/isa_traits.hh"
 #include "arch/power/utility.hh"
 #include "arch/power/vtophys.hh"
-#include "config/full_system.hh"
 
 namespace PowerISA {
 
diff --git a/src/arch/power/stacktrace.cc b/src/arch/power/stacktrace.cc
new file mode 100644
index 000000000..5fcb6342c
--- /dev/null
+++ b/src/arch/power/stacktrace.cc
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/power/stacktrace.hh"
+#include "base/trace.hh"
+
+using namespace std;
+
+namespace PowerISA {
+
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+    : tc(_tc)
+{
+    panic("ProcessInfo constructor not implemented.\n");
+}
+
+Addr
+ProcessInfo::task(Addr ksp) const
+{
+    panic("ProcessInfo::task not implemented.\n");
+    return 0;
+}
+
+int
+ProcessInfo::pid(Addr ksp) const
+{
+    panic("ProcessInfo::pid not implemented.\n");
+    return 0;
+}
+
+string
+ProcessInfo::name(Addr ksp) const
+{
+    panic("ProcessInfo::name not implemented.\n");
+    return "";
+}
+
+StackTrace::StackTrace()
+    : tc(0), stack(64)
+{
+    panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+    : tc(0), stack(64)
+{
+    panic("StackTrace constructor not implemented.\n");
+}
+
+StackTrace::~StackTrace()
+{
+    panic("StackTrace destructor not implemented.\n");
+}
+
+void
+StackTrace::trace(ThreadContext *_tc, bool is_call)
+{
+    panic("StackTrace::trace not implemented.\n");
+}
+
+bool
+StackTrace::isEntry(Addr addr)
+{
+    panic("StackTrace::isEntry not implemented.\n");
+    return false;
+}
+
+bool
+StackTrace::decodeStack(MachInst inst, int &disp)
+{
+    panic("StackTrace::decodeStack not implemented.\n");
+    return false;
+}
+
+bool
+StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+{
+    panic("StackTrace::decodeSave not implemented.\n");
+    return true;
+}
+
+/*
+ * Decode the function prologue for the function we're in, and note
+ * which registers are stored where, and how large the stack frame is.
+ */
+bool
+StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size,
+                           Addr &ra)
+{
+    panic("StackTrace::decodePrologue not implemented.\n");
+    return true;
+}
+
+#if TRACING_ON
+void
+StackTrace::dump()
+{
+    panic("StackTrace::dump not implemented.\n");
+}
+#endif
+
+} // namespace PowerISA
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 0b3edd5a2..9f535e9e5 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -50,6 +50,7 @@
 #include "debug/TLB.hh"
 #include "mem/page_table.hh"
 #include "params/PowerTLB.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
 using namespace std;
@@ -308,14 +309,13 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
-#if !FULL_SYSTEM
+    if (FullSystem)
+        fatal("translate atomic not yet implemented in full system mode.\n");
+
     if (mode == Execute)
         return translateInst(req, tc);
     else
         return translateData(req, tc, mode == Write);
-#else
-  fatal("translate atomic not yet implemented\n");
-#endif
 }
 
 void
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index b02ccda08..e3fa246fc 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -55,11 +55,24 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->pcState(src->pcState());
 }
 
+uint64_t
+getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
+{
+    panic("getArgument not implemented for POWER.\n");
+    return 0;
+}
+
 void
 skipFunction(ThreadContext *tc)
 {
     panic("Not Implemented for POWER");
 }
 
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+    panic("initCPU not implemented for POWER.\n");
+}
+
 
 } // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 349054774..c3868c189 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,6 +78,8 @@ advancePC(PCState &pc, const StaticInstPtr inst)
     pc.advance();
 }
 
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
 static inline bool
 inUserMode(ThreadContext *tc)
 {
@@ -90,6 +92,8 @@ getExecutingAsid(ThreadContext *tc)
     return 0;
 }
 
+void initCPU(ThreadContext *, int cpuId);
+
 } // namespace PowerISA
 
 
diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/power/vtophys.cc
index bd66e049f..b03f507fc 100644..100755
--- a/src/arch/mips/mips_core_specific.hh
+++ b/src/arch/power/vtophys.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2012 Google
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,18 +25,22 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Gabe Black
  */
 
-#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
-#define __ARCH_MIPS_CORE_SPECIFIC_HH__
+#include "arch/power/vtophys.hh"
 
-#include "arch/mips/isa_traits.hh"
+using namespace std;
 
-class ThreadContext;
+Addr
+PowerISA::vtophys(Addr vaddr)
+{
+    fatal("vtophys: Unimplemented on POWER\n");
+}
 
-namespace MipsISA {
-    void initCPU(ThreadContext *tc, int cpuId);
-};
+Addr
+PowerISA::vtophys(ThreadContext *tc, Addr addr)
+{
+    fatal("vtophys: Unimplemented on POWER\n");
+}
 
-#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 7371f38a6..a2582b296 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -44,6 +44,9 @@ class FunctionalPort;
 
 namespace PowerISA {
 
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
 inline Addr
 PteAddr(Addr a)
 {
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cc13d56af..75a3590e7 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -34,37 +34,31 @@ Import('*')
 if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/syscalls.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
+    Source('process.cc')
     Source('remote_gdb.cc')
+    Source('solaris/process.cc')
+    Source('solaris/solaris.cc')
+    Source('system.cc')
     Source('tlb.cc')
+    Source('ua2005.cc')
     Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('SparcInterrupts.py')
     SimObject('SparcNativeTrace.py')
-
+    SimObject('SparcSystem.py')
     SimObject('SparcTLB.py')
+
     DebugFlag('Sparc', "Generic SPARC ISA stuff")
     DebugFlag('RegisterWindows', "Register window manipulation")
 
-    if env['FULL_SYSTEM']:
-        SimObject('SparcSystem.py')
-        SimObject('SparcInterrupts.py')
-
-        Source('interrupts.cc')
-        Source('system.cc')
-        Source('ua2005.cc')
-        Source('vtophys.cc')
-    else:
-        Source('process.cc')
-
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-        Source('linux/syscalls.cc')
-
-        Source('solaris/process.cc')
-        Source('solaris/solaris.cc')
-
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
     # Only non-header files need to be compiled.
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 01d57e627..e67b8c50e 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -33,17 +33,16 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/process.hh"
 #include "arch/sparc/types.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
+#include "sim/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
-#if !FULL_SYSTEM
-#include "arch/sparc/process.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -494,12 +493,13 @@ getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
     NPC = PC + sizeof(MachInst);
 }
 
-#if FULL_SYSTEM
-
 void
 SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
+    if (!FullSystem)
+        return;
+
     countStat()++;
 
     // We can refer to this to see what the trap level -was-, but something
@@ -619,11 +619,14 @@ PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
     */
 }
 
-#else // !FULL_SYSTEM
-
 void
 FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        SparcFaultBase::invoke(tc, inst);
+        return;
+    }
+
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
     bool success = p->pTable->lookup(vaddr, entry);
@@ -639,6 +642,11 @@ FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        SparcFaultBase::invoke(tc, inst);
+        return;
+    }
+
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
     bool success = p->pTable->lookup(vaddr, entry);
@@ -658,6 +666,11 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        SparcFaultBase::invoke(tc, inst);
+        return;
+    }
+
     doNormalFault(tc, trapType(), false);
 
     Process *p = tc->getProcessPtr();
@@ -673,6 +686,11 @@ SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
+    if (FullSystem) {
+        SparcFaultBase::invoke(tc, inst);
+        return;
+    }
+
     doNormalFault(tc, trapType(), false);
 
     Process *p = tc->getProcessPtr();
@@ -688,9 +706,14 @@ FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 void
 TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
-    // In SE, this mechanism is how the process requests a service from the
-    // operating system. We'll get the process object from the thread context
-    // and let it service the request.
+    if (FullSystem) {
+        SparcFaultBase::invoke(tc, inst);
+        return;
+    }
+
+    // In SE, this mechanism is how the process requests a service from
+    // the operating system. We'll get the process object from the thread
+    // context and let it service the request.
 
     Process *p = tc->getProcessPtr();
 
@@ -706,7 +729,5 @@ TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
     tc->pcState(pc);
 }
 
-#endif
-
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 88c269d66..148983f4f 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -32,7 +32,6 @@
 #ifndef __SPARC_FAULTS_HH__
 #define __SPARC_FAULTS_HH__
 
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/faults.hh"
 
@@ -66,10 +65,8 @@ class SparcFaultBase : public FaultBase
         const PrivilegeLevel nextPrivilegeLevel[NumLevels];
         FaultStat count;
     };
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     virtual TrapType trapType() = 0;
     virtual FaultPriority priority() = 0;
     virtual FaultStat & countStat() = 0;
@@ -96,10 +93,8 @@ class SparcFault : public SparcFaultBase
 
 class PowerOnReset : public SparcFault<PowerOnReset>
 {
-#if FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -204,28 +199,28 @@ class VAWatchpoint : public SparcFault<VAWatchpoint> {};
 class FastInstructionAccessMMUMiss :
     public SparcFault<FastInstructionAccessMMUMiss>
 {
-#if !FULL_SYSTEM
   protected:
     Addr vaddr;
   public:
     FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
+    FastInstructionAccessMMUMiss() : vaddr(0)
+    {}
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
 {
-#if !FULL_SYSTEM
   protected:
     Addr vaddr;
   public:
     FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
+    FastDataAccessMMUMiss() : vaddr(0)
+    {}
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
@@ -243,10 +238,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
   public:
     SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
     // These need to be handled specially to enable spill traps in SE
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class SpillNOther : public EnumeratedFault<SpillNOther>
@@ -262,10 +255,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
     FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n)
     {}
     // These need to be handled specially to enable fill traps in SE
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 class FillNOther : public EnumeratedFault<FillNOther>
@@ -281,10 +272,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
     TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n)
     {}
     // In SE, trap instructions are requesting services from the OS.
-#if !FULL_SYSTEM
     void invoke(ThreadContext * tc,
             StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
 };
 
 } // namespace SparcISA
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 6c9be8164..13f252e82 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -32,7 +32,6 @@
 #include "arch/sparc/isa.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MiscRegs.hh"
@@ -136,12 +135,10 @@ ISA::clear()
     nres_error_head = 0;
     nres_error_tail = 0;
 
-#if FULL_SYSTEM
     // If one of these events is active, it's not obvious to me how to get
     // rid of it cleanly. For now we'll just assert that they're not.
     if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
         panic("Tick comparison event active when clearing the ISA object.\n");
-#endif
 }
 
 MiscReg
@@ -346,20 +343,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
       case MISCREG_QUEUE_RES_ERROR_TAIL:
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
       case MISCREG_HPSTATE:
         return readFSReg(miscReg, tc);
-#else
-      case MISCREG_HPSTATE:
-        // HPSTATE is special because because sometimes in privilege
-        // checks for instructions it will read HPSTATE to make sure
-        // the priv. level is ok So, we'll just have to tell it it
-        // isn't, instead of panicing.
-        return 0;
-
-      panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
-#endif
-
     }
     return readMiscRegNoEffect(miscReg);
 }
@@ -569,12 +554,10 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
         return;
       case MISCREG_TL:
         tl = val;
-#if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
             tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
         return;
       case MISCREG_CWP:
         new_val = val >= NWindows ? NWindows - 1 : val;
@@ -610,18 +593,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
       case MISCREG_QUEUE_RES_ERROR_TAIL:
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-#if FULL_SYSTEM
       case MISCREG_HPSTATE:
         setFSReg(miscReg, val, tc);
         return;
-#else
-      case MISCREG_HPSTATE:
-        // HPSTATE is special because normal trap processing saves HPSTATE when
-        // it goes into a trap, and restores it when it returns.
-        return;
-      panic("Accessing Fullsystem register %d to %#x in SE mode\n",
-              miscReg, val);
-#endif
     }
     setMiscRegNoEffect(miscReg, new_val);
 }
@@ -667,7 +641,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
     SERIALIZE_SCALAR(res_error_tail);
     SERIALIZE_SCALAR(nres_error_head);
     SERIALIZE_SCALAR(nres_error_tail);
-#if FULL_SYSTEM
     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
     ThreadContext *tc = NULL;
     BaseCPU *cpu = NULL;
@@ -701,7 +674,6 @@ ISA::serialize(EventManager *em, std::ostream &os)
         SERIALIZE_SCALAR(stick_cmp);
         SERIALIZE_SCALAR(hstick_cmp);
     }
-#endif
 }
 
 void
@@ -747,7 +719,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(nres_error_head);
     UNSERIALIZE_SCALAR(nres_error_tail);
 
-#if FULL_SYSTEM
     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
     ThreadContext *tc = NULL;
     BaseCPU *cpu = NULL;
@@ -778,7 +749,6 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
         }
     }
 
- #endif
 }
 
 }
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index f00068bbc..e5d258786 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -36,7 +36,6 @@
 
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
-#include "config/full_system.hh"
 #include "cpu/cpuevent.hh"
 
 class Checkpoint;
@@ -114,7 +113,6 @@ class ISA
 
     // These need to check the int_dis field and if 0 then
     // set appropriate bit in softint and checkinterrutps on the cpu
-#if FULL_SYSTEM
     void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
     MiscReg readFSReg(int miscReg, ThreadContext * tc);
 
@@ -138,7 +136,6 @@ class ISA
     typedef CpuEventWrapper<ISA,
             &ISA::processHSTickCompare> HSTickCompareEvent;
     HSTickCompareEvent *hSTickCompare;
-#endif
 
     static const int NumGlobalRegs = 8;
     static const int NumWindowedRegs = 24;
@@ -205,11 +202,9 @@ class ISA
 
     ISA()
     {
-#if FULL_SYSTEM
         tickCompare = NULL;
         sTickCompare = NULL;
         hSTickCompare = NULL;
-#endif
 
         clear();
     }
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index a42c96ab1..d38df1c25 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -566,7 +566,7 @@ output exec {{
     static inline Fault
     checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
                 xc->readMiscReg(MISCREG_FPRS) & 0x4) {
                 return NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 0ca56252e..a77059181 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -326,7 +326,7 @@ let {{
     '''
 
     TruncateEA = '''
-        if (!FULL_SYSTEM)
+        if (!FullSystem)
             EA = Pstate<3:> ? EA<31:0> : EA;
     '''
 }};
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 0c49cee16..541254d51 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -74,6 +74,7 @@ output exec {{
 #include "debug/Sparc.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
+#include "sim/full_system.hh"
 #include "sim/pseudo_inst.hh"
 #include "sim/sim_exit.hh"
 
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 620d9c402..9b02a4d80 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -35,7 +35,6 @@
 #include "arch/sparc/sparc_traits.hh"
 #include "arch/sparc/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst_fwd.hh"
 
 namespace BigEndianGuest {}
@@ -78,7 +77,6 @@ const Addr VAddrAMask = ULL(0xFFFFFFFF);
 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
 const Addr BytesInPageMask = ULL(0x1FFF);
 
-#if FULL_SYSTEM
 enum InterruptTypes
 {
     IT_TRAP_LEVEL_ZERO,
@@ -91,8 +89,6 @@ enum InterruptTypes
     NumInterruptTypes
 };
 
-#endif
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 }
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259..c13fdc910 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -38,7 +38,6 @@
  */
 
 #include "arch/sparc/tlb.hh"
-#include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 
@@ -48,21 +47,13 @@ namespace SparcISA
 inline Tick
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 inline Tick
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 43320196b..aba17e505 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -36,7 +36,6 @@
 #include "arch/sparc/isa_traits.hh"
 #include "base/bitfield.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 
 class Checkpoint;
 
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index 712314e01..ece6ec963 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -127,7 +127,6 @@
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "debug/GDBRead.hh"
@@ -135,6 +134,7 @@
 #include "mem/physical.hh"
 #include "mem/port.hh"
 #include "sim/byteswap.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
 
@@ -156,18 +156,18 @@ RemoteGDB::acc(Addr va, size_t len)
     //@Todo In NetBSD, this function checks if all addresses
     // from va to va + len have valid page map entries. Not
     // sure how this will work for other OSes or in general.
-#if FULL_SYSTEM
-    if (va)
-        return true;
-    return false;
-#else
-    TlbEntry entry;
-    // Check to make sure the first byte is mapped into the processes address
-    // space.
-    if (context->getProcessPtr()->pTable->lookup(va, entry))
-        return true;
-    return false;
-#endif
+    if (FullSystem) {
+        if (va)
+            return true;
+        return false;
+    } else {
+        TlbEntry entry;
+        // Check to make sure the first byte is mapped into the processes
+        // address space.
+        if (context->getProcessPtr()->pTable->lookup(va, entry))
+            return true;
+        return false;
+    }
 }
 
 ///////////////////////////////////////////////////////////
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3b..a6179e0f8 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -42,6 +42,7 @@
 #include "debug/TLB.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
@@ -497,14 +498,14 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
 
     if (e == NULL || !e->valid) {
         writeTagAccess(vaddr, context);
-        if (real)
+        if (real) {
             return new InstructionRealTranslationMiss;
-        else
-#if FULL_SYSTEM
-            return new FastInstructionAccessMMUMiss;
-#else
-            return new FastInstructionAccessMMUMiss(req->getVaddr());
-#endif
+        } else {
+            if (FullSystem)
+                return new FastInstructionAccessMMUMiss;
+            else
+                return new FastInstructionAccessMMUMiss(req->getVaddr());
+        }
     }
 
     // were not priviledged accesing priv page
@@ -709,14 +710,14 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
     if (e == NULL || !e->valid) {
         writeTagAccess(vaddr, context);
         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
-        if (real)
+        if (real) {
             return new DataRealTranslationMiss;
-        else
-#if FULL_SYSTEM
-            return new FastDataAccessMMUMiss;
-#else
-            return new FastDataAccessMMUMiss(req->getVaddr());
-#endif
+        } else {
+            if (FullSystem)
+                return new FastDataAccessMMUMiss;
+            else
+                return new FastDataAccessMMUMiss(req->getVaddr());
+        }
 
     }
 
@@ -840,8 +841,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-#if FULL_SYSTEM
-
 Tick
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
@@ -1280,8 +1279,6 @@ doMmuWriteError:
     return tc->getCpuPtr()->ticks(1);
 }
 
-#endif
-
 void
 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b64..cefa38175 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,7 +34,6 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
-#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "params/SparcTLB.hh"
 #include "sim/fault_fwd.hh"
@@ -48,11 +47,9 @@ namespace SparcISA
 
 class TLB : public BaseTLB
 {
-#if !FULL_SYSTEM
     // These faults need to be able to populate the tlb in SE mode.
     friend class FastInstructionAccessMMUMiss;
     friend class FastDataAccessMMUMiss;
-#endif
 
     // TLB state
   protected:
@@ -167,10 +164,8 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
-#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 67c17900b..e6ab64de9 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -36,6 +36,7 @@
 #include "debug/Quiesce.hh"
 #include "debug/Timer.hh"
 #include "sim/system.hh"
+#include "sim/full_system.hh"
 
 using namespace SparcISA;
 using namespace std;
@@ -207,12 +208,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_HPSTATE:
         // T1000 spec says impl. dependent val must always be 1
         setMiscRegNoEffect(miscReg, val | HPSTATE::id);
-#if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
             cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
-#endif
         break;
       case MISCREG_HTSTATE:
         setMiscRegNoEffect(miscReg, val);
@@ -226,7 +225,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
             DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
             // Time to go to sleep
             tc->suspend();
-            if (tc->getKernelStats())
+            if (FullSystem && tc->getKernelStats())
                 tc->getKernelStats()->quiesce();
         }
         break;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 1c9cf552d..272df690c 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -31,10 +31,8 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/utility.hh"
-#if FULL_SYSTEM
 #include "arch/sparc/vtophys.hh"
 #include "mem/fs_translating_port_proxy.hh"
-#endif
 
 namespace SparcISA {
 
@@ -48,7 +46,11 @@ namespace SparcISA {
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
+    if (!FullSystem) {
+        panic("getArgument() only implemented for full system\n");
+        M5_DUMMY_RETURN
+    }
+
     const int NumArgumentRegs = 6;
     if (number < NumArgumentRegs) {
         return tc->readIntReg(8 + number);
@@ -59,10 +61,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
                             (number-NumArgumentRegs) * sizeof(uint64_t));
         return arg;
     }
-#else
-    panic("getArgument() only implemented for FULL_SYSTEM\n");
-    M5_DUMMY_RETURN
-#endif
 }
 
 void
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 76b551ac8..ee94ef29a 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -39,6 +39,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/full_system.hh"
 
 namespace SparcISA
 {
@@ -73,13 +74,9 @@ void initCPU(ThreadContext *tc, int cpuId);
 inline void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-#if FULL_SYSTEM
     // Other CPUs will get activated by IPIs
-    if (cpuId == 0)
+    if (cpuId == 0 || !FullSystem)
         tc->activate(0);
-#else
-    tc->activate(0);
-#endif
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 2742c79e8..3bd968e21 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -53,45 +53,38 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microop.cc')
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
+    Source('linux/syscalls.cc')
+    Source('linux/system.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
+    Source('pagetable_walker.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
+    Source('process.cc')
     Source('remote_gdb.cc')
+    Source('stacktrace.cc')
+    Source('system.cc')
     Source('tlb.cc')
     Source('types.cc')
     Source('utility.cc')
+    Source('vtophys.cc')
 
+    SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
-
+    SimObject('X86System.py')
     SimObject('X86TLB.py')
+
+    DebugFlag('Faults', "Trace all faults/exceptions/traps")
+    DebugFlag('LocalApic', "Local APIC debugging")
+    DebugFlag('PageTableWalker', \
+              "Page table walker state machine debugging")
     DebugFlag('Predecoder', "Predecoder debug output")
     DebugFlag('X86', "Generic X86 ISA debugging")
 
-    if env['FULL_SYSTEM']:
-        DebugFlag('LocalApic', "Local APIC debugging")
-        DebugFlag('PageTableWalker', \
-                  "Page table walker state machine debugging")
-        DebugFlag('Faults', "Trace all faults/exceptions/traps")
-
-        SimObject('X86LocalApic.py')
-        SimObject('X86System.py')
-
-        # Full-system sources
-        Source('interrupts.cc')
-        Source('linux/system.cc')
-        Source('pagetable_walker.cc')
-        Source('system.cc')
-        Source('stacktrace.cc')
-        Source('vtophys.cc')
-    else:
-        Source('process.cc')
-
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-        Source('linux/syscalls.cc')
-
     python_files = (
         '__init__.py',
         'general_purpose/__init__.py',
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index b9be19b64..2f53c4e24 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -26,7 +26,9 @@
 #
 # Authors: Gabe Black
 
+from m5.defines import buildEnv
 from m5.params import *
+from m5.proxy import *
 from Device import BasicPioDevice
 
 class X86LocalApic(BasicPioDevice):
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ae9bfd353..7f2fcd358 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -35,24 +35,21 @@
 #
 # Authors: Gabe Black
 
-from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
 from BaseTLB import BaseTLB
 from MemObject import MemObject
 
-if buildEnv['FULL_SYSTEM']:
-    class X86PagetableWalker(MemObject):
-        type = 'X86PagetableWalker'
-        cxx_class = 'X86ISA::Walker'
-        port = Port("Port for the hardware table walker")
-        system = Param.System(Parent.any, "system object")
+class X86PagetableWalker(MemObject):
+    type = 'X86PagetableWalker'
+    cxx_class = 'X86ISA::Walker'
+    port = Port("Port for the hardware table walker")
+    system = Param.System(Parent.any, "system object")
 
 class X86TLB(BaseTLB):
     type = 'X86TLB'
     cxx_class = 'X86ISA::TLB'
     size = Param.Int(64, "TLB size")
-    if buildEnv['FULL_SYSTEM']:
-        walker = Param.X86PagetableWalker(\
-                X86PagetableWalker(), "page table walker")
+    walker = Param.X86PagetableWalker(\
+            X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/bios/SConscript b/src/arch/x86/bios/SConscript
index 16a413ed0..abc734ef4 100644
--- a/src/arch/x86/bios/SConscript
+++ b/src/arch/x86/bios/SConscript
@@ -40,20 +40,19 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'x86':
-    if env['FULL_SYSTEM']:
-        # The table generated by the bootloader using the BIOS and passed to
-        # the operating system which maps out physical memory.
-        SimObject('E820.py')
-        Source('e820.cc')
+    # The table generated by the bootloader using the BIOS and passed to
+    # the operating system which maps out physical memory.
+    SimObject('E820.py')
+    Source('e820.cc')
 
-        # The DMI tables.
-        SimObject('SMBios.py')
-        Source('smbios.cc')
+    # The DMI tables.
+    SimObject('SMBios.py')
+    Source('smbios.cc')
 
-        # Intel Multiprocessor Specification Configuration Table
-        SimObject('IntelMP.py')
-        Source('intelmp.cc')
+    # Intel Multiprocessor Specification Configuration Table
+    SimObject('IntelMP.py')
+    Source('intelmp.cc')
 
-        # ACPI system description tables
-        SimObject('ACPI.py')
-        Source('acpi.cc')
+    # ACPI system description tables
+    SimObject('ACPI.py')
+    Source('acpi.cc')
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index feb88fd76..e95d8e7dc 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -42,27 +42,25 @@
 
 #include "arch/x86/decoder.hh"
 #include "arch/x86/faults.hh"
+#include "arch/x86/isa_traits.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
-#include "arch/x86/isa_traits.hh"
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-#else
-#include "arch/x86/tlb.hh"
 #include "debug/Faults.hh"
-#endif
+#include "sim/full_system.hh"
 
 namespace X86ISA
 {
-#if FULL_SYSTEM
     void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
+        if (!FullSystem) {
+            FaultBase::invoke(tc, inst);
+            return;
+        }
+
         PCState pcState = tc->pcState();
         Addr pc = pcState.pc();
-        DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
+        DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
+                pc, vector, describe());
         using namespace X86ISAInst::RomLabels;
         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
         MicroPC entry;
@@ -84,8 +82,8 @@ namespace X86ISA
                 panic("Legacy mode interrupts with error codes "
                         "aren't implementde.\n");
             }
-            // Software interrupts shouldn't have error codes. If one does,
-            // there would need to be microcode to set it up.
+            // Software interrupts shouldn't have error codes. If one
+            // does, there would need to be microcode to set it up.
             assert(!isSoft());
             tc->setIntReg(INTREG_MICRO(15), errorCode);
         }
@@ -109,7 +107,11 @@ namespace X86ISA
     void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         X86FaultBase::invoke(tc);
-        // This is the same as a fault, but it happens -after- the instruction.
+        if (!FullSystem)
+            return;
+
+        // This is the same as a fault, but it happens -after- the
+        // instruction.
         PCState pc = tc->pcState();
         pc.uEnd();
     }
@@ -119,19 +121,43 @@ namespace X86ISA
         panic("Abort exception!");
     }
 
+    void
+    InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
+    {
+        if (FullSystem) {
+            X86Fault::invoke(tc, inst);
+        } else {
+            panic("Unrecognized/invalid instruction executed:\n %s",
+                    inst->machInst);
+        }
+    }
+
     void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
-        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
-        X86FaultBase::invoke(tc);
-        /*
-         * If something bad happens while trying to enter the page fault
-         * handler, I'm pretty sure that's a double fault and then all bets are
-         * off. That means it should be safe to update this state now.
-         */
-        if (m5reg.mode == LongMode) {
-            tc->setMiscReg(MISCREG_CR2, addr);
+        if (FullSystem) {
+            HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+            X86FaultBase::invoke(tc);
+            /*
+             * If something bad happens while trying to enter the page fault
+             * handler, I'm pretty sure that's a double fault and then all
+             * bets are off. That means it should be safe to update this
+             * state now.
+             */
+            if (m5reg.mode == LongMode) {
+                tc->setMiscReg(MISCREG_CR2, addr);
+            } else {
+                tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+            }
         } else {
-            tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
+            PageFaultErrorCode code = errorCode;
+            const char *modeStr = "";
+            if (code.fetch)
+                modeStr = "execute";
+            else if (code.write)
+                modeStr = "write";
+            else
+                modeStr = "read";
+            panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
         }
     }
 
@@ -268,30 +294,5 @@ namespace X86ISA
 
         tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
     }
-
-#else
-
-    void
-    InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
-    {
-        panic("Unrecognized/invalid instruction executed:\n %s",
-                inst->machInst);
-    }
-
-    void
-    PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
-    {
-        PageFaultErrorCode code = errorCode;
-        const char *modeStr = "";
-        if (code.fetch)
-            modeStr = "execute";
-        else if (code.write)
-            modeStr = "write";
-        else
-            modeStr = "read";
-        panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
-    }
-
-#endif
 } // namespace X86ISA
 
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index fba2a26b5..94a2ffcc2 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -85,12 +85,10 @@ namespace X86ISA
             return false;
         }
 
-#if FULL_SYSTEM
         void invoke(ThreadContext * tc,
                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
         virtual std::string describe() const;
-#endif
     };
 
     // Base class for x86 faults which behave as if the underlying instruction
@@ -114,10 +112,8 @@ namespace X86ISA
             : X86FaultBase(name, mnem, vector, _errorCode)
         {}
 
-#if FULL_SYSTEM
         void invoke(ThreadContext * tc,
                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     };
 
     // Base class for x86 aborts which seem to be catastrophic failures.
@@ -129,10 +125,8 @@ namespace X86ISA
             : X86FaultBase(name, mnem, vector, _errorCode)
         {}
 
-#if FULL_SYSTEM
         void invoke(ThreadContext * tc,
                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     };
 
     // Base class for x86 interrupts.
@@ -246,10 +240,8 @@ namespace X86ISA
             X86Fault("Invalid-Opcode", "#UD", 6)
         {}
 
-#if !FULL_SYSTEM
         void invoke(ThreadContext * tc,
                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
     };
 
     class DeviceNotAvailable : public X86Fault
@@ -334,9 +326,7 @@ namespace X86ISA
         void invoke(ThreadContext * tc,
                 StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
-#if FULL_SYSTEM
         virtual std::string describe() const;
-#endif
     };
 
     class X87FpExceptionPending : public X86Fault
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 9944f4afd..612244f49 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -47,6 +47,7 @@
 #include "dev/x86/south_bridge.hh"
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
+#include "sim/full_system.hh"
 
 int
 divideFromConf(uint32_t conf)
@@ -273,8 +274,9 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
             pendingUnmaskableInt = pendingStartup = true;
             startupVector = vector;
         }
-    } 
-    cpu->wakeup();
+    }
+    if (FullSystem)
+        cpu->wakeup();
 }
 
 
@@ -302,10 +304,6 @@ X86ISA::Interrupts::init()
     //
     BasicPioDevice::init();
     IntDev::init();
-
-    Pc * pc = dynamic_cast<Pc *>(platform);
-    assert(pc);
-    pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
 }
 
 
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 6cf50e2fe..8567b30f0 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -176,6 +176,9 @@ class Interrupts : public BasicPioDevice, IntDev
     int initialApicId;
 
   public:
+
+    int getInitialApicId() { return initialApicId; }
+
     /*
      * Params stuff.
      */
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 4a5cf32d0..4ebf23032 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -394,7 +394,7 @@
                     default: Inst::RET_FAR();
                 }
                 0x4: int3();
-                0x5: decode FULL_SYSTEM default int_Ib() {
+                0x5: decode FullSystem default int_Ib() {
                     0: decode IMMEDIATE {
                         // Really only the LSB matters, but the predecoder
                         // will sign extend it, and there's no easy way to
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 2471b61ce..030e36404 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
                         default: Inst::UD2();
                     }
                 }
-                0x05: decode FULL_SYSTEM {
+                0x05: decode FullSystem {
                     0: SyscallInst::syscall('xc->syscall(Rax)',
                             IsSyscall, IsNonSpeculative, IsSerializeAfter);
                     default: decode MODE_MODE {
@@ -398,7 +398,7 @@
                 0x1: Inst::RDTSC();
                 0x2: Inst::RDMSR();
                 0x3: rdpmc();
-                0x4: decode FULL_SYSTEM {
+                0x4: decode FullSystem {
                     0: SyscallInst::sysenter('xc->syscall(Rax)',
                             IsSyscall, IsNonSpeculative, IsSerializeAfter);
                     default: sysenter();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 237b29877..9a9759c7a 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -84,6 +84,7 @@ output decoder {{
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 #include "mem/packet.hh"
+#include "sim/full_system.hh"
 
 #if defined(linux) || defined(__APPLE__)
 #include <fenv.h>
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 525f54bfb..054f280a8 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -47,7 +47,6 @@
  */
 
 #include "arch/x86/regs/misc.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
@@ -57,25 +56,18 @@ namespace X86ISA
     inline Tick
     handleIprRead(ThreadContext *xc, Packet *pkt)
     {
-#if !FULL_SYSTEM
-        panic("Shouldn't have a memory mapped register in SE\n");
-#else
         Addr offset = pkt->getAddr() & mask(3);
         MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
         MiscReg data = htog(xc->readMiscReg(index));
         // Make sure we don't trot off the end of data.
         assert(offset + pkt->getSize() <= sizeof(MiscReg));
         pkt->setData(((uint8_t *)&data) + offset);
-#endif
         return xc->getCpuPtr()->ticks(1);
     }
 
     inline Tick
     handleIprWrite(ThreadContext *xc, Packet *pkt)
     {
-#if !FULL_SYSTEM
-        panic("Shouldn't have a memory mapped register in SE\n");
-#else
         Addr offset = pkt->getAddr() & mask(3);
         MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
         MiscReg data;
@@ -84,7 +76,6 @@ namespace X86ISA
         assert(offset + pkt->getSize() <= sizeof(MiscReg));
         pkt->writeData(((uint8_t *)&data) + offset);
         xc->setMiscReg(index, gtoh(data));
-#endif
         return xc->getCpuPtr()->ticks(1);
     }
 };
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 8db7a6088..c7bce59bf 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -47,7 +47,6 @@
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 
 using namespace std;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 131909e50..ff65eb04c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -44,23 +44,19 @@
 #include "arch/x86/regs/msr.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/pagetable.hh"
+#include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/tlb.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/TLB.hh"
 #include "mem/packet_access.hh"
-#include "mem/request.hh"
-
-#if FULL_SYSTEM
-#include "arch/x86/pagetable_walker.hh"
-#else
 #include "mem/page_table.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
-#endif
 
 namespace X86ISA {
 
@@ -72,10 +68,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
     for (int x = 0; x < size; x++)
         freeList.push_back(&tlb[x]);
 
-#if FULL_SYSTEM
     walker = p->walker;
     walker->setTLB(this);
-#endif
 }
 
 TlbEntry *
@@ -293,40 +287,40 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             // The vaddr already has the segment base applied.
             TlbEntry *entry = lookup(vaddr);
             if (!entry) {
-#if FULL_SYSTEM
-                Fault fault = walker->start(tc, translation, req, mode);
-                if (timing || fault != NoFault) {
-                    // This gets ignored in atomic mode.
-                    delayedResponse = true;
-                    return fault;
-                }
-                entry = lookup(vaddr);
-                assert(entry);
-#else
-                DPRINTF(TLB, "Handling a TLB miss for "
-                        "address %#x at pc %#x.\n",
-                        vaddr, tc->instAddr());
-
-                Process *p = tc->getProcessPtr();
-                TlbEntry newEntry;
-                bool success = p->pTable->lookup(vaddr, newEntry);
-                if (!success && mode != Execute) {
-                    // Check if we just need to grow the stack.
-                    if (p->fixupStackFault(vaddr)) {
-                        // If we did, lookup the entry for the new page.
-                        success = p->pTable->lookup(vaddr, newEntry);
+                if (FullSystem) {
+                    Fault fault = walker->start(tc, translation, req, mode);
+                    if (timing || fault != NoFault) {
+                        // This gets ignored in atomic mode.
+                        delayedResponse = true;
+                        return fault;
                     }
-                }
-                if (!success) {
-                    return new PageFault(vaddr, true, mode, true, false);
+                    entry = lookup(vaddr);
+                    assert(entry);
                 } else {
-                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
-                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
-                            newEntry.pageStart());
-                    entry = insert(alignedVaddr, newEntry);
+                    DPRINTF(TLB, "Handling a TLB miss for "
+                            "address %#x at pc %#x.\n",
+                            vaddr, tc->instAddr());
+
+                    Process *p = tc->getProcessPtr();
+                    TlbEntry newEntry;
+                    bool success = p->pTable->lookup(vaddr, newEntry);
+                    if (!success && mode != Execute) {
+                        // Check if we just need to grow the stack.
+                        if (p->fixupStackFault(vaddr)) {
+                            // If we did, lookup the entry for the new page.
+                            success = p->pTable->lookup(vaddr, newEntry);
+                        }
+                    }
+                    if (!success) {
+                        return new PageFault(vaddr, true, mode, true, false);
+                    } else {
+                        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+                        DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
+                                newEntry.pageStart());
+                        entry = insert(alignedVaddr, newEntry);
+                    }
+                    DPRINTF(TLB, "Miss was serviced.\n");
                 }
-                DPRINTF(TLB, "Miss was serviced.\n");
-#endif
             }
 
             DPRINTF(TLB, "Entry found with paddr %#x, "
@@ -366,27 +360,29 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
         req->setPaddr(vaddr);
     }
     // Check for an access to the local APIC
-#if FULL_SYSTEM
-    LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
-    Addr baseAddr = localApicBase.base * PageBytes;
-    Addr paddr = req->getPaddr();
-    if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
-        // The Intel developer's manuals say the below restrictions apply,
-        // but the linux kernel, because of a compiler optimization, breaks
-        // them.
-        /*
-        // Check alignment
-        if (paddr & ((32/8) - 1))
-            return new GeneralProtection(0);
-        // Check access size
-        if (req->getSize() != (32/8))
-            return new GeneralProtection(0);
-        */
-        // Force the access to be uncacheable.
-        req->setFlags(Request::UNCACHEABLE);
-        req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
+    if (FullSystem) {
+        LocalApicBase localApicBase =
+            tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
+        Addr baseAddr = localApicBase.base * PageBytes;
+        Addr paddr = req->getPaddr();
+        if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
+            // The Intel developer's manuals say the below restrictions apply,
+            // but the linux kernel, because of a compiler optimization, breaks
+            // them.
+            /*
+            // Check alignment
+            if (paddr & ((32/8) - 1))
+                return new GeneralProtection(0);
+            // Check access size
+            if (req->getSize() != (32/8))
+                return new GeneralProtection(0);
+            */
+            // Force the access to be uncacheable.
+            req->setFlags(Request::UNCACHEABLE);
+            req->setPaddr(x86LocalAPICAddress(tc->contextId(),
+                        paddr - baseAddr));
+        }
     }
-#endif
     return NoFault;
 };
 
@@ -409,28 +405,12 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
         translation->finish(fault, req, tc, mode);
 }
 
-#if FULL_SYSTEM
-
-Tick
-TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
-{
-    return tc->getCpuPtr()->ticks(1);
-}
-
-Tick
-TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
-{
-    return tc->getCpuPtr()->ticks(1);
-}
-
 Walker *
 TLB::getWalker()
 {
     return walker;
 }
 
-#endif
-
 void
 TLB::serialize(std::ostream &os)
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e4ea0e1b7..449ca19ce 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -46,7 +46,6 @@
 
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
-#include "config/full_system.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
@@ -85,15 +84,11 @@ namespace X86ISA
 
         EntryList::iterator lookupIt(Addr va, bool update_lru = true);
 
-#if FULL_SYSTEM
-      protected:
-
         Walker * walker;
+
       public:
         Walker *getWalker();
-#endif
 
-      public:
         void invalidateAll();
 
         void invalidateNonGlobal();
@@ -120,11 +115,6 @@ namespace X86ISA
         void translateTiming(RequestPtr req, ThreadContext *tc,
                 Translation *translation, Mode mode);
 
-#if FULL_SYSTEM
-        Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-        Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
         // Checkpointing
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 29c770f3d..678467672 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -38,11 +38,7 @@
  * Authors: Gabe Black
  */
 
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
 #include "arch/x86/interrupts.hh"
-#endif
 #include "arch/x86/registers.hh"
 #include "arch/x86/tlb.hh"
 #include "arch/x86/utility.hh"
@@ -55,15 +51,10 @@ namespace X86ISA {
 uint64_t
 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
 {
-#if FULL_SYSTEM
     panic("getArgument() not implemented for x86!\n");
-#else
-    panic("getArgument() only implemented for FULL_SYSTEM\n");
     M5_DUMMY_RETURN
-#endif
 }
 
-# if FULL_SYSTEM
 void initCPU(ThreadContext *tc, int cpuId)
 {
     // This function is essentially performing a reset. The actual INIT
@@ -193,12 +184,9 @@ void initCPU(ThreadContext *tc, int cpuId)
     tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
 }
 
-#endif
-
 void startupCPU(ThreadContext *tc, int cpuId)
 {
-#if FULL_SYSTEM
-    if (cpuId == 0) {
+    if (cpuId == 0 || !FullSystem) {
         tc->activate(0);
     } else {
         // This is an application processor (AP). It should be initialized to
@@ -206,9 +194,6 @@ void startupCPU(ThreadContext *tc, int cpuId)
         // a halted state.
         tc->suspend(0);
     }
-#else
-    tc->activate(0);
-#endif
 }
 
 void
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 4cfbe77db..f120ea6c7 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -45,9 +45,9 @@
 #include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 
 class ThreadContext;
 
@@ -68,12 +68,12 @@ namespace X86ISA
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-#if FULL_SYSTEM
-        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
-        return m5reg.cpl == 3;
-#else
-        return true;
-#endif
+        if (!FullSystem) {
+            return true;
+        } else {
+            HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
+            return m5reg.cpl == 3;
+        }
     }
 
     /**
@@ -83,12 +83,8 @@ namespace X86ISA
     template <class TC>
     void zeroRegisters(TC *tc);
 
-#if FULL_SYSTEM
-
     void initCPU(ThreadContext *tc, int cpuId);
 
-#endif
-
     void startupCPU(ThreadContext *tc, int cpuId);
 
     void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index 60ce37131..e4abfca59 100644
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -43,7 +43,6 @@
 #include "arch/x86/tlb.hh"
 #include "arch/x86/vtophys.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "debug/VtoPhys.hh"
 #include "sim/fault_fwd.hh"
@@ -55,16 +54,12 @@ namespace X86ISA
     Addr
     vtophys(Addr vaddr)
     {
-#if FULL_SYSTEM
         panic("Need access to page tables\n");
-#endif
-        return vaddr;
     }
 
     Addr
     vtophys(ThreadContext *tc, Addr vaddr)
     {
-#if FULL_SYSTEM
         Walker *walker = tc->getDTBPtr()->getWalker();
         Addr size;
         Addr addr = vaddr;
@@ -75,7 +70,5 @@ namespace X86ISA
         Addr paddr = addr | masked_addr;
         DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
         return paddr;
-#endif
-        return vaddr;
     }
 }
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index 1d8256b42..7b38753e2 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -122,13 +122,7 @@
 #include <cstdio>
 #include <string>
 
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
 #include "arch/vtophys.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#endif
-
 #include "base/intmath.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"
@@ -138,7 +132,9 @@
 #include "cpu/thread_context.hh"
 #include "debug/GDBAll.hh"
 #include "mem/port.hh"
+#include "mem/fs_translating_port_proxy.hh"
 #include "mem/se_translating_port_proxy.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -464,12 +460,13 @@ BaseRemoteGDB::read(Addr vaddr, size_t size, char *data)
 
     DPRINTF(GDBRead, "read:  addr=%#x, size=%d", vaddr, size);
 
-#if FULL_SYSTEM
-    FSTranslatingPortProxy *port = context->getVirtProxy();
-#else
-    SETranslatingPortProxy *port = context->getMemProxy();
-#endif
-    port->readBlob(vaddr, (uint8_t*)data, size);
+    if (FullSystem) {
+        FSTranslatingPortProxy *port = context->getVirtProxy();
+        port->readBlob(vaddr, (uint8_t*)data, size);
+    } else {
+        SETranslatingPortProxy *port = context->getMemProxy();
+        port->readBlob(vaddr, (uint8_t*)data, size);
+    }
 
 #if TRACING_ON
     if (DTRACE(GDBRead)) {
@@ -506,15 +503,14 @@ BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data)
         } else
             DPRINTFNR("\n");
     }
-#if FULL_SYSTEM
-    FSTranslatingPortProxy *port = context->getVirtProxy();
-#else
-    SETranslatingPortProxy *port = context->getMemProxy();
-#endif
-    port->writeBlob(vaddr, (uint8_t*)data, size);
-#if !FULL_SYSTEM
-    delete port;
-#endif
+    if (FullSystem) {
+        FSTranslatingPortProxy *port = context->getVirtProxy();
+        port->writeBlob(vaddr, (uint8_t*)data, size);
+    } else {
+        SETranslatingPortProxy *port = context->getMemProxy();
+        port->writeBlob(vaddr, (uint8_t*)data, size);
+        delete port;
+    }
 
     return true;
 }
diff --git a/src/base/vnc/SConscript b/src/base/vnc/SConscript
index 089509b9b..62448cd70 100644
--- a/src/base/vnc/SConscript
+++ b/src/base/vnc/SConscript
@@ -39,10 +39,8 @@
 
 Import('*')
 
-if env['FULL_SYSTEM']:
-    SimObject('VncServer.py')
-    Source('vncserver.cc')
-    DebugFlag('VNC')
-
 Source('convert.cc')
 
+SimObject('VncServer.py')
+Source('vncserver.cc')
+DebugFlag('VNC')
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6800b4c91..19464acbc 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -43,28 +43,22 @@ default_tracer = ExeTracer()
 
 if buildEnv['TARGET_ISA'] == 'alpha':
     from AlphaTLB import AlphaDTB, AlphaITB
-    if buildEnv['FULL_SYSTEM']:
-        from AlphaInterrupts import AlphaInterrupts
+    from AlphaInterrupts import AlphaInterrupts
 elif buildEnv['TARGET_ISA'] == 'sparc':
     from SparcTLB import SparcTLB
-    if buildEnv['FULL_SYSTEM']:
-        from SparcInterrupts import SparcInterrupts
+    from SparcInterrupts import SparcInterrupts
 elif buildEnv['TARGET_ISA'] == 'x86':
     from X86TLB import X86TLB
-    if buildEnv['FULL_SYSTEM']:
-        from X86LocalApic import X86LocalApic
+    from X86LocalApic import X86LocalApic
 elif buildEnv['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB
-    if buildEnv['FULL_SYSTEM']:
-        from MipsInterrupts import MipsInterrupts
+    from MipsInterrupts import MipsInterrupts
 elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
-    if buildEnv['FULL_SYSTEM']:
-        from ArmInterrupts import ArmInterrupts
+    from ArmInterrupts import ArmInterrupts
 elif buildEnv['TARGET_ISA'] == 'power':
     from PowerTLB import PowerTLB
-    if buildEnv['FULL_SYSTEM']:
-        from PowerInterrupts import PowerInterrupts
+    from PowerInterrupts import PowerInterrupts
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -84,50 +78,42 @@ class BaseCPU(MemObject):
     do_statistics_insts = Param.Bool(True,
         "enable statistics pseudo instructions")
 
-    if buildEnv['FULL_SYSTEM']:
-        profile = Param.Latency('0ns', "trace the kernel stack")
-        do_quiesce = Param.Bool(True, "enable quiesce instructions")
-    else:
-        workload = VectorParam.Process("processes to run")
+    profile = Param.Latency('0ns', "trace the kernel stack")
+    do_quiesce = Param.Bool(True, "enable quiesce instructions")
+
+    workload = VectorParam.Process([], "processes to run")
 
     if buildEnv['TARGET_ISA'] == 'sparc':
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            interrupts = Param.SparcInterrupts(
+        interrupts = Param.SparcInterrupts(
                 SparcInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            interrupts = Param.AlphaInterrupts(
+        interrupts = Param.AlphaInterrupts(
                 AlphaInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
-            interrupts = \
-                Param.X86LocalApic(_localApic, "Interrupt Controller")
+        _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+        interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            interrupts = Param.MipsInterrupts(
-                    MipsInterrupts(), "Interrupt Controller")
+        interrupts = Param.MipsInterrupts(
+                MipsInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'arm':
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            interrupts = Param.ArmInterrupts(
-                    ArmInterrupts(), "Interrupt Controller")
+        interrupts = Param.ArmInterrupts(
+                ArmInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'power':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
-            interrupts = Param.PowerInterrupts(
-                    PowerInterrupts(), "Interrupt Controller")
+        interrupts = Param.PowerInterrupts(
+                PowerInterrupts(), "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']
@@ -156,11 +142,11 @@ class BaseCPU(MemObject):
     dcache_port = Port("Data Port")
     _cached_ports = ['icache_port', 'dcache_port']
 
-    if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
         _cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     _uncached_ports = []
-    if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] == 'x86':
         _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
 
     def connectCachedPorts(self, bus):
@@ -184,17 +170,16 @@ class BaseCPU(MemObject):
         self.icache_port = ic.cpu_side
         self.dcache_port = dc.cpu_side
         self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
-        if buildEnv['FULL_SYSTEM']:
-            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
-                if iwc and dwc:
-                    self.itb_walker_cache = iwc
-                    self.dtb_walker_cache = dwc
-                    self.itb.walker.port = iwc.cpu_side
-                    self.dtb.walker.port = dwc.cpu_side
-                    self._cached_ports += ["itb_walker_cache.mem_side", \
-                                           "dtb_walker_cache.mem_side"]
-                else:
-                    self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+        if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+            if iwc and dwc:
+                self.itb_walker_cache = iwc
+                self.dtb_walker_cache = dwc
+                self.itb.walker.port = iwc.cpu_side
+                self.dtb.walker.port = dwc.cpu_side
+                self._cached_ports += ["itb_walker_cache.mem_side", \
+                                       "dtb_walker_cache.mem_side"]
+            else:
+                self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index a1074cb8b..ff731336a 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -109,6 +109,7 @@ SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
 SimObject('ExeTracer.py')
 SimObject('IntelTrace.py')
+SimObject('IntrControl.py')
 SimObject('NativeTrace.py')
 
 Source('activity.cc')
@@ -118,23 +119,19 @@ Source('decode.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
 Source('inteltrace.cc')
+Source('intr_control.cc')
 Source('nativetrace.cc')
 Source('pc_event.cc')
+Source('profile.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
 Source('simple_thread.cc')
 Source('thread_context.cc')
 Source('thread_state.cc')
 
-if env['FULL_SYSTEM']:
-    SimObject('IntrControl.py')
-
-    Source('intr_control.cc')
-    Source('profile.cc')
-
-    if env['TARGET_ISA'] == 'sparc':
-        SimObject('LegionTrace.py')
-        Source('legiontrace.cc')
+if env['TARGET_ISA'] == 'sparc':
+    SimObject('LegionTrace.py')
+    Source('legiontrace.cc')
 
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 370be7ee1..d174995a9 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -59,6 +59,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/SyscallVerbose.hh"
 #include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
@@ -112,18 +113,11 @@ CPUProgressEvent::description() const
     return "CPU Progress";
 }
 
-#if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
     : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
       interrupts(p->interrupts),
       numThreads(p->numThreads), system(p->system),
       phase(p->phase)
-#else
-BaseCPU::BaseCPU(Params *p)
-    : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
-      numThreads(p->numThreads), system(p->system),
-      phase(p->phase)
-#endif
 {
 //    currentTick = curTick();
 
@@ -218,13 +212,13 @@ BaseCPU::BaseCPU(Params *p)
             schedule(event, p->function_trace_start);
         }
     }
-#if FULL_SYSTEM
     interrupts->setCPU(this);
 
-    profileEvent = NULL;
-    if (params()->profile)
-        profileEvent = new ProfileEvent(this, params()->profile);
-#endif
+    if (FullSystem) {
+        profileEvent = NULL;
+        if (params()->profile)
+            profileEvent = new ProfileEvent(this, params()->profile);
+    }
     tracer = params()->tracer;
 }
 
@@ -248,10 +242,10 @@ BaseCPU::init()
 void
 BaseCPU::startup()
 {
-#if FULL_SYSTEM
-    if (!params()->defer_registration && profileEvent)
-        schedule(profileEvent, curTick());
-#endif
+    if (FullSystem) {
+        if (!params()->defer_registration && profileEvent)
+            schedule(profileEvent, curTick());
+    }
 
     if (params()->progress_interval) {
         Tick num_ticks = ticks(params()->progress_interval);
@@ -290,9 +284,6 @@ BaseCPU::regStats()
         }
     } else if (size == 1)
         threadContexts[0]->regStats(name());
-
-#if FULL_SYSTEM
-#endif
 }
 
 Tick
@@ -334,9 +325,9 @@ BaseCPU::registerThreadContexts()
             tc->setContextId(system->registerThreadContext(tc, _cpuId));
         else
             tc->setContextId(system->registerThreadContext(tc));
-#if !FULL_SYSTEM
-        tc->getProcessPtr()->assignThreadContext(tc->contextId());
-#endif
+
+        if (!FullSystem)
+            tc->getProcessPtr()->assignThreadContext(tc->contextId());
     }
 }
 
@@ -355,11 +346,8 @@ BaseCPU::findContext(ThreadContext *tc)
 void
 BaseCPU::switchOut()
 {
-//    panic("This CPU doesn't support sampling!");
-#if FULL_SYSTEM
     if (profileEvent && profileEvent->scheduled())
         deschedule(profileEvent);
-#endif
 }
 
 void
@@ -410,16 +398,16 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
         }
     }
 
-#if FULL_SYSTEM
     interrupts = oldCPU->interrupts;
     interrupts->setCPU(this);
 
-    for (ThreadID i = 0; i < size; ++i)
-        threadContexts[i]->profileClear();
+    if (FullSystem) {
+        for (ThreadID i = 0; i < size; ++i)
+            threadContexts[i]->profileClear();
 
-    if (profileEvent)
-        schedule(profileEvent, curTick());
-#endif
+        if (profileEvent)
+            schedule(profileEvent, curTick());
+    }
 
     // Connect new CPU to old CPU's memory only if new CPU isn't
     // connected to anything.  Also connect old CPU's memory to new
@@ -438,7 +426,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 }
 
 
-#if FULL_SYSTEM
 BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
     : cpu(_cpu), interval(_interval)
 { }
@@ -469,8 +456,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
     interrupts->unserialize(cp, section);
 }
 
-#endif // FULL_SYSTEM
-
 void
 BaseCPU::traceFunctionsInternal(Addr pc)
 {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index d4de55453..41c79dff6 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -48,19 +48,16 @@
 
 #include <vector>
 
+#include "arch/interrupts.hh"
 #include "arch/isa_traits.hh"
 #include "arch/microcode_rom.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "mem/mem_object.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/insttracer.hh"
 
-#if FULL_SYSTEM
-#include "arch/interrupts.hh"
-#endif
-
 class BaseCPUParams;
 class BranchPred;
 class CheckerCPU;
@@ -173,7 +170,6 @@ class BaseCPU : public MemObject
 
     TheISA::MicrocodeRom microcodeRom;
 
-#if FULL_SYSTEM
   protected:
     TheISA::Interrupts *interrupts;
 
@@ -190,7 +186,8 @@ class BaseCPU : public MemObject
     postInterrupt(int int_num, int index)
     {
         interrupts->post(int_num, index);
-        wakeup();
+        if (FullSystem)
+            wakeup();
     }
 
     void
@@ -208,7 +205,7 @@ class BaseCPU : public MemObject
     bool
     checkInterrupts(ThreadContext *tc) const
     {
-        return interrupts->checkInterrupts(tc);
+        return FullSystem && interrupts->checkInterrupts(tc);
     }
 
     class ProfileEvent : public Event
@@ -222,7 +219,6 @@ class BaseCPU : public MemObject
         void process();
     };
     ProfileEvent *profileEvent;
-#endif
 
   protected:
     std::vector<ThreadContext *> threadContexts;
@@ -305,7 +301,6 @@ class BaseCPU : public MemObject
 
     Tick phase;
 
-#if FULL_SYSTEM
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
@@ -319,8 +314,6 @@ class BaseCPU : public MemObject
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-#endif
-
     /**
      * Return pointer to CPU's branch predictor (NULL if none).
      * @return Branch predictor pointer.
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 5719fc84d..9089d1069 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -53,7 +53,6 @@
 #include "arch/utility.hh"
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/exetrace.hh"
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 0c7fe66bf..ec4496eb4 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -31,17 +31,14 @@
 #include <list>
 #include <string>
 
+#include "arch/kernel_stats.hh"
+#include "arch/vtophys.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
 using namespace std;
 //The CheckerCPU does alpha only
 using namespace AlphaISA;
@@ -66,17 +63,14 @@ CheckerCPU::CheckerCPU(Params *p)
 
     exitOnError = p->exitOnError;
     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
-#if FULL_SYSTEM
     itb = p->itb;
     dtb = p->dtb;
     systemPtr = NULL;
-#else
     process = p->process;
     thread = new SimpleThread(this, /* thread_num */ 0, process);
 
     tc = thread->getTC();
     threadContexts.push_back(tc);
-#endif
 
     result.integer = 0;
 }
@@ -88,7 +82,6 @@ CheckerCPU::~CheckerCPU()
 void
 CheckerCPU::setSystem(System *system)
 {
-#if FULL_SYSTEM
     systemPtr = system;
 
     thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
@@ -97,7 +90,6 @@ CheckerCPU::setSystem(System *system)
     threadContexts.push_back(tc);
     delete thread->kernelStats;
     thread->kernelStats = NULL;
-#endif
 }
 
 void
@@ -301,13 +293,11 @@ CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 }
 
 
-#if FULL_SYSTEM
 Addr
 CheckerCPU::dbg_vtophys(Addr addr)
 {
     return vtophys(tc, addr);
 }
-#endif // FULL_SYSTEM
 
 bool
 CheckerCPU::checkFlags(Request *req)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 1e3a17a34..a3e95137d 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -37,7 +37,6 @@
 
 #include "arch/types.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/base_dyn_inst.hh"
 #include "cpu/pc_event.hh"
@@ -46,25 +45,20 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#if FULL_SYSTEM
 namespace TheISA
 {
     class TLB;
 }
-class Processor;
-class PhysicalMemory;
-
-#else
 
-class Process;
-
-#endif // FULL_SYSTEM
 template <class>
 class BaseDynInst;
 class CheckerCPUParams;
-class ThreadContext;
-class MemInterface;
 class Checkpoint;
+class MemInterface;
+class PhysicalMemory;
+class Process;
+class Processor;
+class ThreadContext;
 class Request;
 
 /**
@@ -129,9 +123,7 @@ class CheckerCPU : public BaseCPU
     TheISA::TLB *itb;
     TheISA::TLB *dtb;
 
-#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
-#endif
 
     union Result {
         uint64_t integer;
@@ -273,14 +265,11 @@ class CheckerCPU : public BaseCPU
         this->dtb->demapPage(vaddr, asn);
     }
 
-#if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#else
     // Assume that the normal CPU's call to syscall was successful.
     // The checker's state would have already been updated by the syscall.
     void syscall(uint64_t callnum) { }
-#endif
 
     void handleError()
     {
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 8694dae21..7d8cc8a19 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -31,6 +31,7 @@
 #include <list>
 #include <string>
 
+#include "arch/vtophys.hh"
 #include "base/refcnt.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
@@ -38,13 +39,10 @@
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
 using namespace std;
 //The CheckerCPU does alpha only
 using namespace AlphaISA;
@@ -141,11 +139,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
         // Try to fetch the instruction
 
-#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
-#else
-#define IFETCH_FLAGS(pc)        0
-#endif
+#define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0)
 
         uint64_t fetch_PC = thread->readPC() & ~3;
 
@@ -235,12 +229,10 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         }
 
         if (fault != NoFault) {
-#if FULL_SYSTEM
             fault->invoke(tc, curStaticInst);
             willChangePC = true;
             newPC = thread->readPC();
             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
-#endif
         } else {
 #if THE_ISA != MIPS_ISA
             // go to the next instruction
@@ -255,23 +247,23 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
         }
 
-#if FULL_SYSTEM
-        // @todo: Determine if these should happen only if the
-        // instruction hasn't faulted.  In the SimpleCPU case this may
-        // not be true, but in the O3 or Ozone case this may be true.
-        Addr oldpc;
-        int count = 0;
-        do {
-            oldpc = thread->readPC();
-            system->pcEventQueue.service(tc);
-            count++;
-        } while (oldpc != thread->readPC());
-        if (count > 1) {
-            willChangePC = true;
-            newPC = thread->readPC();
-            DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+        if (FullSystem) {
+            // @todo: Determine if these should happen only if the
+            // instruction hasn't faulted.  In the SimpleCPU case this may
+            // not be true, but in the O3 or Ozone case this may be true.
+            Addr oldpc;
+            int count = 0;
+            do {
+                oldpc = thread->readPC();
+                system->pcEventQueue.service(tc);
+                count++;
+            } while (oldpc != thread->readPC());
+            if (count > 1) {
+                willChangePC = true;
+                newPC = thread->readPC();
+                DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+            }
         }
-#endif
 
         // @todo:  Optionally can check all registers. (Or just those
         // that have been modified).
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 4eb3eabfd..178ded80e 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -89,7 +89,6 @@ class CheckerThreadContext : public ThreadContext
 
     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-#if FULL_SYSTEM
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
@@ -97,15 +96,14 @@ class CheckerThreadContext : public ThreadContext
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
+    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
+
     PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); }
 
     FSTranslatingPortProxy* getVirtProxy()
     { return actualTC->getVirtProxy(); }
-#else
-    SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
 
-    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
+    SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
 
     Status status() const { return actualTC->status(); }
 
@@ -125,9 +123,7 @@ class CheckerThreadContext : public ThreadContext
     /// Set the status to Halted.
     void halt() { actualTC->halt(); }
 
-#if FULL_SYSTEM
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
 
     void takeOverFrom(ThreadContext *oldContext)
     {
@@ -141,7 +137,6 @@ class CheckerThreadContext : public ThreadContext
     void unserialize(Checkpoint *cp, const std::string &section)
     { actualTC->unserialize(cp, section); }
 
-#if FULL_SYSTEM
     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
     Tick readLastActivate() { return actualTC->readLastActivate(); }
@@ -149,7 +144,6 @@ class CheckerThreadContext : public ThreadContext
 
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
-#endif
 
     int threadId() { return actualTC->threadId(); }
 
@@ -253,9 +247,7 @@ class CheckerThreadContext : public ThreadContext
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
 
-#if !FULL_SYSTEM
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
 };
 
 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 61c9b24a9..2f4d26976 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -111,7 +111,6 @@ class ExecContext {
     Fault writeMem(uint8_t *data, unsigned size,
                    Addr addr, unsigned flags, uint64_t *res);
 
-#if FULL_SYSTEM
     /** Somewhat Alpha-specific function that handles returning from
      * an error or interrupt. */
     Fault hwrei();
@@ -121,10 +120,9 @@ class ExecContext {
      * return value is false, actual PAL call will be suppressed.
      */
     bool simPalCheck(int palFunc);
-#else
+
     /** Executes a syscall specified by the callnum. */
     void syscall(int64_t callnum);
-#endif
 
     /** Finish a DTB address translation. */
     void finishTranslation(WholeTranslationState *state);
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 40991652d..0b21a1270 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -83,10 +83,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
     std::string sym_str;
     Addr sym_addr;
     Addr cur_pc = pc.instAddr();
-    if (debugSymbolTable && Debug::ExecSymbol
-#if FULL_SYSTEM
-        && !inUserMode(thread)
-#endif
+    if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread)
         && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
         if (cur_pc != sym_addr)
             sym_str += csprintf("+%d",cur_pc - sym_addr);
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 9614a5df2..5a14e92a7 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -33,7 +33,6 @@
 
 #include "arch/utility.hh"
 #include "base/bigint.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/resource_list.hh"
 #include "cpu/inorder/cpu.hh"
@@ -46,21 +45,20 @@
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Activity.hh"
 #include "debug/InOrderCPU.hh"
+#include "debug/Interrupt.hh"
 #include "debug/RefCount.hh"
 #include "debug/SkedCache.hh"
 #include "debug/Quiesce.hh"
 #include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
-
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
 #include "sim/system.hh"
-#endif
 
 #if THE_ISA == ALPHA_ISA
 #include "arch/alpha/osfpal.hh"
@@ -152,12 +150,11 @@ InOrderCPU::CPUEvent::process()
         cpu->trapPending[tid] = false;
         break;
 
-#if !FULL_SYSTEM
       case Syscall:
         cpu->syscall(inst->syscallNum, tid);
         cpu->resPool->trap(fault, tid, inst);
         break;
-#endif
+
       default:
         fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);    
     }
@@ -197,9 +194,7 @@ InOrderCPU::InOrderCPU(Params *params)
       timeBuffer(2 , 2),
       removeInstsThisCycle(false),
       activityRec(params->name, NumStages, 10, params->activity),
-#if FULL_SYSTEM
       system(params->system),
-#endif // FULL_SYSTEM
 #ifdef DEBUG
       cpuEventNum(0),
       resReqCount(0),
@@ -217,33 +212,33 @@ InOrderCPU::InOrderCPU(Params *params)
     // Resize for Multithreading CPUs
     thread.resize(numThreads);
 
-#if !FULL_SYSTEM
     ThreadID active_threads = params->workload.size();
+    if (FullSystem) {
+        active_threads = 1;
+    } else {
+        active_threads = params->workload.size();
 
-    if (active_threads > MaxThreads) {
-        panic("Workload Size too large. Increase the 'MaxThreads'"
-              "in your InOrder implementation or "
-              "edit your workload size.");
-    }
+        if (active_threads > MaxThreads) {
+            panic("Workload Size too large. Increase the 'MaxThreads'"
+                  "in your InOrder implementation or "
+                  "edit your workload size.");
+        }
 
-    
-    if (active_threads > 1) {
-        threadModel = (InOrderCPU::ThreadModel) params->threadModel;
-
-        if (threadModel == SMT) {
-            DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");            
-        } else if (threadModel == SwitchOnCacheMiss) {
-            DPRINTF(InOrderCPU, "Setting Thread Model to "
-                    "Switch On Cache Miss\n");
+
+        if (active_threads > 1) {
+            threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+
+            if (threadModel == SMT) {
+                DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
+            } else if (threadModel == SwitchOnCacheMiss) {
+                DPRINTF(InOrderCPU, "Setting Thread Model to "
+                        "Switch On Cache Miss\n");
+            }
+
+        } else {
+            threadModel = Single;
         }
-        
-    } else {
-        threadModel = Single;
     }
-     
-        
-    
-#endif
 
     // Bind the fetch & data ports from the resource pool.
     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
@@ -260,36 +255,34 @@ InOrderCPU::InOrderCPU(Params *params)
         pc[tid].set(0);
         lastCommittedPC[tid].set(0);
 
-#if FULL_SYSTEM
-        // SMT is not supported in FS mode yet.
-        assert(numThreads == 1);
-        thread[tid] = new Thread(this, 0);
-#else
-        if (tid < (ThreadID)params->workload.size()) {
-            DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
-                    tid, params->workload[tid]->prog_fname);
-            thread[tid] =
-                new Thread(this, tid, params->workload[tid]);
+        if (FullSystem) {
+            // SMT is not supported in FS mode yet.
+            assert(numThreads == 1);
+            thread[tid] = new Thread(this, 0, NULL);
         } else {
-            //Allocate Empty thread so M5 can use later
-            //when scheduling threads to CPU
-            Process* dummy_proc = params->workload[0];
-            thread[tid] = new Thread(this, tid, dummy_proc);
+            if (tid < (ThreadID)params->workload.size()) {
+                DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
+                        tid, params->workload[tid]->prog_fname);
+                thread[tid] =
+                    new Thread(this, tid, params->workload[tid]);
+            } else {
+                //Allocate Empty thread so M5 can use later
+                //when scheduling threads to CPU
+                Process* dummy_proc = params->workload[0];
+                thread[tid] = new Thread(this, tid, dummy_proc);
+            }
+
+            // Eventually set this with parameters...
+            asid[tid] = tid;
         }
-        
-        // Eventually set this with parameters...
-        asid[tid] = tid;
-#endif
 
         // Setup the TC that will serve as the interface to the threads/CPU.
         InOrderThreadContext *tc = new InOrderThreadContext;
         tc->cpu = this;
         tc->thread = thread[tid];
 
-#if FULL_SYSTEM
         // Setup quiesce event.
         this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
 
         // Give the thread the TC.
         thread[tid]->tc = tc;
@@ -348,16 +341,17 @@ InOrderCPU::InOrderCPU(Params *params)
 
         dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
 
-#if FULL_SYSTEM
-    // Use this dummy inst to force squashing behind every instruction
-    // in pipeline
-    dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
-    dummyTrapInst[tid]->seqNum = 0;
-    dummyTrapInst[tid]->squashSeqNum = 0;
-    dummyTrapInst[tid]->setTid(tid);
-#endif
 
-    trapPending[tid] = false;
+        if (FullSystem) {
+            // Use this dummy inst to force squashing behind every instruction
+            // in pipeline
+            dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
+            dummyTrapInst[tid]->seqNum = 0;
+            dummyTrapInst[tid]->squashSeqNum = 0;
+            dummyTrapInst[tid]->setTid(tid);
+        }
+
+        trapPending[tid] = false;
 
     }
 
@@ -698,9 +692,7 @@ InOrderCPU::tick()
 
     ++numCycles;
 
-#if FULL_SYSTEM
     checkForInterrupts();
-#endif
 
     bool pipes_idle = true;
     //Tick each of the stages
@@ -761,14 +753,14 @@ InOrderCPU::init()
     for (ThreadID tid = 0; tid < numThreads; ++tid)
         thread[tid]->inSyscall = true;
 
-#if FULL_SYSTEM
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        ThreadContext *src_tc = threadContexts[tid];
-        TheISA::initCPU(src_tc, src_tc->contextId());
-        // Initialise the ThreadContext's memory proxies
-        thread[tid]->initMemProxies(thread[tid]->getTC());
+    if (FullSystem) {
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            ThreadContext *src_tc = threadContexts[tid];
+            TheISA::initCPU(src_tc, src_tc->contextId());
+            // Initialise the ThreadContext's memory proxies
+            thread[tid]->initMemProxies(thread[tid]->getTC());
+        }
     }
-#endif
 
     // Clear inSyscall.
     for (ThreadID tid = 0; tid < numThreads; ++tid)
@@ -784,7 +776,6 @@ InOrderCPU::getPort(const std::string &if_name, int idx)
     return resPool->getPort(if_name, idx);
 }
 
-#if FULL_SYSTEM
 Fault
 InOrderCPU::hwrei(ThreadID tid)
 {
@@ -870,7 +861,6 @@ InOrderCPU::getInterrupts()
     return interrupts->getInterrupt(threadContexts[0]);
 }
 
-
 void
 InOrderCPU::processInterrupts(Fault interrupt)
 {
@@ -889,8 +879,6 @@ InOrderCPU::processInterrupts(Fault interrupt)
     trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
 }
 
-#endif
-
 void
 InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 {
@@ -1681,7 +1669,6 @@ InOrderCPU::wakeCPU()
     schedule(&tickEvent, nextCycle(curTick()));
 }
 
-#if FULL_SYSTEM
 // Lots of copied full system code...place into BaseCPU class?
 void
 InOrderCPU::wakeup()
@@ -1694,9 +1681,7 @@ InOrderCPU::wakeup()
     DPRINTF(Quiesce, "Suspended Processor woken\n");
     threadContexts[0]->activate();
 }
-#endif
 
-#if !FULL_SYSTEM
 void
 InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 {
@@ -1734,7 +1719,6 @@ InOrderCPU::syscall(int64_t callnum, ThreadID tid)
     // Clear Non-Speculative Block Variable
     nonSpecInstActive[tid] = false;
 }
-#endif
 
 TheISA::TLB*
 InOrderCPU::getITBPtr()
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 1559874cd..7d22bc902 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -43,7 +43,6 @@
 #include "arch/types.hh"
 #include "base/statistics.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_stage.hh"
@@ -413,7 +412,6 @@ class InOrderCPU : public BaseCPU
     /** Get a Memory Port */
     Port* getPort(const std::string &if_name, int idx = 0);
 
-#if FULL_SYSTEM
     /** HW return from error interrupt. */
     Fault hwrei(ThreadID tid);
 
@@ -435,14 +433,13 @@ class InOrderCPU : public BaseCPU
 
     /** Check if this address is a valid data address. */
     bool validDataAddr(Addr addr) { return true; }
-#else
+
     /** Schedule a syscall on the CPU */
     void syscallContext(Fault fault, ThreadID tid, DynInstPtr inst,
                         int delay = 0);
 
     /** Executes a syscall.*/
     void syscall(int64_t callnum, ThreadID tid);
-#endif
 
     /** Schedule a trap on the CPU */
     void trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
@@ -749,9 +746,7 @@ class InOrderCPU : public BaseCPU
     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
     void wakeCPU();
 
-#if FULL_SYSTEM
     virtual void wakeup();
-#endif
 
     /* LL/SC debug functionality
     unsigned stCondFails;
@@ -780,10 +775,8 @@ class InOrderCPU : public BaseCPU
         return total;
     }
 
-#if FULL_SYSTEM
     /** Pointer to the system. */
     System *system;
-#endif
 
     /** The global sequence number counter. */
     InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc
index 99729577e..bde5b1e94 100644
--- a/src/cpu/inorder/inorder_cpu_builder.cc
+++ b/src/cpu/inorder/inorder_cpu_builder.cc
@@ -38,21 +38,23 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "params/InOrderCPU.hh"
+#include "sim/full_system.hh"
 
 InOrderCPU *
 InOrderCPUParams::create()
 {
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    ThreadID actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
+    ThreadID actual_num_threads;
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        actual_num_threads = 1;
+    } else {
+        actual_num_threads =
+            (numThreads >= workload.size()) ? numThreads : workload.size();
 
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
-#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index ff178f6d3..b61beece2 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -45,6 +45,7 @@
 #include "cpu/exetrace.hh"
 #include "debug/InOrderDynInst.hh"
 #include "mem/request.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -269,8 +270,6 @@ InOrderDynInst::memAccess()
 }
 
 
-#if FULL_SYSTEM
-
 Fault
 InOrderDynInst::hwrei()
 {
@@ -311,17 +310,15 @@ InOrderDynInst::simPalCheck(int palFunc)
 #endif
     return this->cpu->simPalCheck(palFunc, this->threadNumber);
 }
-#endif
 
 void
 InOrderDynInst::syscall(int64_t callnum)
 {
-#if FULL_SYSTEM
-    panic("Syscall emulation isn't available in FS mode.\n");
-#else
+    if (FullSystem)
+        panic("Syscall emulation isn't available in FS mode.\n");
+
     syscallNum = callnum;
     cpu->syscallContext(NoFault, this->threadNumber, this);
-#endif
 }
 
 void
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index f49476ec5..b49dd7594 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -45,7 +45,6 @@
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/inorder_trace.hh"
 #include "cpu/inorder/pipeline_traits.hh"
@@ -517,15 +516,12 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
 
     /** Calls a syscall. */
-#if FULL_SYSTEM
     /** Calls hardware return from error interrupt. */
     Fault hwrei();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
-#else
     short syscallNum;
-#endif
 
     /** Emulates a syscall. */
     void syscall(int64_t callnum);
diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh
index 51b7409ad..44f2a5018 100644
--- a/src/cpu/inorder/params.hh
+++ b/src/cpu/inorder/params.hh
@@ -50,10 +50,8 @@ class InOrderParams : public BaseCPU::Params
   public:
 
     // Workloads
-#if !FULL_SYSTEM
     std::vector<Process *> workload;
     Process *process;
-#endif // FULL_SYSTEM
 
     //
     // Memory System/Caches
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 856675e05..0ab9f0579 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -430,13 +430,11 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
     }
 }
 
-#if !FULL_SYSTEM
 void
 CacheUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     tlbBlocked[tid] = false;
 }
-#endif
 
 Fault
 CacheUnit::read(DynInstPtr inst, Addr addr,
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 6ca300163..2155c920c 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -149,9 +149,8 @@ class CacheUnit : public Resource
 
     bool processSquash(CacheReqPacket *cache_pkt);
 
-#if !FULL_SYSTEM
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
-#endif
+
     void recvRetry();
 
     /** Returns a specific port. */
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index a0a486269..16f737308 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -38,6 +38,7 @@
 #include "debug/Fault.hh"
 #include "debug/InOrderExecute.hh"
 #include "debug/InOrderStall.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace ThePipeline;
@@ -219,14 +220,14 @@ ExecutionUnit::execute(int slot_num)
                                     seq_num, didx, inst->readIntResult(didx));
 #endif
 
-#if !FULL_SYSTEM
-                    // The Syscall might change the PC, so conservatively
-                    // squash everything behing it
-                    if (inst->isSyscall()) {
-                        inst->setSquashInfo(stage_num);
-                        setupSquash(inst, stage_num, tid);
+                    if (!FullSystem) {
+                        // The Syscall might change the PC, so conservatively
+                        // squash everything behing it
+                        if (inst->isSyscall()) {
+                            inst->setSquashInfo(stage_num);
+                            setupSquash(inst, stage_num, tid);
+                        }
                     }
-#endif
                 } else {
                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
                             "fault.\n", inst->readTid(), seq_num, fault->name());
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 82e681f04..acfcf0939 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -34,18 +34,16 @@
 #include "cpu/inorder/thread_context.hh"
 #include "cpu/exetrace.hh"
 #include "debug/InOrderCPU.hh"
+#include "sim/full_system.hh"
 
 using namespace TheISA;
 
-#if FULL_SYSTEM
-
 FSTranslatingPortProxy*
 InOrderThreadContext::getVirtProxy()
 {
     return thread->getVirtProxy();
 }
 
-
 void
 InOrderThreadContext::dumpFuncProfile()
 {
@@ -79,26 +77,19 @@ InOrderThreadContext::profileSample()
 {
     thread->profileSample();
 }
-#endif
 
 void
 InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
     assert(getSystemPtr() == old_context->getSystemPtr());
-#if !FULL_SYSTEM
     assert(getProcessPtr() == old_context->getProcessPtr());
-#endif
-
-
 
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
 
-#if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
-#endif
  
     old_context->setStatus(ThreadContext::Halted);
 
@@ -151,11 +142,10 @@ InOrderThreadContext::halt(int delay)
 void
 InOrderThreadContext::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
-    ;
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 5b67d7e8b..7fe0fb5ef 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -109,7 +109,6 @@ class InOrderThreadContext : public ThreadContext
 
     void setNextMicroPC(uint64_t val) { };
 
-#if FULL_SYSTEM
     /** Returns a pointer to physical memory. */
     PhysicalMemory *getPhysMemPtr()
     { assert(0); return 0; /*return cpu->physmem;*/ }
@@ -146,12 +145,11 @@ class InOrderThreadContext : public ThreadContext
     {
         return this->thread->quiesceEvent;
     }
-#else
+
     SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
 
     /** Returns a pointer to this thread's process. */
     Process *getProcessPtr() { return thread->getProcessPtr(); }
-#endif
 
     /** Returns this thread's status. */
     Status status() const { return thread->status(); }
@@ -273,11 +271,9 @@ class InOrderThreadContext : public ThreadContext
      * misspeculating, this is set as false. */
     bool misspeculating() { return false; }
 
-#if !FULL_SYSTEM
     /** Executes a syscall in SE mode. */
     void syscall(int64_t callnum)
     { return cpu->syscall(callnum, thread->threadId()); }
-#endif
 
     /** Reads the funcExeInst counter. */
     Counter readFuncExeInst() { return thread->funcExeInst; }
diff --git a/src/cpu/inorder/thread_state.cc b/src/cpu/inorder/thread_state.cc
index b17f05c7d..040e29283 100644
--- a/src/cpu/inorder/thread_state.cc
+++ b/src/cpu/inorder/thread_state.cc
@@ -36,12 +36,9 @@
 
 using namespace TheISA;
 
-#if FULL_SYSTEM
 void 
 InOrderThreadState::dumpFuncProfile()    
 {
     std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
     profile->dump(tc, *os);
 }
-#endif
-
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index 227097569..1ffc59f65 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -39,17 +39,13 @@
 #include "cpu/thread_state.hh"
 #include "sim/sim_exit.hh"
 
-class Event;
-class InOrderCPU;
-
-#if FULL_SYSTEM
 class EndQuiesceEvent;
-class FunctionProfile;
-class ProfileNode;
-#else
+class Event;
 class FunctionalMemory;
+class FunctionProfile;
+class InOrderCPU;
 class Process;
-#endif
+class ProfileNode;
 
 /**
  * Class that has various thread state, such as the status, the
@@ -76,28 +72,17 @@ class InOrderThreadState : public ThreadState {
      */
     bool trapPending;
 
-#if FULL_SYSTEM
-    InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num)
-        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num),
-          cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false)
-    { }
-#else
     InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
                        Process *_process)
         : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num,
                       _process),
           cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false)
     { }
-#endif
 
-#if !FULL_SYSTEM
     /** Handles the syscall. */
     void syscall(int64_t callnum) { process->syscall(callnum, tc); }
-#endif
 
-#if FULL_SYSTEM
     void dumpFuncProfile();    
-#endif
 
     /** Pointer to the ThreadContext of this thread. */
     ThreadContext *tc;
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index aa8e99fd1..75d30c894 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -36,11 +36,6 @@
     #error Legion tracing only works with SPARC simulations!
 #endif
 
-#include "config/full_system.hh"
-#if !FULL_SYSTEM
-    #error Legion tracing only works in full system!
-#endif
-
 #include <sys/ipc.h>
 #include <sys/shm.h>
 
@@ -50,28 +45,24 @@
 #include "arch/sparc/predecoder.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/utility.hh"
+#include "arch/tlb.hh"
 #include "base/socket.hh"
 #include "cpu/base.hh"
 #include "cpu/decode.hh"
 #include "cpu/legiontrace.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#endif
-
 //XXX This is temporary
 #include "cpu/m5legion_interface.h"
 
 using namespace std;
 using namespace TheISA;
 
-#if FULL_SYSTEM
 static int diffcount = 0;
 static bool wasMicro = false;
-#endif
 
 namespace Trace {
 SharedData *shared_data = NULL;
@@ -597,5 +588,7 @@ Trace::LegionTraceRecord::dump()
 Trace::LegionTrace *
 LegionTraceParams::create()
 {
+    if (!FullSystem)
+        panic("Legion tracing only works in full system!");
     return new Trace::LegionTrace(this);
 };
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 6f721a11b..c3e561cd9 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -40,15 +40,11 @@ class DerivO3CPU(BaseCPU):
     activity = Param.Unsigned(0, "Initial count")
 
     if buildEnv['USE_CHECKER']:
-        if not buildEnv['FULL_SYSTEM']:
-            checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
-                                              exitOnError=False,
-                                              updateOnError=True,
-                                              warnOnlyOnLoadError=False),
-                                    "checker")
-        else:
-            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
-                                              warnOnlyOnLoadError=False), "checker")
+        checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
+                                          exitOnError=False,
+                                          updateOnError=True,
+                                          warnOnlyOnLoadError=False),
+                                "checker")
         checker.itb = Parent.itb
         checker.dtb = Parent.dtb
 
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 5d0bd2ed2..b34613f68 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -90,11 +90,8 @@ O3CheckerParams::create()
     params->dtb = dtb;
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
-#else
     params->process = workload;
-#endif
 
     O3Checker *cpu = new O3Checker(params);
     return cpu;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index ffc2c16d2..b45d37df9 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -267,13 +267,11 @@ class DefaultCommit
     void squashAfter(ThreadID tid, DynInstPtr &head_inst,
             uint64_t squash_after_seq_num);
 
-#if FULL_SYSTEM
     /** Handles processing an interrupt. */
     void handleInterrupt();
 
     /** Get fetch redirecting so we can handle an interrupt */
     void propagateInterrupt();
-#endif // FULL_SYSTEM
 
     /** Commits as many instructions as possible. */
     void commitInsts();
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 9ff31a622..b6a4c0387 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -47,7 +47,6 @@
 #include "arch/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cp_annotate.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/commit.hh"
@@ -62,6 +61,7 @@
 #include "debug/O3PipeView.hh"
 #include "params/DerivO3CPU.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
@@ -149,9 +149,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
         pc[tid].set(0);
         lastCommitedSeqNum[tid] = 0;
     }
-#if FULL_SYSTEM
     interrupt = NoFault;
-#endif
 }
 
 template <class Impl>
@@ -701,7 +699,6 @@ DefaultCommit<Impl>::tick()
     updateStatus();
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 DefaultCommit<Impl>::handleInterrupt()
@@ -767,22 +764,20 @@ DefaultCommit<Impl>::propagateInterrupt()
         toIEW->commitInfo[0].interruptPending = true;
 }
 
-#endif // FULL_SYSTEM
-
 template <class Impl>
 void
 DefaultCommit<Impl>::commit()
 {
-
-#if FULL_SYSTEM
-    // Check for any interrupt that we've already squashed for and start processing it.
-    if (interrupt != NoFault)
-        handleInterrupt();
-
-    // Check if we have a interrupt and get read to handle it
-    if (cpu->checkInterrupts(cpu->tcBase(0)))
-        propagateInterrupt();
-#endif // FULL_SYSTEM
+    if (FullSystem) {
+        // Check for any interrupt that we've already squashed for and start
+        // processing it.
+        if (interrupt != NoFault)
+            handleInterrupt();
+
+        // Check if we have a interrupt and get read to handle it
+        if (cpu->checkInterrupts(cpu->tcBase(0)))
+            propagateInterrupt();
+    }
 
     ////////////////////////////////////
     // Check for any possible squashes, handle them first
@@ -1176,22 +1171,22 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     updateComInstStats(head_inst);
 
-#if FULL_SYSTEM
-    if (thread[tid]->profile) {
-        thread[tid]->profilePC = head_inst->instAddr();
-        ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
-                                                          head_inst->staticInst);
+    if (FullSystem) {
+        if (thread[tid]->profile) {
+            thread[tid]->profilePC = head_inst->instAddr();
+            ProfileNode *node = thread[tid]->profile->consume(
+                    thread[tid]->getTC(), head_inst->staticInst);
 
-        if (node)
-            thread[tid]->profileNode = node;
-    }
-    if (CPA::available()) {
-        if (head_inst->isControl()) {
-            ThreadContext *tc = thread[tid]->getTC();
-            CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            if (node)
+                thread[tid]->profileNode = node;
+        }
+        if (CPA::available()) {
+            if (head_inst->isControl()) {
+                ThreadContext *tc = thread[tid]->getTC();
+                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
+            }
         }
     }
-#endif
     DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
             head_inst->seqNum, head_inst->pcState());
     if (head_inst->traceData) {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7e0b4cee7..ef08c96f4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -43,13 +43,14 @@
  *          Rick Strong
  */
 
-#include "config/full_system.hh"
+#include "arch/kernel_stats.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/cpu.hh"
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/activity.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Activity.hh"
@@ -57,15 +58,11 @@
 #include "debug/Quiesce.hh"
 #include "enums/MemoryMode.hh"
 #include "sim/core.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
-#else
-#include "sim/process.hh"
-#endif
-
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
 #endif
@@ -270,18 +267,16 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
         checker->setIcachePort(&icachePort);
-#if FULL_SYSTEM
         checker->setSystem(params->system);
-#endif
     } else {
         checker = NULL;
     }
 #endif // USE_CHECKER
 
-#if !FULL_SYSTEM
-    thread.resize(numThreads);
-    tids.resize(numThreads);
-#endif
+    if (!FullSystem) {
+        thread.resize(numThreads);
+        tids.resize(numThreads);
+    }
 
     // The stages also need their CPU pointer setup.  However this
     // must be done at the upper level CPU because they have pointers
@@ -317,17 +312,18 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     rename.setIEWStage(&iew);
     rename.setCommitStage(&commit);
 
-#if !FULL_SYSTEM
-    ThreadID active_threads = params->workload.size();
+    ThreadID active_threads;
+    if (FullSystem) {
+        active_threads = 1;
+    } else {
+        active_threads = params->workload.size();
 
-    if (active_threads > Impl::MaxThreads) {
-        panic("Workload Size too large. Increase the 'MaxThreads'"
-              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
-              "edit your workload size.");
+        if (active_threads > Impl::MaxThreads) {
+            panic("Workload Size too large. Increase the 'MaxThreads' "
+                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
+                  "or edit your workload size.");
+        }
     }
-#else
-    ThreadID active_threads = 1;
-#endif
 
     //Make Sure That this a Valid Architeture
     assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
@@ -406,31 +402,31 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     this->thread.resize(this->numThreads);
 
     for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
-#if FULL_SYSTEM
-        // SMT is not supported in FS mode yet.
-        assert(this->numThreads == 1);
-        this->thread[tid] = new Thread(this, 0);
-#else
-        if (tid < params->workload.size()) {
-            DPRINTF(O3CPU, "Workload[%i] process is %#x",
-                    tid, this->thread[tid]);
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, params->workload[tid]);
-
-            //usedTids[tid] = true;
-            //threadMap[tid] = tid;
+        if (FullSystem) {
+            // SMT is not supported in FS mode yet.
+            assert(this->numThreads == 1);
+            this->thread[tid] = new Thread(this, 0, NULL);
         } else {
-            //Allocate Empty thread so M5 can use later
-            //when scheduling threads to CPU
-            Process* dummy_proc = NULL;
-
-            this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
-                    (typename Impl::O3CPU *)(this),
-                    tid, dummy_proc);
-            //usedTids[tid] = false;
+            if (tid < params->workload.size()) {
+                DPRINTF(O3CPU, "Workload[%i] process is %#x",
+                        tid, this->thread[tid]);
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, params->workload[tid]);
+
+                //usedTids[tid] = true;
+                //threadMap[tid] = tid;
+            } else {
+                //Allocate Empty thread so M5 can use later
+                //when scheduling threads to CPU
+                Process* dummy_proc = NULL;
+
+                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
+                        (typename Impl::O3CPU *)(this),
+                        tid, dummy_proc);
+                //usedTids[tid] = false;
+            }
         }
-#endif // !FULL_SYSTEM
 
         ThreadContext *tc;
 
@@ -452,10 +448,10 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
         assert(o3_tc->cpu);
         o3_tc->thread = this->thread[tid];
 
-#if FULL_SYSTEM
-        // Setup quiesce event.
-        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
-#endif
+        if (FullSystem) {
+            // Setup quiesce event.
+            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
+        }
         // Give the thread the TC.
         this->thread[tid]->tc = tc;
 
@@ -608,9 +604,8 @@ FullO3CPU<Impl>::tick()
 
     commit.tick();
 
-#if !FULL_SYSTEM
-    doContextSwitch();
-#endif
+    if (!FullSystem)
+        doContextSwitch();
 
     // Now advance the time buffers
     timeBuffer.advance();
@@ -642,9 +637,8 @@ FullO3CPU<Impl>::tick()
         }
     }
 
-#if !FULL_SYSTEM
-    updateThreadPriority();
-#endif
+    if (!FullSystem)
+        updateThreadPriority();
 }
 
 template <class Impl>
@@ -665,14 +659,14 @@ FullO3CPU<Impl>::init()
     if (icachePort.isConnected())
         fetch.setIcache();
 
-#if FULL_SYSTEM
-    for (ThreadID tid = 0; tid < numThreads; tid++) {
-        ThreadContext *src_tc = threadContexts[tid];
-        TheISA::initCPU(src_tc, src_tc->contextId());
-        // Initialise the ThreadContext's memory proxies
-        thread[tid]->initMemProxies(thread[tid]->getTC());
+    if (FullSystem) {
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            ThreadContext *src_tc = threadContexts[tid];
+            TheISA::initCPU(src_tc, src_tc->contextId());
+            // Initialise the ThreadContext's memory proxies
+            thread[tid]->initMemProxies(thread[tid]->getTC());
+        }
     }
-#endif
 
     // Clear inSyscall.
     for (int tid = 0; tid < numThreads; ++tid)
@@ -813,11 +807,11 @@ FullO3CPU<Impl>::insertThread(ThreadID tid)
     DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
     // Will change now that the PC and thread state is internal to the CPU
     // and not in the ThreadContext.
-#if FULL_SYSTEM
-    ThreadContext *src_tc = system->threadContexts[tid];
-#else
-    ThreadContext *src_tc = tcBase(tid);
-#endif
+    ThreadContext *src_tc;
+    if (FullSystem)
+        src_tc = system->threadContexts[tid];
+    else
+        src_tc = tcBase(tid);
 
     //Bind Int Regs to Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
@@ -968,7 +962,6 @@ FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
     }
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 Fault
 FullO3CPU<Impl>::hwrei(ThreadID tid)
@@ -1035,8 +1028,6 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
     this->trap(interrupt, 0, NULL);
 }
 
-#endif
-
 template <class Impl>
 void
 FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
@@ -1045,8 +1036,6 @@ FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
     fault->invoke(this->threadContexts[tid], inst);
 }
 
-#if !FULL_SYSTEM
-
 template <class Impl>
 void
 FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
@@ -1067,8 +1056,6 @@ FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
     --(this->thread[tid]->funcExeInst);
 }
 
-#endif
-
 template <class Impl>
 void
 FullO3CPU<Impl>::serialize(std::ostream &os)
@@ -1662,7 +1649,6 @@ FullO3CPU<Impl>::wakeCPU()
     schedule(tickEvent, nextCycle());
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 FullO3CPU<Impl>::wakeup()
@@ -1675,7 +1661,6 @@ FullO3CPU<Impl>::wakeup()
     DPRINTF(Quiesce, "Suspended Processor woken\n");
     this->threadContexts[0]->activate();
 }
-#endif
 
 template <class Impl>
 ThreadID
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 121253475..165144c1b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -54,7 +54,6 @@
 
 #include "arch/types.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/comm.hh"
@@ -424,12 +423,10 @@ class FullO3CPU : public BaseO3CPU
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
   public:
-#if !FULL_SYSTEM
     /** Executes a syscall.
      * @todo: Determine if this needs to be virtual.
      */
     void syscall(int64_t callnum, ThreadID tid);
-#endif
 
     /** Starts draining the CPU's pipeline of all instructions in
      * order to stop all memory accesses. */
@@ -454,7 +451,6 @@ class FullO3CPU : public BaseO3CPU
     /** Traps to handle given fault. */
     void trap(Fault fault, ThreadID tid, StaticInstPtr inst);
 
-#if FULL_SYSTEM
     /** HW return from error interrupt. */
     Fault hwrei(ThreadID tid);
 
@@ -474,7 +470,6 @@ class FullO3CPU : public BaseO3CPU
 
     /** Check if this address is a valid data address. */
     bool validDataAddr(Addr addr) { return true; }
-#endif
 
     /** Register accessors.  Index refers to the physical register index. */
 
@@ -709,9 +704,7 @@ class FullO3CPU : public BaseO3CPU
     /** Wakes the CPU, rescheduling the CPU if it's not already active. */
     void wakeCPU();
 
-#if FULL_SYSTEM
     virtual void wakeup();
-#endif
 
     /** Gets a free thread id. Use if thread ids change across system. */
     ThreadID getFreeTid();
diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc
index 097dc7181..296ad1793 100644
--- a/src/cpu/o3/cpu_builder.cc
+++ b/src/cpu/o3/cpu_builder.cc
@@ -30,7 +30,6 @@
 
 #include <string>
 
-#include "config/full_system.hh"
 #include "config/use_checker.hh"
 #include "cpu/o3/cpu.hh"
 #include "cpu/o3/impl.hh"
@@ -47,22 +46,23 @@ class DerivO3CPU : public FullO3CPU<O3CPUImpl>
 DerivO3CPU *
 DerivO3CPUParams::create()
 {
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    if (workload.size() > numThreads) {
-        fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
-              workload.size(), numThreads);
-    } else if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    ThreadID actual_num_threads;
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        actual_num_threads = 1;
+    } else {
+        if (workload.size() > numThreads) {
+            fatal("Workload Size (%i) > Max Supported Threads (%i) on This CPU",
+                  workload.size(), numThreads);
+        } else if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
+
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        actual_num_threads =
+            (numThreads >= workload.size()) ? numThreads : workload.size();
     }
-    
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        (numThreads >= workload.size()) ? numThreads : workload.size();
-#endif
 
     numThreads = actual_num_threads;
 
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index a523a8b45..985e92826 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -30,13 +30,13 @@
 
 #include "arch/types.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/decode.hh"
 #include "cpu/inst_seq.hh"
 #include "debug/Activity.hh"
 #include "debug/Decode.hh"
 #include "params/DerivO3CPU.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -322,19 +322,18 @@ DefaultDecode<Impl>::squash(ThreadID tid)
 
     if (decodeStatus[tid] == Blocked ||
         decodeStatus[tid] == Unblocking) {
-#if !FULL_SYSTEM
-        // In syscall emulation, we can have both a block and a squash due
-        // to a syscall in the same cycle.  This would cause both signals to
-        // be high.  This shouldn't happen in full system.
-        // @todo: Determine if this still happens.
-        if (toFetch->decodeBlock[tid]) {
-            toFetch->decodeBlock[tid] = 0;
-        } else {
+        if (FullSystem) {
             toFetch->decodeUnblock[tid] = 1;
+        } else {
+            // In syscall emulation, we can have both a block and a squash due
+            // to a syscall in the same cycle.  This would cause both signals
+            // to be high.  This shouldn't happen in full system.
+            // @todo: Determine if this still happens.
+            if (toFetch->decodeBlock[tid])
+                toFetch->decodeBlock[tid] = 0;
+            else
+                toFetch->decodeUnblock[tid] = 1;
         }
-#else
-        toFetch->decodeUnblock[tid] = 1;
-#endif
     }
 
     // Set status to squashing.
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index e58eb99c5..1b101ede9 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -199,13 +199,11 @@ class BaseO3DynInst : public BaseDynInst<Impl>
                 this->setFloatRegOperandBits(this->staticInst.get(), idx, this->cpu->readFloatRegBits(prev_phys_reg));
         }
     }
-#if FULL_SYSTEM
     /** Calls hardware return from error interrupt. */
     Fault hwrei();
     /** Traps to handle specified fault. */
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
-#endif
 
     /** Emulates a syscall. */
     void syscall(int64_t callnum);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 500d63de8..76a456ee3 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -42,6 +42,7 @@
 
 #include "base/cp_annotate.hh"
 #include "cpu/o3/dyn_inst.hh"
+#include "sim/full_system.hh"
 
 template <class Impl>
 BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr staticInst,
@@ -143,7 +144,6 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
     return this->fault;
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 Fault
 BaseO3DynInst<Impl>::hwrei()
@@ -188,15 +188,14 @@ BaseO3DynInst<Impl>::simPalCheck(int palFunc)
 #endif
     return this->cpu->simPalCheck(palFunc, this->threadNumber);
 }
-#endif
 
 template <class Impl>
 void
 BaseO3DynInst<Impl>::syscall(int64_t callnum)
 {
-#if FULL_SYSTEM
-    panic("Syscall emulation isn't available in FS mode.\n");
-#else
+    if (FullSystem)
+        panic("Syscall emulation isn't available in FS mode.\n");
+
     // HACK: check CPU's nextPC before and after syscall. If it
     // changes, update this instruction's nextPC because the syscall
     // must have changed the nextPC.
@@ -206,6 +205,5 @@ BaseO3DynInst<Impl>::syscall(int64_t callnum)
     if (!(curPC == newPC)) {
         this->pcState(newPC);
     }
-#endif
 }
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d145fb099..1b82f8a4c 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -45,7 +45,9 @@
 #include <cstring>
 
 #include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
 #include "arch/utility.hh"
+#include "arch/vtophys.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
@@ -61,12 +63,8 @@
 #include "sim/byteswap.hh"
 #include "sim/core.hh"
 #include "sim/eventq.hh"
-
-#if FULL_SYSTEM
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
-#endif // FULL_SYSTEM
 
 using namespace std;
 
@@ -840,15 +838,15 @@ DefaultFetch<Impl>::tick()
 
     DPRINTF(Fetch, "Running stage.\n");
 
-    #if FULL_SYSTEM
-    if (fromCommit->commitInfo[0].interruptPending) {
-        interruptPending = true;
-    }
+    if (FullSystem) {
+        if (fromCommit->commitInfo[0].interruptPending) {
+            interruptPending = true;
+        }
 
-    if (fromCommit->commitInfo[0].clearInterrupt) {
-        interruptPending = false;
+        if (fromCommit->commitInfo[0].clearInterrupt) {
+            interruptPending = false;
+        }
     }
-#endif
 
     for (threadFetched = 0; threadFetched < numFetchingThreads;
          threadFetched++) {
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index c58361cd6..0d7e0f68f 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -47,7 +47,6 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/lsq.hh"
 #include "cpu/o3/scoreboard.hh"
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 731c67ae6..db127a2da 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -46,7 +46,6 @@
 #include <map>
 #include <queue>
 
-#include "config/full_system.hh"
 #include "cpu/o3/lsq_unit.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/port.hh"
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a11d95f3b..3c1a4eda3 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -44,7 +44,6 @@
 #include "arch/mmapped_ipr.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/timebuf.hh"
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index d04f45cc0..117c955c2 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -35,17 +35,13 @@
 #include <vector>
 
 #include "arch/isa_traits.hh"
+#include "arch/kernel_stats.hh"
 #include "arch/types.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/comm.hh"
 #include "debug/IEW.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#endif
-
 /**
  * Simple physical register file class.
  * Right now this is specific to Alpha until we decide if/how to make things
@@ -174,10 +170,8 @@ class PhysRegFile
     /** Floating point register file. */
     PhysFloatReg *floatRegFile;
 
-#if FULL_SYSTEM
   private:
     int intrflag;                       // interrupt flag
-#endif
 
   private:
     /** CPU pointer. */
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 98c0f231b..04935604e 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -45,7 +45,6 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/registers.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/rename.hh"
 #include "debug/Activity.hh"
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index dcde54a54..0484f519c 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -31,7 +31,6 @@
 
 #include <list>
 
-#include "config/full_system.hh"
 #include "cpu/o3/rob.hh"
 #include "debug/Fetch.hh"
 #include "debug/ROB.hh"
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 6ac745770..ff6ca0093 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -92,24 +92,23 @@ class O3ThreadContext : public ThreadContext
     /** Returns a pointer to the system. */
     virtual System *getSystemPtr() { return cpu->system; }
 
-#if FULL_SYSTEM
     /** Returns a pointer to this thread's kernel statistics. */
     virtual TheISA::Kernel::Statistics *getKernelStats()
     { return thread->kernelStats; }
 
+    /** Returns a pointer to this thread's process. */
+    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
+
     virtual PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
 
     virtual FSTranslatingPortProxy* getVirtProxy();
 
     virtual void initMemProxies(ThreadContext *tc)
     { thread->initMemProxies(tc); }
-#else
+
     virtual SETranslatingPortProxy* getMemProxy()
     { return thread->getMemProxy(); }
 
-    /** Returns a pointer to this thread's process. */
-    virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
-#endif
     /** Returns this thread's status. */
     virtual Status status() const { return thread->status(); }
 
@@ -127,12 +126,11 @@ class O3ThreadContext : public ThreadContext
     /** Set the status to Halted. */
     virtual void halt(int delay = 0);
 
-#if FULL_SYSTEM
     /** Dumps the function profiling information.
      * @todo: Implement.
      */
     virtual void dumpFuncProfile();
-#endif
+
     /** Takes over execution of a thread from another CPU. */
     virtual void takeOverFrom(ThreadContext *old_context);
 
@@ -144,7 +142,6 @@ class O3ThreadContext : public ThreadContext
     /** Unserializes state. */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-#if FULL_SYSTEM
     /** Reads the last tick that this thread was activated on. */
     virtual Tick readLastActivate();
     /** Reads the last tick that this thread was suspended on. */
@@ -154,7 +151,6 @@ class O3ThreadContext : public ThreadContext
     virtual void profileClear();
     /** Samples the function profiling information. */
     virtual void profileSample();
-#endif
 
     /** Copies the architectural registers from another TC into this TC. */
     virtual void copyArchRegs(ThreadContext *tc);
@@ -231,20 +227,18 @@ class O3ThreadContext : public ThreadContext
      * misspeculating, this is set as false. */
     virtual bool misspeculating() { return false; }
 
-#if !FULL_SYSTEM
     /** Executes a syscall in SE mode. */
     virtual void syscall(int64_t callnum)
     { return cpu->syscall(callnum, thread->threadId()); }
 
     /** Reads the funcExeInst counter. */
     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
-#else
+
     /** Returns pointer to the quiesce event. */
     virtual EndQuiesceEvent *getQuiesceEvent()
     {
         return this->thread->quiesceEvent;
     }
-#endif
 
 };
 
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 4c2fee22d..5ba454458 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -41,13 +41,13 @@
  *          Korey Sewell
  */
 
+#include "arch/kernel_stats.hh"
 #include "arch/registers.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/quiesce_event.hh"
 #include "debug/O3CPU.hh"
 
-#if FULL_SYSTEM
 template <class Impl>
 FSTranslatingPortProxy*
 O3ThreadContext<Impl>::getVirtProxy()
@@ -61,18 +61,14 @@ O3ThreadContext<Impl>::dumpFuncProfile()
 {
     thread->dumpFuncProfile();
 }
-#endif
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-#if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
-#else
     assert(getProcessPtr() == old_context->getProcessPtr());
-#endif
 
     // copy over functional state
     setStatus(old_context->status());
@@ -80,24 +76,23 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     setContextId(old_context->contextId());
     setThreadId(old_context->threadId());
 
-#if !FULL_SYSTEM
-    thread->funcExeInst = old_context->readFuncExeInst();
-#else
-    EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
-    if (other_quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        other_quiesce->tc = this;
+    if (FullSystem) {
+        EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+        if (other_quiesce) {
+            // Point the quiesce event's TC at this TC so that it wakes up
+            // the proper CPU.
+            other_quiesce->tc = this;
+        }
+        if (thread->quiesceEvent) {
+            thread->quiesceEvent->tc = this;
+        }
+
+        // Transfer kernel stats from one CPU to the other.
+        thread->kernelStats = old_context->getKernelStats();
+        cpu->lockFlag = false;
+    } else {
+        thread->funcExeInst = old_context->readFuncExeInst();
     }
-    if (thread->quiesceEvent) {
-        thread->quiesceEvent->tc = this;
-    }
-
-    // Transfer kernel stats from one CPU to the other.
-    thread->kernelStats = old_context->getKernelStats();
-//    storeCondFailures = 0;
-    cpu->lockFlag = false;
-#endif
 
     old_context->setStatus(ThreadContext::Halted);
 
@@ -115,10 +110,7 @@ O3ThreadContext<Impl>::activate(int delay)
     if (thread->status() == ThreadContext::Active)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
-#endif
-
     thread->setStatus(ThreadContext::Active);
 
     // status() == Suspended
@@ -135,19 +127,9 @@ O3ThreadContext<Impl>::suspend(int delay)
     if (thread->status() == ThreadContext::Suspended)
         return;
 
-#if FULL_SYSTEM
     thread->lastActivate = curTick();
     thread->lastSuspend = curTick();
-#endif
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->checkInterrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
+
     thread->setStatus(ThreadContext::Suspended);
     cpu->suspendContext(thread->threadId());
 }
@@ -170,35 +152,28 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::serialize(std::ostream &os)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->serialize(os);
-#endif
-
 }
 
 template <class Impl>
 void
 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 {
-#if FULL_SYSTEM
-    if (thread->kernelStats)
+    if (FullSystem && thread->kernelStats)
         thread->kernelStats->unserialize(cp, section);
-#endif
-
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 Tick
 O3ThreadContext<Impl>::readLastActivate()
@@ -226,7 +201,6 @@ O3ThreadContext<Impl>::profileSample()
 {
     thread->profileSample();
 }
-#endif
 
 template <class Impl>
 void
@@ -237,9 +211,8 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
     TheISA::copyRegs(tc, this);
     thread->inSyscall = false;
 
-#if !FULL_SYSTEM
-    this->thread->funcExeInst = tc->readFuncExeInst();
-#endif
+    if (!FullSystem)
+        this->thread->funcExeInst = tc->readFuncExeInst();
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 1171053b9..9273b00da 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -35,19 +35,15 @@
 #include "base/output.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_exit.hh"
 
-class Event;
-class Process;
-
-#if FULL_SYSTEM
 class EndQuiesceEvent;
-class FunctionProfile;
-class ProfileNode;
-#else
+class Event;
 class FunctionalMemory;
+class FunctionProfile;
 class Process;
-#endif
+class ProfileNode;
 
 /**
  * Class that has various thread state, such as the status, the
@@ -75,13 +71,16 @@ struct O3ThreadState : public ThreadState {
      */
     bool trapPending;
 
-#if FULL_SYSTEM
-    O3ThreadState(O3CPU *_cpu, int _thread_num)
-        : ThreadState(_cpu, _thread_num),
+    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
+        : ThreadState(_cpu, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
+        if (!FullSystem)
+            return;
+
         if (cpu->params()->profile) {
-            profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
+            profile = new FunctionProfile(
+                    cpu->params()->system->kernelSymtab);
             Callback *cb =
                 new MakeCallback<O3ThreadState,
                 &O3ThreadState::dumpFuncProfile>(this);
@@ -94,12 +93,6 @@ struct O3ThreadState : public ThreadState {
         profileNode = &dummyNode;
         profilePC = 3;
     }
-#else
-    O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
-        : ThreadState(_cpu, _thread_num, _process),
-          cpu(_cpu), inSyscall(0), trapPending(0)
-    { }
-#endif
 
     /** Pointer to the ThreadContext of this thread. */
     ThreadContext *tc;
@@ -107,18 +100,14 @@ struct O3ThreadState : public ThreadState {
     /** Returns a pointer to the TC of this thread. */
     ThreadContext *getTC() { return tc; }
 
-#if !FULL_SYSTEM
     /** Handles the syscall. */
     void syscall(int64_t callnum) { process->syscall(callnum, tc); }
-#endif
 
-#if FULL_SYSTEM
     void dumpFuncProfile()
     {
         std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
         profile->dump(tc, *os);
     }
-#endif
 };
 
 #endif // __CPU_O3_THREAD_STATE_HH__
diff --git a/src/cpu/ozone/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py
index d4620cd8e..d79418b27 100644
--- a/src/cpu/ozone/SimpleOzoneCPU.py
+++ b/src/cpu/ozone/SimpleOzoneCPU.py
@@ -35,8 +35,7 @@ class SimpleOzoneCPU(BaseCPU):
 
     numThreads = Param.Unsigned("number of HW thread contexts")
 
-    if not buildEnv['FULL_SYSTEM']:
-        mem = Param.FunctionalMemory(NULL, "memory")
+    mem = Param.FunctionalMemory(NULL, "memory")
 
     width = Param.Unsigned("Width")
     frontEndWidth = Param.Unsigned("Front end width")
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh
index 169f328ad..1df0cdf0e 100644
--- a/src/cpu/ozone/back_end_impl.hh
+++ b/src/cpu/ozone/back_end_impl.hh
@@ -1456,7 +1456,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //        thread->funcExeInst--;
 
         if (inst->isNonSpeculative()) {
-#if !FULL_SYSTEM
             // Hack to make sure syscalls aren't executed until all stores
             // write back their data.  This direct communication shouldn't
             // be used for anything other than this.
@@ -1464,7 +1463,6 @@ BackEnd<Impl>::commitInst(int inst_num)
                 DPRINTF(BE, "Waiting for all stores to writeback.\n");
                 return false;
             }
-#endif
 
             DPRINTF(BE, "Encountered a store or non-speculative "
                     "instruction at the head of the ROB, PC %#x.\n",
@@ -1512,7 +1510,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 
     if (inst_fault != NoFault) {
         if (!inst->isNop()) {
-#if FULL_SYSTEM
             DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
                     inst->seqNum, inst->readPC());
 
@@ -1533,10 +1530,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //            generateTrapEvent();
 
             return false;
-#else // !FULL_SYSTEM
-            panic("fault (%d) detected @ PC %08p", inst_fault,
-                  inst->PC);
-#endif // FULL_SYSTEM
         }
     }
 
@@ -1574,7 +1567,6 @@ BackEnd<Impl>::commitInst(int inst_num)
     // Write the done sequence number here.
     toIEW->doneSeqNum = inst->seqNum;
 
-#if FULL_SYSTEM
     int count = 0;
     Addr oldpc;
     do {
@@ -1591,7 +1583,6 @@ BackEnd<Impl>::commitInst(int inst_num)
 //        squashPending = true;
         return false;
     }
-#endif
     return true;
 }
 
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 6baa95658..f4bb03dcc 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -91,11 +91,8 @@ OzoneCheckerParams::create()
     params->dtb = dtb;
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
-#else
     params->process = workload;
-#endif
 
     OzoneChecker *cpu = new OzoneChecker(params);
     return cpu;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 541fea44c..ff43ad6cb 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -33,8 +33,8 @@
 
 #include <set>
 
+#include "arch/alpha/tlb.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/rename_table.hh"
 #include "cpu/ozone/thread_state.hh"
@@ -48,31 +48,20 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#if FULL_SYSTEM
-#include "arch/alpha/tlb.hh"
-
-namespace TheISA
-{
-    class TLB;
-}
-class PhysicalMemory;
-class MemoryController;
 
 namespace TheISA {
     namespace Kernel {
         class Statistics;
     };
+    class TLB;
 };
 
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
-
 class Checkpoint;
 class EndQuiesceEvent;
+class MemoryController;
 class MemObject;
+class PhysicalMemory;
+class Process;
 class Request;
 
 namespace Trace {
@@ -116,7 +105,6 @@ class OzoneCPU : public BaseCPU
 
         TheISA::TLB * getDTBPtr() { return cpu->dtb; }
 
-#if FULL_SYSTEM
         System *getSystemPtr() { return cpu->system; }
 
         PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
@@ -124,15 +112,14 @@ class OzoneCPU : public BaseCPU
         TheISA::Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
 
+        Process *getProcessPtr() { return thread->getProcessPtr(); }
+
         PortProxy* getPhysProxy() { return thread->getPhysProxy(); }
 
         FSTranslatingPortProxy* getVirtProxy()
         { return thread->getVirtProxy(); }
-#else
-        SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
 
-        Process *getProcessPtr() { return thread->getProcessPtr(); }
-#endif
+        SETranslatingPortProxy* getMemProxy() { return thread->getMemProxy(); }
 
         Status status() const { return thread->status(); }
 
@@ -148,9 +135,7 @@ class OzoneCPU : public BaseCPU
         /// Set the status to Halted.
         void halt();
 
-#if FULL_SYSTEM
         void dumpFuncProfile();
-#endif
 
         void takeOverFrom(ThreadContext *old_context);
 
@@ -159,7 +144,6 @@ class OzoneCPU : public BaseCPU
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
 
-#if FULL_SYSTEM
         EndQuiesceEvent *getQuiesceEvent();
 
         Tick readLastActivate();
@@ -167,7 +151,6 @@ class OzoneCPU : public BaseCPU
 
         void profileClear();
         void profileSample();
-#endif
 
         int threadId();
 
@@ -227,12 +210,10 @@ class OzoneCPU : public BaseCPU
 
         bool misspeculating() { return false; }
 
-#if !FULL_SYSTEM
         Counter readFuncExeInst() { return thread->funcExeInst; }
 
         void setFuncExeInst(Counter new_val)
         { thread->funcExeInst = new_val; }
-#endif
     };
 
     // Ozone specific thread context
@@ -326,7 +307,6 @@ class OzoneCPU : public BaseCPU
 
     int switchCount;
 
-#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -335,7 +315,6 @@ class OzoneCPU : public BaseCPU
     TheISA::TLB *dtb;
     System *system;
     PhysicalMemory *physmem;
-#endif
 
     virtual Port *getPort(const std::string &name, int idx);
 
@@ -414,13 +393,10 @@ class OzoneCPU : public BaseCPU
 
     void dumpInsts() { frontEnd->dumpInsts(); }
 
-#if FULL_SYSTEM
     Fault hwrei();
     bool simPalCheck(int palFunc);
     void processInterrupts();
-#else
     void syscall(uint64_t &callnum);
-#endif
 
     ThreadContext *tcBase() { return tc; }
 
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 63b7eb6ff..65f68152f 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -57,21 +57,20 @@ DerivOzoneCPUParams::create()
 {
     DerivOzoneCPU *cpu;
 
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        numThreads.isValid() ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        ThreadID actual_num_threads = 1;
+    } else {
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        ThreadID actual_num_threads =
+            numThreads.isValid() ? numThreads : workload.size();
+
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
 
-#endif
-
     SimpleParams *params = new SimpleParams;
 
     params->clock = clock;
@@ -84,15 +83,11 @@ DerivOzoneCPUParams::create()
 
     params->system = system;
     params->cpu_id = cpu_id;
-#if FULL_SYSTEM
     params->profile = profile;
     params->do_quiesce = do_quiesce;
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
-#else
     params->workload = workload;
-//    params->pTable = page_table;
-#endif // FULL_SYSTEM
 
     params->checker = checker;
     params->max_insts_any_thread = max_insts_any_thread;
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 273d46bdc..f532078fe 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -29,37 +29,33 @@
  *          Nathan Binkert
  */
 
+#include "arch/alpha/osfpal.hh"
+#include "arch/faults.hh"
 #include "arch/isa_traits.hh" // For MachInst
+#include "arch/kernel_stats.hh"
+#include "arch/tlb.hh"
+#include "arch/types.hh"
+#include "arch/vtophys.hh"
+#include "base/callback.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/ozone/cpu.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/profile.hh"
 #include "cpu/quiesce_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-
-#if FULL_SYSTEM
-#include "arch/alpha/osfpal.hh"
-#include "arch/faults.hh"
-#include "arch/kernel_stats.hh"
-#include "arch/tlb.hh"
-#include "arch/types.hh"
-#include "arch/vtophys.hh"
-#include "base/callback.hh"
-#include "cpu/profile.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
 #include "sim/system.hh"
-#else // !FULL_SYSTEM
-#include "sim/process.hh"
-#endif // FULL_SYSTEM
 
 #if USE_CHECKER
 #include "cpu/checker/thread_context.hh"
@@ -89,12 +85,8 @@ OzoneCPU<Impl>::TickEvent::description() const
 
 template <class Impl>
 OzoneCPU<Impl>::OzoneCPU(Params *p)
-#if FULL_SYSTEM
-    : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
-#else
-    : BaseCPU(p), thread(this, 0, p->workload[0], 0),
-      tickEvent(this, p->width),
-#endif
+    : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this,
+            p->width),
 #ifndef NDEBUG
       instcount(0),
 #endif
@@ -109,9 +101,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 #if USE_CHECKER
         BaseCPU *temp_checker = p->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
-#if FULL_SYSTEM
         checker->setSystem(p->system);
-#endif
         checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
         thread.tc = checkerTC;
         tc = checkerTC;
@@ -133,33 +123,35 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 
     itb = p->itb;
     dtb = p->dtb;
-#if FULL_SYSTEM
-    // Setup thread state stuff.
-    thread.cpu = this;
-    thread.setTid(0);
-
-    thread.quiesceEvent = new EndQuiesceEvent(tc);
-
-    system = p->system;
-    physmem = p->system->physmem;
-
-    if (p->profile) {
-        thread.profile = new FunctionProfile(p->system->kernelSymtab);
-        // @todo: This might be better as an ThreadContext instead of OzoneTC
-        Callback *cb =
-            new MakeCallback<OzoneTC,
-            &OzoneTC::dumpFuncProfile>(&ozoneTC);
-        registerExitCallback(cb);
-    }
 
-    // let's fill with a dummy node for now so we don't get a segfault
-    // on the first cycle when there's no node available.
-    static ProfileNode dummyNode;
-    thread.profileNode = &dummyNode;
-    thread.profilePC = 3;
-#else
-    thread.cpu = this;
-#endif // !FULL_SYSTEM
+    if (FullSystem) {
+        // Setup thread state stuff.
+        thread.cpu = this;
+        thread.setTid(0);
+
+        thread.quiesceEvent = new EndQuiesceEvent(tc);
+
+        system = p->system;
+        physmem = p->system->physmem;
+
+        if (p->profile) {
+            thread.profile = new FunctionProfile(p->system->kernelSymtab);
+            // @todo: This might be better as an ThreadContext instead of
+            // OzoneTC
+            Callback *cb =
+                new MakeCallback<OzoneTC,
+                &OzoneTC::dumpFuncProfile>(&ozoneTC);
+            registerExitCallback(cb);
+        }
+
+        // let's fill with a dummy node for now so we don't get a segfault
+        // on the first cycle when there's no node available.
+        static ProfileNode dummyNode;
+        thread.profileNode = &dummyNode;
+        thread.profilePC = 3;
+    } else {
+        thread.cpu = this;
+    }
 
     numInst = 0;
     startNumInst = 0;
@@ -194,9 +186,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
-#if FULL_SYSTEM
     thread.connectMemPorts(tc);
-#endif
 
     DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
 }
@@ -305,10 +295,8 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay)
     notIdleFraction++;
     scheduleTickEvent(delay);
     _status = Running;
-#if FULL_SYSTEM
     if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
         thread.quiesceEvent->deschedule();
-#endif
     thread.setStatus(ThreadContext::Active);
     frontEnd->wakeFromQuiesce();
 }
@@ -398,14 +386,14 @@ OzoneCPU<Impl>::init()
 
     // Mark this as in syscall so it won't need to squash
     thread.inSyscall = true;
-#if FULL_SYSTEM
-    for (int i = 0; i < threadContexts.size(); ++i) {
-        ThreadContext *tc = threadContexts[i];
+    if (FullSystem) {
+        for (int i = 0; i < threadContexts.size(); ++i) {
+            ThreadContext *tc = threadContexts[i];
 
-        // initialize CPU, including PC
-        TheISA::initCPU(tc, tc->contextId());
+            // initialize CPU, including PC
+            TheISA::initCPU(tc, tc->contextId());
+        }
     }
-#endif
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 
@@ -464,29 +452,24 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
     thread.getTC()->copyArchRegs(temp.getTC());
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 Addr
 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
 {
     return vtophys(tc, addr);
 }
-#endif // FULL_SYSTEM
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::wakeup()
 {
     if (_status == Idle) {
         DPRINTF(IPI,"Suspended Processor awoke\n");
-//      thread.activate();
         // Hack for now.  Otherwise might have to go through the tc, or
         // I need to figure out what's the right thing to call.
         activateContext(thread.threadId(), 1);
     }
 }
-#endif // FULL_SYSTEM
 
 /* start simulation, program loaded, processor precise state initialized */
 template <class Impl>
@@ -519,7 +502,6 @@ OzoneCPU<Impl>::squashFromTC()
     backEnd->generateTCEvent();
 }
 
-#if !FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::syscall(uint64_t &callnum)
@@ -542,7 +524,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
     frontEnd->renameTable.copyFrom(thread.renameTable);
     backEnd->renameTable.copyFrom(thread.renameTable);
 }
-#else
+
 template <class Impl>
 Fault
 OzoneCPU<Impl>::hwrei()
@@ -600,7 +582,6 @@ OzoneCPU<Impl>::simPalCheck(int palFunc)
 
     return true;
 }
-#endif
 
 template <class Impl>
 BaseCPU *
@@ -639,25 +620,20 @@ OzoneCPU<Impl>::OzoneTC::halt()
     cpu->haltContext(thread->threadId());
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
 {
     thread->dumpFuncProfile();
 }
-#endif
 
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
 {
     // some things should already be set up
-#if FULL_SYSTEM
     assert(getSystemPtr() == old_context->getSystemPtr());
-#else
     assert(getProcessPtr() == old_context->getProcessPtr());
-#endif
 
     // copy over functional state
     setStatus(old_context->status());
@@ -665,9 +641,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
     setCpuId(old_context->cpuId());
     setContextId(old_context->contextId());
 
-#if !FULL_SYSTEM
     setFuncExeInst(old_context->readFuncExeInst());
-#else
     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
     if (other_quiesce) {
         // Point the quiesce event's TC at this TC so that it wakes up
@@ -691,10 +665,10 @@ template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
 {
-#if FULL_SYSTEM
-    thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
-    thread->kernelStats->regStats(name + ".kern");
-#endif
+    if (FullSystem) {
+        thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
+        thread->kernelStats->regStats(name + ".kern");
+    }
 }
 
 template <class Impl>
@@ -711,7 +685,6 @@ void
 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section)
 { }
 
-#if FULL_SYSTEM
 template <class Impl>
 EndQuiesceEvent *
 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
@@ -746,7 +719,6 @@ OzoneCPU<Impl>::OzoneTC::profileSample()
 {
     thread->profileSample();
 }
-#endif
 
 template <class Impl>
 int
@@ -781,9 +753,7 @@ OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
         thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
     }
 
-#if !FULL_SYSTEM
     thread->funcExeInst = tc->readFuncExeInst();
-#endif
 
     // Need to copy the TC values into the current rename table,
     // copy the misc regs.
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index c1853b1ed..b5c0bee7c 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -36,7 +36,6 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/cpu.hh"   // MUST include this
 #include "cpu/ozone/ozone_impl.hh"
@@ -214,13 +213,10 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
     void setMiscReg(int misc_reg, const MiscReg &val);
 
-#if FULL_SYSTEM
     Fault hwrei();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);
-#else
     void syscall(uint64_t &callnum);
-#endif
 
     ListIt iqIt;
     bool iqItValid;
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 5eb8ea8da..96d326ffc 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -28,14 +28,10 @@
  * Authors: Kevin Lim
  */
 
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/dyn_inst.hh"
-#include "sim/faults.hh"
-
-#if FULL_SYSTEM
 #include "kern/kernel_stats.hh"
-#endif
+#include "sim/faults.hh"
 
 template <class Impl>
 OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
@@ -239,8 +235,6 @@ OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
     this->thread->setMiscReg(misc_reg, val);
 }
 
-#if FULL_SYSTEM
-
 template <class Impl>
 Fault
 OzoneDynInst<Impl>::hwrei()
@@ -269,11 +263,10 @@ OzoneDynInst<Impl>::simPalCheck(int palFunc)
 {
     return this->cpu->simPalCheck(palFunc);
 }
-#else
+
 template <class Impl>
 void
 OzoneDynInst<Impl>::syscall(uint64_t &callnum)
 {
     this->cpu->syscall(callnum);
 }
-#endif
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index a11cf74bd..e7255d75f 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -426,13 +426,10 @@ FrontEnd<Impl>::tick()
         numInstsReady[0]++;
         ++num_inst;
 
-#if FULL_SYSTEM
         if (inst->isQuiesce()) {
-//            warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
             status = QuiescePending;
             break;
         }
-#endif
 
         if (inst->predTaken()) {
             // Start over with tick?
@@ -980,9 +977,6 @@ FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
 
     cacheBlkValid = false;
 
-#if !FULL_SYSTEM
-//    pTable = params->pTable;
-#endif
     fetchFault = NoFault;
     serializeNext = false;
     barrierInst = NULL;
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 5c2f9c28f..820e7d33b 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -73,9 +73,7 @@ class InorderBackEnd
 
     void regStats() { }
 
-#if FULL_SYSTEM
     void checkInterrupts();
-#endif
 
     void tick();
     void executeInsts();
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 13c066fd2..59d1dab0d 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -79,7 +79,6 @@ InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
     thread->setFuncExeInst(0);
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 InorderBackEnd<Impl>::checkInterrupts()
@@ -134,7 +133,6 @@ InorderBackEnd<Impl>::checkInterrupts()
         setSquashInfoFromXC();
     }
 }
-#endif
 
 template <class Impl>
 void
@@ -149,8 +147,7 @@ InorderBackEnd<Impl>::tick()
 
     // if (interrupt) then set thread PC, stall front end, record that
     // I'm waiting for it to drain.  (for now just squash)
-#if FULL_SYSTEM
-    if (interruptBlocked || cpu->checkInterrupts(tc)) {
+    if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) {
         if (!robEmpty()) {
             interruptBlocked = true;
         //AlphaDep
@@ -165,7 +162,6 @@ InorderBackEnd<Impl>::tick()
             return;
         }
     }
-#endif
 
     if (status != DcacheMissLoadStall &&
         status != DcacheMissStoreStall) {
@@ -180,15 +176,11 @@ InorderBackEnd<Impl>::tick()
             (*instsAdded)++;
         }
 
-#if FULL_SYSTEM
         if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
             handleFault();
         } else {
             executeInsts();
         }
-#else
-        executeInsts();
-#endif
     }
 }
 
@@ -209,24 +201,24 @@ InorderBackEnd<Impl>::executeInsts()
         thread->setPC(commitPC);
         thread->setNextPC(inst->readNextPC());
 
-#if FULL_SYSTEM
-        int count = 0;
-        Addr oldpc;
-        do {
-            if (count == 0)
-                assert(!thread->inSyscall && !thread->trapPending);
-            oldpc = thread->readPC();
-            cpu->system->pcEventQueue.service(
-                thread->getXCProxy());
-            count++;
-        } while (oldpc != thread->readPC());
-        if (count > 1) {
-            DPRINTF(IBE, "PC skip function event, stopping commit\n");
-            completed_last_inst = false;
-            squashPending = true;
-            break;
+        if (FullSystem) {
+            int count = 0;
+            Addr oldpc;
+            do {
+                if (count == 0)
+                    assert(!thread->inSyscall && !thread->trapPending);
+                oldpc = thread->readPC();
+                cpu->system->pcEventQueue.service(
+                    thread->getXCProxy());
+                count++;
+            } while (oldpc != thread->readPC());
+            if (count > 1) {
+                DPRINTF(IBE, "PC skip function event, stopping commit\n");
+                completed_last_inst = false;
+                squashPending = true;
+                break;
+            }
         }
-#endif
 
         Fault inst_fault = NoFault;
 
@@ -296,7 +288,6 @@ InorderBackEnd<Impl>::executeInsts()
         }
 
         if (inst_fault != NoFault) {
-#if FULL_SYSTEM
             DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
                     inst->seqNum, inst->readPC());
 
@@ -313,14 +304,8 @@ InorderBackEnd<Impl>::executeInsts()
 
             squashPending = true;
 
-            // Generate trap squash event.
-//            generateTrapEvent(tid);
             completed_last_inst = false;
             break;
-#else // !FULL_SYSTEM
-            panic("fault (%d) detected @ PC %08p", inst_fault,
-                  inst->PC);
-#endif // FULL_SYSTEM
         }
 
         for (int i = 0; i < inst->numDestRegs(); ++i) {
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index 1d8328610..c812a10a2 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -38,7 +38,6 @@
 #include "arch/faults.hh"
 #include "arch/types.hh"
 #include "base/hashmap.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/mem_interface.hh"
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index 880d0d183..c06a58754 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -520,7 +520,6 @@ LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
     fromCommit = comm->getWire(-1);
 }
 
-#if FULL_SYSTEM
 template <class Impl>
 void
 LWBackEnd<Impl>::checkInterrupts()
@@ -557,7 +556,6 @@ LWBackEnd<Impl>::checkInterrupts()
         }
     }
 }
-#endif
 
 template <class Impl>
 void
@@ -604,9 +602,7 @@ LWBackEnd<Impl>::tick()
 
     wbCycle = 0;
 
-#if FULL_SYSTEM
     checkInterrupts();
-#endif
 
     if (trapSquash) {
         assert(!tcSquash);
@@ -1049,16 +1045,8 @@ LWBackEnd<Impl>::commitInst(int inst_num)
             (inst->isStoreConditional() && inst->getFault() == NoFault) ||
             inst->isMemBarrier() ||
             inst->isWriteBarrier()) {
-#if !FULL_SYSTEM
-            // Hack to make sure syscalls aren't executed until all stores
-            // write back their data.  This direct communication shouldn't
-            // be used for anything other than this.
-            if (inst_num > 0 || LSQ.hasStoresToWB())
-#else
             if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
-                    inst->isQuiesce()) &&
-                LSQ.hasStoresToWB())
-#endif
+                    inst->isQuiesce()) && LSQ.hasStoresToWB())
             {
                 DPRINTF(BE, "Waiting for all stores to writeback.\n");
                 return false;
@@ -1184,11 +1172,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         ++freed_regs;
     }
 
-#if FULL_SYSTEM
-    if (thread->profile) {
-//        bool usermode =
-//            (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
-//        thread->profilePC = usermode ? 1 : inst->readPC();
+    if (FullSystem && thread->profile) {
         thread->profilePC = inst->readPC();
         ProfileNode *node = thread->profile->consume(thread->getTC(),
                                                      inst->staticInst);
@@ -1196,7 +1180,6 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         if (node)
             thread->profileNode = node;
     }
-#endif
 
     if (inst->traceData) {
         inst->traceData->setFetchSeq(inst->seqNum);
@@ -1225,23 +1208,23 @@ LWBackEnd<Impl>::commitInst(int inst_num)
     toIEW->doneSeqNum = inst->seqNum;
     lastCommitCycle = curTick();
 
-#if FULL_SYSTEM
-    int count = 0;
-    Addr oldpc;
-    do {
-        if (count == 0)
-            assert(!thread->inSyscall && !thread->trapPending);
-        oldpc = thread->readPC();
-        cpu->system->pcEventQueue.service(
-            thread->getTC());
-        count++;
-    } while (oldpc != thread->readPC());
-    if (count > 1) {
-        DPRINTF(BE, "PC skip function event, stopping commit\n");
-        tcSquash = true;
-        return false;
+    if (FullSystem) {
+        int count = 0;
+        Addr oldpc;
+        do {
+            if (count == 0)
+                assert(!thread->inSyscall && !thread->trapPending);
+            oldpc = thread->readPC();
+            cpu->system->pcEventQueue.service(
+                thread->getTC());
+            count++;
+        } while (oldpc != thread->readPC());
+        if (count > 1) {
+            DPRINTF(BE, "PC skip function event, stopping commit\n");
+            tcSquash = true;
+            return false;
+        }
     }
-#endif
     return true;
 }
 
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 1add13894..dd573e5e0 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -40,7 +40,6 @@
 #include "arch/types.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/packet.hh"
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index f4446ede3..512dc3b9e 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -60,21 +60,20 @@ SimpleOzoneCPUParams::create()
 {
     SimpleOzoneCPU *cpu;
 
-#if FULL_SYSTEM
-    // Full-system only supports a single thread for the moment.
-    ThreadID actual_num_threads = 1;
-#else
-    // In non-full-system mode, we infer the number of threads from
-    // the workload if it's not explicitly specified.
-    ThreadID actual_num_threads =
-        numThreads.isValid() ? numThreads : workload.size();
-
-    if (workload.size() == 0) {
-        fatal("Must specify at least one workload!");
+    if (FullSystem) {
+        // Full-system only supports a single thread for the moment.
+        ThreadID actual_num_threads = 1;
+    } else {
+        // In non-full-system mode, we infer the number of threads from
+        // the workload if it's not explicitly specified.
+        ThreadID actual_num_threads =
+            numThreads.isValid() ? numThreads : workload.size();
+
+        if (workload.size() == 0) {
+            fatal("Must specify at least one workload!");
+        }
     }
 
-#endif
-
     SimpleParams *params = new SimpleParams;
 
     params->clock = clock;
@@ -87,10 +86,7 @@ SimpleOzoneCPUParams::create()
 
     params->system = system;
     params->cpu_id = cpu_id;
-#if !FULL_SYSTEM
     params->workload = workload;
-//    params->pTable = page_table;
-#endif // FULL_SYSTEM
 
     params->mem = mem;
     params->checker = checker;
diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index b241dea73..228b78128 100644
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -56,9 +56,7 @@ class SimpleParams : public BaseCPU::Params
   public:
 
     TheISA::TLB *itb; TheISA::TLB *dtb;
-#if !FULL_SYSTEM
     std::vector<Process *> workload;
-#endif // FULL_SYSTEM
 
     //Page Table
     PageTable *pTable;
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 638b9d86c..98ecd850c 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -45,14 +45,11 @@
 class Event;
 //class Process;
 
-#if FULL_SYSTEM
 class EndQuiesceEvent;
+class FunctionalMemory;
 class FunctionProfile;
-class ProfileNode;
-#else
 class Process;
-class FunctionalMemory;
-#endif
+class ProfileNode;
 
 // Maybe this ozone thread state should only really have committed state?
 // I need to think about why I'm using this and what it's useful for.  Clearly
@@ -66,7 +63,6 @@ struct OzoneThreadState : public ThreadState {
     typedef typename Impl::CPUType CPUType;
     typedef TheISA::MiscReg MiscReg;
 
-#if FULL_SYSTEM
     OzoneThreadState(CPUType *_cpu, int _thread_num)
         : ThreadState(_cpu, -1, _thread_num),
           intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
@@ -86,14 +82,13 @@ struct OzoneThreadState : public ThreadState {
         profilePC = 3;
         miscRegFile.clear();
     }
-#else
+
     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
         : ThreadState(_cpu, -1, _thread_num, _process),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         miscRegFile.clear();
     }
-#endif
 
     RenameTable<Impl> renameTable;
 
@@ -147,13 +142,11 @@ struct OzoneThreadState : public ThreadState {
     void setNextPC(uint64_t val)
     { nextPC = val; }
 
-#if FULL_SYSTEM
     void dumpFuncProfile()
     {
         std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
         profile->dump(tc, *os);
     }
-#endif
 };
 
 #endif // __CPU_OZONE_THREAD_STATE_HH__
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index 385a83b27..9cf63f7d3 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -36,7 +36,6 @@
 
 #include "base/debug.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/thread_context.hh"
@@ -140,7 +139,6 @@ BreakPCEvent::process(ThreadContext *tc)
         delete this;
 }
 
-#if FULL_SYSTEM
 void
 sched_break_pc_sys(System *sys, Addr addr)
 {
@@ -156,4 +154,3 @@ sched_break_pc(Addr addr)
     }
 
 }
-#endif
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 425c8b1f1..2c12b244b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -42,6 +42,7 @@
 #include "params/AtomicSimpleCPU.hh"
 #include "sim/faults.hh"
 #include "sim/system.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -83,18 +84,18 @@ void
 AtomicSimpleCPU::init()
 {
     BaseCPU::init();
-#if FULL_SYSTEM
-    ThreadID size = threadContexts.size();
-    for (ThreadID i = 0; i < size; ++i) {
-        ThreadContext *tc = threadContexts[i];
-
-        // initialize CPU, including PC
-        TheISA::initCPU(tc, tc->contextId());
+    if (FullSystem) {
+        ThreadID size = threadContexts.size();
+        for (ThreadID i = 0; i < size; ++i) {
+            ThreadContext *tc = threadContexts[i];
+            // initialize CPU, including PC
+            TheISA::initCPU(tc, tc->contextId());
+        }
     }
 
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
-#endif
+
     if (hasPhysMemPort) {
         AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
         physMemAddr = *pmAddrList.begin();
@@ -560,9 +561,7 @@ AtomicSimpleCPU *
 AtomicSimpleCPUParams::create()
 {
     numThreads = 1;
-#if !FULL_SYSTEM
-    if (workload.size() != 1)
+    if (!FullSystem && workload.size() != 1)
         panic("only one workload allowed");
-#endif
     return new AtomicSimpleCPU(this);
 }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 70e2c39e6..610cc6b89 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -41,7 +41,11 @@
  */
 
 #include "arch/faults.hh"
+#include "arch/kernel_stats.hh"
+#include "arch/stacktrace.hh"
+#include "arch/tlb.hh"
 #include "arch/utility.hh"
+#include "arch/vtophys.hh"
 #include "base/loader/symtab.hh"
 #include "base/cp_annotate.hh"
 #include "base/cprintf.hh"
@@ -63,37 +67,29 @@
 #include "debug/Decode.hh"
 #include "debug/Fetch.hh"
 #include "debug/Quiesce.hh"
+#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 #include "params/BaseSimpleCPU.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/stacktrace.hh"
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
-#else // !FULL_SYSTEM
-#include "mem/mem_object.hh"
-#endif // FULL_SYSTEM
-
 using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
 {
-#if FULL_SYSTEM
-    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
-#else
-    thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
-            p->itb, p->dtb);
-#endif // !FULL_SYSTEM
+    if (FullSystem)
+        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+    else
+        thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
+                p->itb, p->dtb);
 
     thread->setStatus(ThreadContext::Halted);
 
@@ -290,15 +286,12 @@ change_thread_state(ThreadID tid, int activate, int priority)
 {
 }
 
-#if FULL_SYSTEM
 Addr
 BaseSimpleCPU::dbg_vtophys(Addr addr)
 {
     return vtophys(tc, addr);
 }
-#endif // FULL_SYSTEM
 
-#if FULL_SYSTEM
 void
 BaseSimpleCPU::wakeup()
 {
@@ -308,12 +301,10 @@ BaseSimpleCPU::wakeup()
     DPRINTF(Quiesce,"Suspended Processor awoke\n");
     thread->activate();
 }
-#endif // FULL_SYSTEM
 
 void
 BaseSimpleCPU::checkForInterrupts()
 {
-#if FULL_SYSTEM
     if (checkInterrupts(tc)) {
         Fault interrupt = interrupts->getInterrupt(tc);
 
@@ -324,7 +315,6 @@ BaseSimpleCPU::checkForInterrupts()
             predecoder.reset();
         }
     }
-#endif
 }
 
 
@@ -422,15 +412,13 @@ BaseSimpleCPU::postExecute()
 
     TheISA::PCState pc = tc->pcState();
     Addr instAddr = pc.instAddr();
-#if FULL_SYSTEM
-    if (thread->profile) {
+    if (FullSystem && thread->profile) {
         bool usermode = TheISA::inUserMode(tc);
         thread->profilePC = usermode ? 1 : instAddr;
         ProfileNode *node = thread->profile->consume(tc, curStaticInst);
         if (node)
             thread->profileNode = node;
     }
-#endif
 
     if (curStaticInst->isMemRef()) {
         numMemRefs++;
@@ -478,7 +466,8 @@ BaseSimpleCPU::postExecute()
     }
     /* End power model statistics */
 
-    traceFunctions(instAddr);
+    if (FullSystem)
+        traceFunctions(instAddr);
 
     if (traceData) {
         traceData->dump();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index ad281aa2b..0e5526040 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -35,7 +35,6 @@
 
 #include "arch/predecoder.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/decode.hh"
@@ -46,30 +45,22 @@
 #include "mem/port.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 // forward declarations
-#if FULL_SYSTEM
-class Processor;
-namespace TheISA
-{
-    class ITB;
-    class DTB;
-}
+class Checkpoint;
 class MemObject;
-
-#else
-
 class Process;
-
-#endif // FULL_SYSTEM
+class Processor;
+class ThreadContext;
 
 namespace TheISA
 {
+    class DTB;
+    class ITB;
     class Predecoder;
 }
-class ThreadContext;
-class Checkpoint;
 
 namespace Trace {
     class InstRecord;
@@ -141,11 +132,9 @@ class BaseSimpleCPU : public BaseCPU
 
   public:
 
-#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
-#endif
 
     // current instruction
     TheISA::MachInst inst;
@@ -399,19 +388,16 @@ class BaseSimpleCPU : public BaseCPU
 
     //Fault CacheOp(uint8_t Op, Addr EA);
 
-#if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#endif
 
     void
     syscall(int64_t callnum)
     {
-#if FULL_SYSTEM
-        panic("Syscall emulation isn't available in FS mode.\n");
-#else
+        if (FullSystem)
+            panic("Syscall emulation isn't available in FS mode.\n");
+
         thread->syscall(callnum);
-#endif
     }
 
     bool misspeculating() { return thread->misspeculating(); }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f8d13efd9..fd02e8300 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -54,6 +54,7 @@
 #include "mem/packet_access.hh"
 #include "params/TimingSimpleCPU.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -74,17 +75,16 @@ void
 TimingSimpleCPU::init()
 {
     BaseCPU::init();
-#if FULL_SYSTEM
-    for (int i = 0; i < threadContexts.size(); ++i) {
-        ThreadContext *tc = threadContexts[i];
-
-        // initialize CPU, including PC
-        TheISA::initCPU(tc, _cpuId);
+    if (FullSystem) {
+        for (int i = 0; i < threadContexts.size(); ++i) {
+            ThreadContext *tc = threadContexts[i];
+            // initialize CPU, including PC
+            TheISA::initCPU(tc, _cpuId);
+        }
     }
 
     // Initialise the ThreadContext's memory proxies
     tcBase()->initMemProxies(tcBase());
-#endif
 }
 
 void
@@ -966,9 +966,7 @@ TimingSimpleCPU *
 TimingSimpleCPUParams::create()
 {
     numThreads = 1;
-#if !FULL_SYSTEM
-    if (workload.size() != 1)
+    if (!FullSystem && workload.size() != 1)
         panic("only one workload allowed");
-#endif
     return new TimingSimpleCPU(this);
 }
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 2541bdee1..a12ab8e8a 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -34,39 +34,44 @@
 #include <string>
 
 #include "arch/isa_traits.hh"
-#include "arch/utility.hh"
-#include "config/the_isa.hh"
-#include "cpu/base.hh"
-#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
-#include "params/BaseCPU.hh"
-
-#if FULL_SYSTEM
 #include "arch/kernel_stats.hh"
 #include "arch/stacktrace.hh"
+#include "arch/utility.hh"
 #include "base/callback.hh"
 #include "base/cprintf.hh"
 #include "base/output.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
+#include "cpu/base.hh"
 #include "cpu/profile.hh"
 #include "cpu/quiesce_event.hh"
+#include "cpu/simple_thread.hh"
+#include "cpu/thread_context.hh"
+#include "params/BaseCPU.hh"
 #include "mem/fs_translating_port_proxy.hh"
+#include "mem/se_translating_port_proxy.hh"
+#include "sim/full_system.hh"
+#include "sim/process.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_exit.hh"
-#else
-#include "mem/se_translating_port_proxy.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
-#endif
 
 using namespace std;
 
 // constructor
-#if FULL_SYSTEM
+SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
+                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
+    : ThreadState(_cpu, _thread_num, _process),
+      cpu(_cpu), itb(_itb), dtb(_dtb)
+{
+    clearArchRegs();
+    tc = new ProxyThreadContext<SimpleThread>(this);
+}
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num),
+    : ThreadState(_cpu, _thread_num, NULL),
       cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb)
 
 {
@@ -93,24 +98,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
     if (use_kernel_stats)
         kernelStats = new TheISA::Kernel::Statistics(system);
 }
-#else
-SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
-                           TheISA::TLB *_itb, TheISA::TLB *_dtb)
-    : ThreadState(_cpu, _thread_num, _process),
-      cpu(_cpu), itb(_itb), dtb(_dtb)
-{
-    clearArchRegs();
-    tc = new ProxyThreadContext<SimpleThread>(this);
-}
-
-#endif
 
 SimpleThread::SimpleThread()
-#if FULL_SYSTEM
-    : ThreadState(NULL, -1)
-#else
     : ThreadState(NULL, -1, NULL)
-#endif
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
@@ -124,29 +114,27 @@ void
 SimpleThread::takeOverFrom(ThreadContext *oldContext)
 {
     // some things should already be set up
-#if FULL_SYSTEM
-    assert(system == oldContext->getSystemPtr());
-#else
+    if (FullSystem)
+        assert(system == oldContext->getSystemPtr());
     assert(process == oldContext->getProcessPtr());
-#endif
 
     copyState(oldContext);
-#if FULL_SYSTEM
-    EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
-    if (quiesce) {
-        // Point the quiesce event's TC at this TC so that it wakes up
-        // the proper CPU.
-        quiesce->tc = tc;
-    }
-    if (quiesceEvent) {
-        quiesceEvent->tc = tc;
-    }
-
-    TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
-    if (stats) {
-        kernelStats = stats;
+    if (FullSystem) {
+        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
+        if (quiesce) {
+            // Point the quiesce event's TC at this TC so that it wakes up
+            // the proper CPU.
+            quiesce->tc = tc;
+        }
+        if (quiesceEvent) {
+            quiesceEvent->tc = tc;
+        }
+
+        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
+        if (stats) {
+            kernelStats = stats;
+        }
     }
-#endif
 
     storeCondFailures = 0;
 
@@ -158,16 +146,16 @@ SimpleThread::copyTC(ThreadContext *context)
 {
     copyState(context);
 
-#if FULL_SYSTEM
-    EndQuiesceEvent *quiesce = context->getQuiesceEvent();
-    if (quiesce) {
-        quiesceEvent = quiesce;
-    }
-    TheISA::Kernel::Statistics *stats = context->getKernelStats();
-    if (stats) {
-        kernelStats = stats;
+    if (FullSystem) {
+        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
+        if (quiesce) {
+            quiesceEvent = quiesce;
+        }
+        TheISA::Kernel::Statistics *stats = context->getKernelStats();
+        if (stats) {
+            kernelStats = stats;
+        }
     }
-#endif
 }
 
 void
@@ -176,9 +164,8 @@ SimpleThread::copyState(ThreadContext *oldContext)
     // copy over functional state
     _status = oldContext->status();
     copyArchRegs(oldContext);
-#if !FULL_SYSTEM
-    funcExeInst = oldContext->readFuncExeInst();
-#endif
+    if (FullSystem)
+        funcExeInst = oldContext->readFuncExeInst();
 
     _threadId = oldContext->threadId();
     _contextId = oldContext->contextId();
@@ -215,14 +202,12 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     isa.unserialize(cpu, cp, section);
 }
 
-#if FULL_SYSTEM
 void
 SimpleThread::dumpFuncProfile()
 {
     std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
     profile->dump(tc, *os);
 }
-#endif
 
 void
 SimpleThread::activate(int delay)
@@ -251,15 +236,6 @@ SimpleThread::suspend()
 
     lastActivate = curTick();
     lastSuspend = curTick();
-/*
-#if FULL_SYSTEM
-    // Don't change the status from active if there are pending interrupts
-    if (cpu->checkInterrupts()) {
-        assert(status() == ThreadContext::Active);
-        return;
-    }
-#endif
-*/
     _status = ThreadContext::Suspended;
     cpu->suspendContext(_threadId);
 }
@@ -279,10 +255,8 @@ SimpleThread::halt()
 void
 SimpleThread::regStats(const string &name)
 {
-#if FULL_SYSTEM
-    if (kernelStats)
+    if (FullSystem && kernelStats)
         kernelStats->regStats(name + ".kern");
-#endif
 }
 
 void
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index ebc23276a..f2132dc36 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -38,28 +38,27 @@
 #include "arch/tlb.hh"
 #include "arch/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/decode.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
 #include "debug/FloatRegs.hh"
 #include "debug/IntRegs.hh"
+#include "mem/page_table.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
 #include "sim/eventq.hh"
+#include "sim/process.hh"
 #include "sim/serialize.hh"
+#include "sim/system.hh"
 
 class BaseCPU;
 
-#if FULL_SYSTEM
-
-#include "sim/system.hh"
 
 class FunctionProfile;
 class ProfileNode;
-class FunctionalPort;
 class PhysicalPort;
+class TranslatingPort;
 
 namespace TheISA {
     namespace Kernel {
@@ -67,14 +66,6 @@ namespace TheISA {
     };
 };
 
-#else // !FULL_SYSTEM
-
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-class TranslatingPort;
-
-#endif // FULL_SYSTEM
-
 /**
  * The SimpleThread object provides a combination of the ThreadState
  * object and the ThreadContext interface. It implements the
@@ -133,14 +124,13 @@ class SimpleThread : public ThreadState
     Decoder decoder;
 
     // constructor: initialize SimpleThread from given process structure
-#if FULL_SYSTEM
+    // FS
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
                  TheISA::TLB *_itb, TheISA::TLB *_dtb,
                  bool use_kernel_stats = true);
-#else
+    // SE
     SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
                  TheISA::TLB *_itb, TheISA::TLB *_dtb);
-#endif
 
     SimpleThread();
 
@@ -184,15 +174,12 @@ class SimpleThread : public ThreadState
         dtb->demapPage(vaddr, asn);
     }
 
-#if FULL_SYSTEM
     void dumpFuncProfile();
 
     Fault hwrei();
 
     bool simPalCheck(int palFunc);
 
-#endif
-
     /*******************************************
      * ThreadContext interface functions.
      ******************************************/
@@ -207,7 +194,6 @@ class SimpleThread : public ThreadState
 
     System *getSystemPtr() { return system; }
 
-#if FULL_SYSTEM
     PortProxy* getPhysProxy() { return physProxy; }
 
     /** Return a virtual port. This port cannot be cached locally in an object.
@@ -215,7 +201,6 @@ class SimpleThread : public ThreadState
      * mean stale data.
      */
     FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
-#endif
 
     Status status() const { return _status; }
 
@@ -384,12 +369,10 @@ class SimpleThread : public ThreadState
     void setStCondFailures(unsigned sc_failures)
     { storeCondFailures = sc_failures; }
 
-#if !FULL_SYSTEM
     void syscall(int64_t callnum)
     {
         process->syscall(callnum, tc);
     }
-#endif
 };
 
 
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 334bdf4d4..c403667bf 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -56,7 +56,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
             panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
-#if FULL_SYSTEM
     for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
         TheISA::MiscReg t1 = one->readMiscRegNoEffect(i);
         TheISA::MiscReg t2 = two->readMiscRegNoEffect(i);
@@ -64,7 +63,6 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
             panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
     }
-#endif
 
     if (!(one->pcState() == two->pcState()))
         panic("PC state doesn't match.");
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index d80d26e3d..261ace7cf 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -37,7 +37,6 @@
 #include "arch/registers.hh"
 #include "arch/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
@@ -125,7 +124,6 @@ class ThreadContext
 
     virtual System *getSystemPtr() = 0;
 
-#if FULL_SYSTEM
     virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
 
     virtual PortProxy* getPhysProxy() = 0;
@@ -139,11 +137,10 @@ class ThreadContext
      * tc ThreadContext for the virtual-to-physical translation
      */
     virtual void initMemProxies(ThreadContext *tc) = 0;
-#else
+
     virtual SETranslatingPortProxy *getMemProxy() = 0;
 
     virtual Process *getProcessPtr() = 0;
-#endif
 
     virtual Status status() const = 0;
 
@@ -159,9 +156,7 @@ class ThreadContext
     /// Set the status to Halted.
     virtual void halt(int delay = 0) = 0;
 
-#if FULL_SYSTEM
     virtual void dumpFuncProfile() = 0;
-#endif
 
     virtual void takeOverFrom(ThreadContext *old_context) = 0;
 
@@ -170,7 +165,6 @@ class ThreadContext
     virtual void serialize(std::ostream &os) = 0;
     virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
 
-#if FULL_SYSTEM
     virtual EndQuiesceEvent *getQuiesceEvent() = 0;
 
     // Not necessarily the best location for these...
@@ -180,7 +174,6 @@ class ThreadContext
 
     virtual void profileClear() = 0;
     virtual void profileSample() = 0;
-#endif
 
     virtual void copyArchRegs(ThreadContext *tc) = 0;
 
@@ -242,7 +235,6 @@ class ThreadContext
     // Only really makes sense for old CPU model.  Still could be useful though.
     virtual bool misspeculating() = 0;
 
-#if !FULL_SYSTEM
     // Same with st cond failures.
     virtual Counter readFuncExeInst() = 0;
 
@@ -252,7 +244,6 @@ class ThreadContext
     // 1 if the CPU has no more active threads (meaning it's OK to exit);
     // Used in syscall-emulation mode when a  thread calls the exit syscall.
     virtual int exit() { return 1; };
-#endif
 
     /** function to compare two thread contexts (for debugging) */
     static void compare(ThreadContext *one, ThreadContext *two);
@@ -300,7 +291,6 @@ class ProxyThreadContext : public ThreadContext
 
     System *getSystemPtr() { return actualTC->getSystemPtr(); }
 
-#if FULL_SYSTEM
     TheISA::Kernel::Statistics *getKernelStats()
     { return actualTC->getKernelStats(); }
 
@@ -309,11 +299,10 @@ class ProxyThreadContext : public ThreadContext
     FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); }
 
     void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); }
-#else
+
     SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); }
 
     Process *getProcessPtr() { return actualTC->getProcessPtr(); }
-#endif
 
     Status status() const { return actualTC->status(); }
 
@@ -329,9 +318,7 @@ class ProxyThreadContext : public ThreadContext
     /// Set the status to Halted.
     void halt(int delay = 0) { actualTC->halt(); }
 
-#if FULL_SYSTEM
     void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
-#endif
 
     void takeOverFrom(ThreadContext *oldContext)
     { actualTC->takeOverFrom(oldContext); }
@@ -342,7 +329,6 @@ class ProxyThreadContext : public ThreadContext
     void unserialize(Checkpoint *cp, const std::string &section)
     { actualTC->unserialize(cp, section); }
 
-#if FULL_SYSTEM
     EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
 
     Tick readLastActivate() { return actualTC->readLastActivate(); }
@@ -350,7 +336,6 @@ class ProxyThreadContext : public ThreadContext
 
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
-#endif
 
     // @todo: Do I need this?
     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
@@ -418,12 +403,10 @@ class ProxyThreadContext : public ThreadContext
     // @todo: Fix this!
     bool misspeculating() { return actualTC->misspeculating(); }
 
-#if !FULL_SYSTEM
     void syscall(int64_t callnum)
     { actualTC->syscall(callnum); }
 
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
-#endif
 };
 
 #endif
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 6c9bb99ea..ca8b9987e 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -28,52 +28,37 @@
  * Authors: Kevin Lim
  */
 
+#include "arch/kernel_stats.hh"
 #include "base/output.hh"
 #include "cpu/base.hh"
 #include "cpu/profile.hh"
+#include "cpu/quiesce_event.hh"
 #include "cpu/thread_state.hh"
+#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port.hh"
 #include "mem/port_proxy.hh"
 #include "mem/se_translating_port_proxy.hh"
+#include "sim/full_system.hh"
 #include "sim/serialize.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "cpu/quiesce_event.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#endif
-
-#if FULL_SYSTEM
-ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid)
-#else
 ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
-#endif
     : numInst(0), numLoad(0), _status(ThreadContext::Halted),
       baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
-#if FULL_SYSTEM
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
-      kernelStats(NULL), physProxy(NULL), virtProxy(NULL),
-#else
-      proxy(NULL), process(_process),
-#endif
-      funcExeInst(0), storeCondFailures(0)
+      kernelStats(NULL), process(_process), physProxy(NULL), virtProxy(NULL),
+      proxy(NULL), funcExeInst(0), storeCondFailures(0)
 {
 }
 
 ThreadState::~ThreadState()
 {
-#if FULL_SYSTEM
-    if (physProxy != NULL) {
+    if (physProxy != NULL)
         delete physProxy;
-    }
-    if (virtProxy != NULL) {
+    if (virtProxy != NULL)
         delete virtProxy;
-    }
-#else
-    if (proxy != NULL) {
+    if (proxy != NULL)
         delete proxy;
-    }
-#endif
 }
 
 void
@@ -83,14 +68,15 @@ ThreadState::serialize(std::ostream &os)
     // thread_num and cpu_id are deterministic from the config
     SERIALIZE_SCALAR(funcExeInst);
 
-#if FULL_SYSTEM
+    if (!FullSystem)
+        return;
+
     Tick quiesceEndTick = 0;
     if (quiesceEvent->scheduled())
         quiesceEndTick = quiesceEvent->when();
     SERIALIZE_SCALAR(quiesceEndTick);
     if (kernelStats)
         kernelStats->serialize(os);
-#endif
 }
 
 void
@@ -101,17 +87,17 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
     // thread_num and cpu_id are deterministic from the config
     UNSERIALIZE_SCALAR(funcExeInst);
 
-#if FULL_SYSTEM
+    if (!FullSystem)
+        return;
+
     Tick quiesceEndTick;
     UNSERIALIZE_SCALAR(quiesceEndTick);
     if (quiesceEndTick)
         baseCpu->schedule(quiesceEvent, quiesceEndTick);
     if (kernelStats)
         kernelStats->unserialize(cp, section);
-#endif
 }
 
-#if FULL_SYSTEM
 void
 ThreadState::initMemProxies(ThreadContext *tc)
 {
@@ -139,7 +125,6 @@ ThreadState::profileSample()
         profile->sample(profileNode, profilePC);
 }
 
-#else
 SETranslatingPortProxy *
 ThreadState::getMemProxy()
 {
@@ -153,4 +138,3 @@ ThreadState::getMemProxy()
 
     return proxy;
 }
-#endif
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index a007567c1..30bb64ed7 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -36,13 +36,9 @@
 #include "cpu/base.hh"
 #include "cpu/profile.hh"
 #include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
 #include "mem/mem_object.hh"
 #include "sim/process.hh"
-#endif
 
-#if FULL_SYSTEM
 class EndQuiesceEvent;
 class FunctionProfile;
 class ProfileNode;
@@ -51,7 +47,6 @@ namespace TheISA {
         class Statistics;
     };
 };
-#endif
 
 class Checkpoint;
 class PortProxy;
@@ -67,11 +62,7 @@ class FSTranslatingPort;
 struct ThreadState {
     typedef ThreadContext::Status Status;
 
-#if FULL_SYSTEM
-    ThreadState(BaseCPU *cpu, ThreadID _tid);
-#else
     ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
-#endif
 
     ~ThreadState();
 
@@ -93,7 +84,6 @@ struct ThreadState {
 
     Tick readLastSuspend() { return lastSuspend; }
 
-#if FULL_SYSTEM
     /**
      * Initialise the physical and virtual port proxies and tie them to
      * the data port of the CPU.
@@ -115,11 +105,10 @@ struct ThreadState {
     PortProxy* getPhysProxy() { return physProxy; }
 
     FSTranslatingPortProxy* getVirtProxy() { return virtProxy; }
-#else
+
     Process *getProcessPtr() { return process; }
 
     SETranslatingPortProxy* getMemProxy();
-#endif
 
     /** Reads the number of instructions functionally executed and
      * committed.
@@ -173,7 +162,6 @@ struct ThreadState {
     /** Last time suspend was called on this thread. */
     Tick lastSuspend;
 
-#if FULL_SYSTEM
   public:
     FunctionProfile *profile;
     ProfileNode *profileNode;
@@ -181,7 +169,10 @@ struct ThreadState {
     EndQuiesceEvent *quiesceEvent;
 
     TheISA::Kernel::Statistics *kernelStats;
+
   protected:
+    Process *process;
+
     /** A port proxy outgoing only for functional accesses to physical
      * addresses.*/
     PortProxy *physProxy;
@@ -189,12 +180,8 @@ struct ThreadState {
     /** A translating port proxy, outgoing only, for functional
      * accesse to virtual addresses. */
     FSTranslatingPortProxy* virtProxy;
-#else
     SETranslatingPortProxy* proxy;
 
-    Process *process;
-#endif
-
   public:
     /*
      * number of executed instructions, for matching with syscall trace
diff --git a/src/dev/Device.py b/src/dev/Device.py
index aa622aa05..c32946277 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -34,7 +34,6 @@ class PioDevice(MemObject):
     type = 'PioDevice'
     abstract = True
     pio = Port("Programmed I/O port")
-    platform = Param.Platform(Parent.any, "Platform this device is part of")
     system = Param.System(Parent.any, "System this device is part of")
 
 class BasicPioDevice(PioDevice):
diff --git a/src/dev/Pci.py b/src/dev/Pci.py
index 9c2f27142..95cb3916f 100644
--- a/src/dev/Pci.py
+++ b/src/dev/Pci.py
@@ -33,6 +33,7 @@ from Device import BasicPioDevice, DmaDevice, PioDevice
 
 class PciConfigAll(PioDevice):
     type = 'PciConfigAll'
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
     bus = Param.UInt8(0x00, "PCI bus to act as config space for")
     size = Param.MemorySize32('16MB', "Size of config space")
@@ -41,6 +42,7 @@ class PciConfigAll(PioDevice):
 class PciDevice(DmaDevice):
     type = 'PciDevice'
     abstract = True
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     config = Port("PCI configuration space port")
     pci_bus = Param.Int("PCI bus")
     pci_dev = Param.Int("PCI device number")
diff --git a/src/dev/SConscript b/src/dev/SConscript
index 744e7b3c1..c041081b5 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -34,79 +34,77 @@ Import('*')
 if env['TARGET_ISA'] == 'no':
     Return()
 
-if env['FULL_SYSTEM']:
-    SimObject('BadDevice.py')
-    SimObject('CopyEngine.py')
-    SimObject('Device.py')
-    SimObject('DiskImage.py')
-    SimObject('Ethernet.py')
-    SimObject('Ide.py')
-    SimObject('Pci.py')
-    SimObject('Platform.py')
-    SimObject('SimpleDisk.py')
-    SimObject('Terminal.py')
-    SimObject('Uart.py')
+SimObject('BadDevice.py')
+SimObject('CopyEngine.py')
+SimObject('Device.py')
+SimObject('DiskImage.py')
+SimObject('Ethernet.py')
+SimObject('Ide.py')
+SimObject('Pci.py')
+SimObject('Platform.py')
+SimObject('SimpleDisk.py')
+SimObject('Terminal.py')
+SimObject('Uart.py')
 
-    Source('baddev.cc')
-    Source('copy_engine.cc')
-    Source('disk_image.cc')
-    Source('etherbus.cc')
-    Source('etherdevice.cc')
-    Source('etherdump.cc')
-    Source('etherint.cc')
-    Source('etherlink.cc')
-    Source('etherpkt.cc')
-    Source('ethertap.cc')
-    Source('i8254xGBe.cc')
-    Source('ide_ctrl.cc')
-    Source('ide_disk.cc')
-    Source('intel_8254_timer.cc')
-    Source('io_device.cc')
-    Source('isa_fake.cc')
-    Source('mc146818.cc')
-    Source('ns_gige.cc')
-    Source('pciconfigall.cc')
-    Source('pcidev.cc')
-    Source('pktfifo.cc')
-    Source('platform.cc')
-    Source('ps2.cc')
-    Source('simple_disk.cc')
-    Source('sinic.cc')
-    Source('terminal.cc')
-    Source('uart.cc')
-    Source('uart8250.cc')
+Source('baddev.cc')
+Source('copy_engine.cc')
+Source('disk_image.cc')
+Source('etherbus.cc')
+Source('etherdevice.cc')
+Source('etherdump.cc')
+Source('etherint.cc')
+Source('etherlink.cc')
+Source('etherpkt.cc')
+Source('ethertap.cc')
+Source('i8254xGBe.cc')
+Source('ide_ctrl.cc')
+Source('ide_disk.cc')
+Source('intel_8254_timer.cc')
+Source('io_device.cc')
+Source('isa_fake.cc')
+Source('mc146818.cc')
+Source('ns_gige.cc')
+Source('pciconfigall.cc')
+Source('pcidev.cc')
+Source('pktfifo.cc')
+Source('platform.cc')
+Source('ps2.cc')
+Source('simple_disk.cc')
+Source('sinic.cc')
+Source('terminal.cc')
+Source('uart.cc')
+Source('uart8250.cc')
 
-    DebugFlag('DiskImageRead')
-    DebugFlag('DiskImageWrite')
-    DebugFlag('DMA')
-    DebugFlag('DMACopyEngine')
-    DebugFlag('Ethernet')
-    DebugFlag('EthernetCksum')
-    DebugFlag('EthernetDMA')
-    DebugFlag('EthernetData')
-    DebugFlag('EthernetDesc')
-    DebugFlag('EthernetEEPROM')
-    DebugFlag('EthernetIntr')
-    DebugFlag('EthernetPIO')
-    DebugFlag('EthernetSM')
-    DebugFlag('IdeCtrl')
-    DebugFlag('IdeDisk')
-    DebugFlag('Intel8254Timer')
-    DebugFlag('IsaFake')
-    DebugFlag('MC146818')
-    DebugFlag('PCIDEV')
-    DebugFlag('PciConfigAll')
-    DebugFlag('SimpleDisk')
-    DebugFlag('SimpleDiskData')
-    DebugFlag('Terminal')
-    DebugFlag('TerminalVerbose')
-    DebugFlag('Uart')
-
-    CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
-    CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
-        'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
-        'EthernetCksum', 'EthernetEEPROM' ])
-    CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
-        'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
-    CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
+DebugFlag('DiskImageRead')
+DebugFlag('DiskImageWrite')
+DebugFlag('DMA')
+DebugFlag('DMACopyEngine')
+DebugFlag('Ethernet')
+DebugFlag('EthernetCksum')
+DebugFlag('EthernetDMA')
+DebugFlag('EthernetData')
+DebugFlag('EthernetDesc')
+DebugFlag('EthernetEEPROM')
+DebugFlag('EthernetIntr')
+DebugFlag('EthernetPIO')
+DebugFlag('EthernetSM')
+DebugFlag('IdeCtrl')
+DebugFlag('IdeDisk')
+DebugFlag('Intel8254Timer')
+DebugFlag('IsaFake')
+DebugFlag('MC146818')
+DebugFlag('PCIDEV')
+DebugFlag('PciConfigAll')
+DebugFlag('SimpleDisk')
+DebugFlag('SimpleDiskData')
+DebugFlag('Terminal')
+DebugFlag('TerminalVerbose')
+DebugFlag('Uart')
 
+CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+    'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+    'EthernetCksum', 'EthernetEEPROM' ])
+CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+    'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
diff --git a/src/dev/Uart.py b/src/dev/Uart.py
index 9254dc695..3dfc885eb 100644
--- a/src/dev/Uart.py
+++ b/src/dev/Uart.py
@@ -33,6 +33,7 @@ from Device import BasicPioDevice
 class Uart(BasicPioDevice):
     type = 'Uart'
     abstract = True
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     terminal = Param.Terminal(Parent.any, "The terminal")
 
 class Uart8250(Uart):
diff --git a/src/dev/alpha/AlphaBackdoor.py b/src/dev/alpha/AlphaBackdoor.py
index fa9627164..14894b863 100644
--- a/src/dev/alpha/AlphaBackdoor.py
+++ b/src/dev/alpha/AlphaBackdoor.py
@@ -26,6 +26,7 @@
 #
 # Authors: Nathan Binkert
 
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice
@@ -35,4 +36,5 @@ class AlphaBackdoor(BasicPioDevice):
     cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
     disk = Param.SimpleDisk("Simple Disk")
     terminal = Param.Terminal(Parent.any, "The console terminal")
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index 32baa6f48..9c8a5b4ce 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
+if env['TARGET_ISA'] == 'alpha':
     SimObject('AlphaBackdoor.py')
     SimObject('Tsunami.py')
 
diff --git a/src/dev/alpha/backdoor.cc b/src/dev/alpha/backdoor.cc
index 31ab62866..972778801 100644
--- a/src/dev/alpha/backdoor.cc
+++ b/src/dev/alpha/backdoor.cc
@@ -46,6 +46,9 @@
 #include "cpu/thread_context.hh"
 #include "debug/AlphaBackdoor.hh"
 #include "dev/alpha/backdoor.hh"
+#include "dev/alpha/tsunami.hh"
+#include "dev/alpha/tsunami_cchip.hh"
+#include "dev/alpha/tsunami_io.hh"
 #include "dev/platform.hh"
 #include "dev/simple_disk.hh"
 #include "dev/terminal.hh"
@@ -91,7 +94,10 @@ AlphaBackdoor::startup()
     alphaAccess->entryPoint = system->getKernelEntry();
     alphaAccess->mem_size = system->physmem->size();
     alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
-    alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
+    Tsunami *tsunami = dynamic_cast<Tsunami *>(params()->platform);
+    if (!tsunami)
+        fatal("Platform is not Tsunami.\n");
+    alphaAccess->intrClockFrequency = tsunami->io->frequency();
 }
 
 Tick
diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc
index 34aab6ed0..41a2fef0c 100644
--- a/src/dev/alpha/tsunami.cc
+++ b/src/dev/alpha/tsunami.cc
@@ -36,6 +36,7 @@
 #include <string>
 #include <vector>
 
+#include "arch/alpha/system.hh"
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "dev/alpha/tsunami.hh"
@@ -43,7 +44,6 @@
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/alpha/tsunami_pchip.hh"
 #include "dev/terminal.hh"
-#include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
@@ -52,17 +52,16 @@ using namespace TheISA;
 Tsunami::Tsunami(const Params *p)
     : Platform(p), system(p->system)
 {
-    // set the back pointer from the system to myself
-    system->platform = this;
-
     for (int i = 0; i < Tsunami::Max_CPUs; i++)
         intr_sum_type[i] = 0;
 }
 
-Tick
-Tsunami::intrFrequency()
+void
+Tsunami::init()
 {
-    return io->frequency();
+    AlphaSystem *alphaSystem = dynamic_cast<AlphaSystem *>(system);
+    assert(alphaSystem);
+    alphaSystem->setIntrFreq(io->frequency());
 }
 
 void
diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh
index 64aafe533..9380864b0 100644
--- a/src/dev/alpha/tsunami.hh
+++ b/src/dev/alpha/tsunami.hh
@@ -80,17 +80,13 @@ class Tsunami : public Platform
     int intr_sum_type[Tsunami::Max_CPUs];
     int ipi_pending[Tsunami::Max_CPUs];
 
+    void init();
+
   public:
     typedef TsunamiParams Params;
     Tsunami(const Params *p);
 
     /**
-     * Return the interrupting frequency to AlphaAccess
-     * @return frequency of RTC interrupts
-     */
-    virtual Tick intrFrequency();
-
-    /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
     virtual void postConsoleInt();
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 1dec9a40d..dc2219cd1 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -83,6 +83,7 @@ class RealViewCtrl(BasicPioDevice):
 
 class Gic(PioDevice):
     type = 'Gic'
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     dist_addr = Param.Addr(0x1f001000, "Address for distributor")
     cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
     dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index 07a3e14ae..deedcb49f 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -39,7 +39,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
+if env['TARGET_ISA'] == 'arm':
     SimObject('RealView.py')
 
     Source('a9scu.cc')
diff --git a/src/dev/arm/gic.cc b/src/dev/arm/gic.cc
index 4c45760b8..f686c2a13 100644
--- a/src/dev/arm/gic.cc
+++ b/src/dev/arm/gic.cc
@@ -45,6 +45,7 @@
 #include "debug/Checkpoint.hh"
 #include "debug/GIC.hh"
 #include "debug/IPI.hh"
+#include "debug/Interrupt.hh"
 #include "dev/arm/gic.hh"
 #include "dev/arm/realview.hh"
 #include "dev/terminal.hh"
@@ -52,9 +53,10 @@
 #include "mem/packet_access.hh"
 
 Gic::Gic(const Params *p)
-    : PioDevice(p),distAddr(p->dist_addr), cpuAddr(p->cpu_addr),
-      distPioDelay(p->dist_pio_delay), cpuPioDelay(p->cpu_pio_delay),
-      intLatency(p->int_latency), enabled(false), itLines(p->it_lines)
+    : PioDevice(p), platform(p->platform), distAddr(p->dist_addr),
+      cpuAddr(p->cpu_addr), distPioDelay(p->dist_pio_delay),
+      cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
+      enabled(false), itLines(p->it_lines)
 {
     itLinesLog2 = ceilLog2(itLines);
 
diff --git a/src/dev/arm/gic.hh b/src/dev/arm/gic.hh
index 6e3f12cdb..67d48cd86 100644
--- a/src/dev/arm/gic.hh
+++ b/src/dev/arm/gic.hh
@@ -124,6 +124,8 @@ class Gic : public PioDevice
         Bitfield<12,10> cpu_id;
     EndBitUnion(IAR)
 
+    Platform *platform;
+
     /** Distributor address GIC listens at */
     Addr distAddr;
 
diff --git a/src/dev/arm/realview.cc b/src/dev/arm/realview.cc
index 8cc318f89..b33624cc6 100644
--- a/src/dev/arm/realview.cc
+++ b/src/dev/arm/realview.cc
@@ -60,17 +60,7 @@ using namespace TheISA;
 
 RealView::RealView(const Params *p)
     : Platform(p), system(p->system)
-{
-    // set the back pointer from the system to myself
-    system->platform = this;
-}
-
-Tick
-RealView::intrFrequency()
-{
-    panic("Need implementation\n");
-    M5_DUMMY_RETURN
-}
+{}
 
 void
 RealView::postConsoleInt()
diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh
index 8ec9db5fc..70647d47c 100644
--- a/src/dev/arm/realview.hh
+++ b/src/dev/arm/realview.hh
@@ -82,12 +82,6 @@ class RealView : public Platform
     void setGic(Gic *_gic) { gic = _gic; }
 
     /**
-     * Return the interrupting frequency to AlphaAccess
-     * @return frequency of RTC interrupts
-     */
-    virtual Tick intrFrequency();
-
-    /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
     virtual void postConsoleInt();
diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc
index 1b4d04afc..9fb88d876 100644
--- a/src/dev/baddev.cc
+++ b/src/dev/baddev.cc
@@ -39,7 +39,6 @@
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "dev/baddev.hh"
-#include "dev/platform.hh"
 #include "mem/port.hh"
 #include "params/BadDevice.hh"
 #include "sim/system.hh"
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index 6cb7bbed7..840343dce 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -55,7 +55,7 @@ PioPort::getAddrRanges()
 
 
 PioDevice::PioDevice(const Params *p)
-    : MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
+    : MemObject(p), sys(p->system), pioPort(NULL)
 {}
 
 PioDevice::~PioDevice()
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 45fd385b9..ea2364f33 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -42,7 +42,6 @@
 #include "sim/sim_object.hh"
 
 class Event;
-class Platform;
 class PioDevice;
 class DmaDevice;
 class System;
@@ -186,11 +185,6 @@ class DmaPort : public Port
 class PioDevice : public MemObject
 {
   protected:
-
-    /** The platform we are in. This is used to decide what type of memory
-     * transaction we should perform. */
-    Platform *platform;
-
     System *sys;
 
     /** The pioPort that handles the requests for us and provides us requests
diff --git a/src/dev/mips/SConscript b/src/dev/mips/SConscript
index 369dbfed2..801b1916d 100755
--- a/src/dev/mips/SConscript
+++ b/src/dev/mips/SConscript
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
+if env['TARGET_ISA'] == 'mips':
     SimObject('Malta.py')
 
     DebugFlag('Malta')
diff --git a/src/dev/mips/malta.cc b/src/dev/mips/malta.cc
index bcf970745..277633c6b 100755
--- a/src/dev/mips/malta.cc
+++ b/src/dev/mips/malta.cc
@@ -39,6 +39,7 @@
 
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/malta_io.hh"
@@ -53,19 +54,10 @@ using namespace TheISA;
 Malta::Malta(const Params *p)
     : Platform(p), system(p->system)
 {
-    // set the back pointer from the system to myself
-    system->platform = this;
-
     for (int i = 0; i < Malta::Max_CPUs; i++)
         intr_sum_type[i] = 0;
 }
 
-Tick
-Malta::intrFrequency()
-{
-    return io->frequency();
-}
-
 void
 Malta::postConsoleInt()
 {
diff --git a/src/dev/mips/malta.hh b/src/dev/mips/malta.hh
index 69ae004b3..e612fb295 100755
--- a/src/dev/mips/malta.hh
+++ b/src/dev/mips/malta.hh
@@ -92,12 +92,6 @@ class Malta : public Platform
     Malta(const Params *p);
 
     /**
-     * Return the interrupting frequency to MipsAccess
-     * @return frequency of RTC interrupts
-     */
-    virtual Tick intrFrequency();
-
-    /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
     virtual void postConsoleInt();
diff --git a/src/dev/mips/malta_cchip.cc b/src/dev/mips/malta_cchip.cc
index b2d5069c5..25062e422 100755
--- a/src/dev/mips/malta_cchip.cc
+++ b/src/dev/mips/malta_cchip.cc
@@ -37,11 +37,11 @@
 #include <string>
 #include <vector>
 
-#include "arch/mips/mips_core_specific.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/maltareg.h"
diff --git a/src/dev/mips/malta_io.cc b/src/dev/mips/malta_io.cc
index bd9288487..1ae5442bf 100755
--- a/src/dev/mips/malta_io.cc
+++ b/src/dev/mips/malta_io.cc
@@ -43,6 +43,7 @@
 #include "base/time.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/malta_io.hh"
diff --git a/src/dev/mips/malta_pchip.cc b/src/dev/mips/malta_pchip.cc
index 7832a31bd..dd1993cc6 100755
--- a/src/dev/mips/malta_pchip.cc
+++ b/src/dev/mips/malta_pchip.cc
@@ -39,6 +39,7 @@
 
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_pchip.hh"
 #include "dev/mips/maltareg.h"
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 534cbb173..42c803553 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -83,7 +83,7 @@ PciDev::PciConfigPort::getAddrRanges()
 
 
 PciDev::PciDev(const Params *p)
-    : DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency),
+    : DmaDevice(p), platform(p->platform), pioDelay(p->pio_latency),
       configDelay(p->config_latency), configPort(NULL)
 {
     config.vendor = htole(p->VendorID);
@@ -143,7 +143,7 @@ PciDev::PciDev(const Params *p)
         }
     }
 
-    plat->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
+    platform->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
             letoh(config.interruptLine));
 }
 
diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh
index 4c3ecc594..c0c3df0a6 100644
--- a/src/dev/pcidev.hh
+++ b/src/dev/pcidev.hh
@@ -148,7 +148,7 @@ class PciDev : public DmaDevice
     }
 
   protected:
-    Platform *plat;
+    Platform *platform;
     Tick pioDelay;
     Tick configDelay;
     PciConfigPort *configPort;
@@ -172,15 +172,15 @@ class PciDev : public DmaDevice
 
   public:
     Addr pciToDma(Addr pciAddr) const
-    { return plat->pciToDma(pciAddr); }
+    { return platform->pciToDma(pciAddr); }
 
     void
     intrPost()
-    { plat->postPciInt(letoh(config.interruptLine)); }
+    { platform->postPciInt(letoh(config.interruptLine)); }
 
     void
     intrClear()
-    { plat->clearPciInt(letoh(config.interruptLine)); }
+    { platform->clearPciInt(letoh(config.interruptLine)); }
 
     uint8_t
     interruptLine()
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index a3f239865..b3d1bec9f 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -64,7 +64,6 @@ class Platform : public SimObject
     virtual ~Platform();
     virtual void postConsoleInt() = 0;
     virtual void clearConsoleInt() = 0;
-    virtual Tick intrFrequency() = 0;
     virtual void postPciInt(int line);
     virtual void clearPciInt(int line);
     virtual Addr pciToDma(Addr pciAddr) const;
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index 772aa4864..e82e5ee05 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
+if env['TARGET_ISA'] == 'sparc':
     SimObject('T1000.py')
 
     Source('dtod.cc')
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index cbf390737..901304251 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -46,6 +46,7 @@ class DumbTOD(BasicPioDevice):
 
 class Iob(PioDevice):
     type = 'Iob'
+    platform = Param.Platform(Parent.any, "Platform this device is part of.")
     pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
 
 
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index e7947dcdf..757c50a24 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -42,6 +42,7 @@
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
+#include "cpu/thread_context.hh"
 #include "debug/Iob.hh"
 #include "dev/sparc/iob.hh"
 #include "dev/platform.hh"
@@ -61,9 +62,6 @@ Iob::Iob(const Params *p)
 
     pioDelay = p->pio_latency;
 
-    // Get the interrupt controller from the platform
-    ic = platform->intrctrl;
-
     for (int x = 0; x < NumDeviceIds; ++x) {
         intMan[x].cpu = 0;
         intMan[x].vector = 0;
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index c00d942c9..12f43ab23 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -48,17 +48,7 @@ using namespace TheISA;
 
 T1000::T1000(const Params *p)
     : Platform(p), system(p->system)
-{
-    // set the back pointer from the system to myself
-    system->platform = this;
-}
-
-Tick
-T1000::intrFrequency()
-{
-    panic("Need implementation\n");
-    M5_DUMMY_RETURN
-}
+{}
 
 void
 T1000::postConsoleInt()
diff --git a/src/dev/sparc/t1000.hh b/src/dev/sparc/t1000.hh
index 01ff3d319..6440f317b 100644
--- a/src/dev/sparc/t1000.hh
+++ b/src/dev/sparc/t1000.hh
@@ -60,12 +60,6 @@ class T1000 : public Platform
     T1000(const Params *p);
 
     /**
-     * Return the interrupting frequency to AlphaAccess
-     * @return frequency of RTC interrupts
-     */
-    virtual Tick intrFrequency();
-
-    /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
     virtual void postConsoleInt();
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index eeb68cf44..038e4824b 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -30,7 +30,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+if env['TARGET_ISA'] == 'x86':
     SimObject('Pc.py')
     Source('pc.cc')
 
diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc
index 584090a9e..d9c07f5ae 100644
--- a/src/dev/x86/i82094aa.cc
+++ b/src/dev/x86/i82094aa.cc
@@ -30,6 +30,7 @@
 
 #include "arch/x86/interrupts.hh"
 #include "arch/x86/intmessage.hh"
+#include "cpu/base.hh"
 #include "debug/I82094AA.hh"
 #include "dev/x86/i82094aa.hh"
 #include "dev/x86/i8259.hh"
@@ -196,13 +197,11 @@ X86ISA::I82094AA::signalInterrupt(int line)
             }
         } else {
             for (int i = 0; i < numContexts; i++) {
-                std::map<int, Interrupts *>::iterator localApicIt =
-                    localApics.find(i);
-                assert(localApicIt != localApics.end());
-                Interrupts *localApic = localApicIt->second;
+                Interrupts *localApic = sys->getThreadContext(i)->
+                    getCpuPtr()->getInterruptController();
                 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
                         message.destination) {
-                    apics.push_back(localApicIt->first);
+                    apics.push_back(localApic->getInitialApicId());
                 }
             }
             if (message.deliveryMode == DeliveryMode::LowestPriority &&
@@ -245,13 +244,6 @@ X86ISA::I82094AA::lowerInterruptPin(int number)
 }
 
 void
-X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic)
-{
-    assert(localApic);
-    localApics[initialId] = localApic;
-}
-
-void
 X86ISA::I82094AA::serialize(std::ostream &os)
 {
     uint64_t* redirTableArray = (uint64_t*)redirTable;
diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh
index 0bcf8973d..dfef059c3 100644
--- a/src/dev/x86/i82094aa.hh
+++ b/src/dev/x86/i82094aa.hh
@@ -70,8 +70,6 @@ class I82094AA : public PioDevice, public IntDev
 
     I8259 * extIntPic;
 
-    std::map<int, Interrupts *> localApics;
-
     uint8_t regSel;
     uint8_t initialApicId;
     uint8_t id;
@@ -133,7 +131,6 @@ class I82094AA : public PioDevice, public IntDev
     void signalInterrupt(int line);
     void raiseInterruptPin(int number);
     void lowerInterruptPin(int number);
-    void registerLocalApic(int id, Interrupts *localApic);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 7912a45e1..dd8e34d9e 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -55,8 +55,6 @@ Pc::Pc(const Params *p)
     : Platform(p), system(p->system)
 {
     southBridge = NULL;
-    // set the back pointer from the system to myself
-    system->platform = this;
 }
 
 void
@@ -117,13 +115,6 @@ Pc::init()
     southBridge->pic2->maskAll();
 }
 
-Tick
-Pc::intrFrequency()
-{
-    panic("Need implementation for intrFrequency\n");
-    M5_DUMMY_RETURN
-}
-
 void
 Pc::postConsoleInt()
 {
diff --git a/src/dev/x86/pc.hh b/src/dev/x86/pc.hh
index 427cc4165..c999440d2 100644
--- a/src/dev/x86/pc.hh
+++ b/src/dev/x86/pc.hh
@@ -62,12 +62,6 @@ class Pc : public Platform
     Pc(const Params *p);
 
     /**
-     * Return the interrupting frequency to AlphaAccess
-     * @return frequency of RTC interrupts
-     */
-    virtual Tick intrFrequency();
-
-    /**
      * Cause the cpu to post a serial interrupt to the CPU.
      */
     virtual void postConsoleInt();
diff --git a/src/kern/SConscript b/src/kern/SConscript
index 93394829b..38734e650 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -33,23 +33,21 @@ Import('*')
 if env['TARGET_ISA'] == 'no':
     Return()
 
-if env['FULL_SYSTEM']:
-    Source('kernel_stats.cc')
-    Source('system_events.cc')
+Source('kernel_stats.cc')
+Source('linux/events.cc')
+Source('linux/linux.cc')
+Source('linux/linux_syscalls.cc')
+Source('linux/printk.cc')
+Source('operatingsystem.cc')
+Source('system_events.cc')
 
-    DebugFlag('DebugPrintf')
-    DebugFlag('Printf')
+DebugFlag('DebugPrintf')
+DebugFlag('Printf')
 
-    Source('linux/events.cc')
-    Source('linux/linux_syscalls.cc')
-    Source('linux/printk.cc')
-    
-    if env['TARGET_ISA'] == 'alpha':
-        Source('tru64/dump_mbuf.cc')
-        Source('tru64/printf.cc')
-        Source('tru64/tru64_events.cc')
-        Source('tru64/tru64_syscalls.cc')
-        DebugFlag('BADADDR')
-else:
-    Source('linux/linux.cc')
-    Source('operatingsystem.cc')
+if env['TARGET_ISA'] == 'alpha':
+    Source('tru64/dump_mbuf.cc')
+    Source('tru64/printf.cc')
+    Source('tru64/tru64_events.cc')
+    Source('tru64/tru64_syscalls.cc')
+
+    DebugFlag('BADADDR')
diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc
index 09c1a6760..96e219bd4 100644
--- a/src/kern/kernel_stats.cc
+++ b/src/kern/kernel_stats.cc
@@ -33,8 +33,10 @@
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "kern/tru64/tru64_syscalls.hh"
 #include "kern/kernel_stats.hh"
+#if THE_ISA == ALPHA_ISA
+#include "kern/tru64/tru64_syscalls.hh"
+#endif
 #include "sim/system.hh"
 
 using namespace std;
@@ -90,13 +92,14 @@ Statistics::regStats(const string &_name)
         ;
 
     _iplUsed = _iplGood / _iplCount;
-
+#if THE_ISA == ALPHA_ISA
     _syscall
         .init(SystemCalls<Tru64>::Number)
         .name(name() + ".syscall")
         .desc("number of syscalls executed")
         .flags(total | pdf | nozero | nonan)
         ;
+#endif
 
     //@todo This needs to get the names of syscalls from an appropriate place.
 #if 0
diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh
index e4ca67fcb..d5abde83f 100644
--- a/src/kern/kernel_stats.hh
+++ b/src/kern/kernel_stats.hh
@@ -61,7 +61,9 @@ class Statistics : public Serializable
     Stats::Vector _iplTicks;
     Stats::Formula _iplUsed;
 
+#if THE_ISA == ALPHA_ISA
     Stats::Vector _syscall;
+#endif
 //    Stats::Vector _faults;
 
   private:
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index 7fe107139..30ebdbb4a 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -32,13 +32,6 @@
 #define __LINUX_HH__
 
 #include "base/types.hh"
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
-
-class Linux {};
-
-#else //!FULL_SYSTEM
 
 #include <string>
 
@@ -180,7 +173,4 @@ class Linux : public OperatingSystem
 
 };  // class Linux
 
-
-#endif // FULL_SYSTEM
-
 #endif // __LINUX_HH__
diff --git a/src/kern/operatingsystem.hh b/src/kern/operatingsystem.hh
index 6574e3c6b..fd5899cf8 100644
--- a/src/kern/operatingsystem.hh
+++ b/src/kern/operatingsystem.hh
@@ -32,13 +32,7 @@
 #define __KERN_OPERATINGSYSTEM_HH__
 
 #include "base/types.hh"
-#include "config/full_system.hh"
 
-#if FULL_SYSTEM
-
-class OperatingSystem {};
-
-#else //!FULL_SYSTEM
 #include <string>
 
 class LiveProcess;
@@ -128,7 +122,4 @@ class OperatingSystem {
 
 };  // class OperatingSystem
 
-
-#endif // FULL_SYSTEM
-
 #endif // __OPERATINGSYSTEM_HH__
diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index 00eee994b..da6ce84f7 100644
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -32,14 +32,6 @@
 #define __SOLARIS_HH__
 
 #include "base/types.hh"
-#include "config/full_system.hh"
-
-#if FULL_SYSTEM
-
-class Solaris {};
-
-#else //!FULL_SYSTEM
-
 #include "kern/operatingsystem.hh"
 
 class TranslatingPort;
@@ -126,7 +118,4 @@ class Solaris : public OperatingSystem
 
 };  // class Solaris
 
-
-#endif // FULL_SYSTEM
-
 #endif // __SOLARIS_HH__
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 776607c85..3b9bbd2bf 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -32,16 +32,9 @@
 #ifndef __TRU64_HH__
 #define __TRU64_HH__
 
-#include "config/full_system.hh"
 #include "kern/operatingsystem.hh"
 #include "sim/byteswap.hh"
 
-#if FULL_SYSTEM
-
-class Tru64 {};
-
-#else //!FULL_SYSTEM
-
 #include <sys/stat.h>
 #include <sys/types.h>
 #if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__)
@@ -1226,6 +1219,4 @@ class Tru64_PreF64 : public Tru64
     }
 };
 
-#endif // FULL_SYSTEM
-
 #endif // __TRU64_HH__
diff --git a/src/mem/SConscript b/src/mem/SConscript
index dafc8c4a2..09cc93c77 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -37,21 +37,18 @@ SimObject('MemObject.py')
 Source('bridge.cc')
 Source('bus.cc')
 Source('mem_object.cc')
+Source('mport.cc')
 Source('packet.cc')
 Source('port.cc')
 Source('tport.cc')
-Source('mport.cc')
+Source('fs_translating_port_proxy.cc')
+Source('se_translating_port_proxy.cc')
 
 if env['TARGET_ISA'] != 'no':
     SimObject('PhysicalMemory.py')
     Source('dram.cc')
-    Source('physical.cc')
-
-if env['FULL_SYSTEM']:
-    Source('fs_translating_port_proxy.cc')
-elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
-    Source('se_translating_port_proxy.cc')
+    Source('physical.cc')
 
 DebugFlag('Bus')
 DebugFlag('BusAddrRanges')
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 278329152..2b7fa4b9f 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -38,6 +38,7 @@
 #include "debug/Cache.hh"
 #include "mem/cache/base.hh"
 #include "mem/cache/mshr.hh"
+#include "sim/full_system.hh"
 
 using namespace std;
 
@@ -149,11 +150,7 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         hits[access_idx]
-#if FULL_SYSTEM
-            .init(_numCpus + 1)
-#else
-            .init(_numCpus)
-#endif
+            .init(FullSystem ? (_numCpus + 1) : _numCpus)
             .name(name() + "." + cstr + "_hits")
             .desc("number of " + cstr + " hits")
             .flags(total | nozero | nonan)
@@ -190,11 +187,7 @@ BaseCache::regStats()
         const string &cstr = cmd.toString();
 
         misses[access_idx]
-#if FULL_SYSTEM
-            .init(_numCpus + 1)
-#else
-            .init(_numCpus)
-#endif
+            .init(FullSystem ? (_numCpus + 1) : _numCpus)
             .name(name() + "." + cstr + "_misses")
             .desc("number of " + cstr + " misses")
             .flags(total | nozero | nonan)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index e6a5c284f..fded6fca6 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -47,7 +47,6 @@
 #include "base/statistics.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "debug/Cache.hh"
 #include "debug/CachePort.hh"
 #include "mem/cache/mshr_queue.hh"
@@ -57,6 +56,7 @@
 #include "mem/tport.hh"
 #include "params/BaseCache.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_exit.hh"
 
 class MSHR;
@@ -505,12 +505,10 @@ class BaseCache : public MemObject
              * available, meanwhile writeback hit/miss stats are not used
              * in any aggregate hit/miss calculations, so just lump them all
              * in bucket 0 */
-#if FULL_SYSTEM
-        } else if (id == -1) {
+        } else if (FullSystem && id == -1) {
             // Device accesses have id -1
             // lump device accesses into their own bucket
             misses[pkt->cmdToIndex()][_numCpus]++;
-#endif
         } else {
             misses[pkt->cmdToIndex()][id % _numCpus]++;
         }
@@ -533,12 +531,10 @@ class BaseCache : public MemObject
         if (pkt->cmd == MemCmd::Writeback) {
             assert(id == -1);
             hits[pkt->cmdToIndex()][0]++;
-#if FULL_SYSTEM
-        } else if (id == -1) {
+        } else if (FullSystem && id == -1) {
             // Device accesses have id -1
             // lump device accesses into their own bucket
             hits[pkt->cmdToIndex()][_numCpus]++;
-#endif
         } else {
             /* the % is necessary in case there are switch cpus */
             hits[pkt->cmdToIndex()][id % _numCpus]++;
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index ce3448c4c..f47e73c74 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -217,12 +217,13 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
 {
     int i = 0, count;
     paramIn(cp, section, "ptable.size", count);
-    Addr vaddr;
-    TheISA::TlbEntry *entry;
 
     pTable.clear();
 
-    while(i < count) {
+    while (i < count) {
+        TheISA::TlbEntry *entry;
+        Addr vaddr;
+
         paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
         entry = new TheISA::TlbEntry();
         entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index a63f6e619..09ed8b292 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -59,7 +59,6 @@
 #include "base/misc.hh"
 #include "base/random.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "debug/LLSC.hh"
 #include "debug/MemoryAccess.hh"
diff --git a/src/mem/se_translating_port_proxy.cc b/src/mem/se_translating_port_proxy.cc
index 027930287..0f7ecb491 100644
--- a/src/mem/se_translating_port_proxy.cc
+++ b/src/mem/se_translating_port_proxy.cc
@@ -44,6 +44,7 @@
 
 #include <string>
 
+#include "arch/isa_traits.hh"
 #include "base/chunk_generator.hh"
 #include "config/the_isa.hh"
 #include "mem/page_table.hh"
@@ -64,10 +65,10 @@ SETranslatingPortProxy::~SETranslatingPortProxy()
 bool
 SETranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size)
 {
-    Addr paddr;
     int prevSize = 0;
 
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+        Addr paddr;
 
         if (!pTable->translate(gen.addr(),paddr))
             return false;
@@ -90,11 +91,10 @@ SETranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size)
 bool
 SETranslatingPortProxy::tryWriteBlob(Addr addr, uint8_t *p, int size)
 {
-
-    Addr paddr;
     int prevSize = 0;
 
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+        Addr paddr;
 
         if (!pTable->translate(gen.addr(), paddr)) {
             if (allocating == Always) {
@@ -129,9 +129,8 @@ SETranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size)
 bool
 SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size)
 {
-    Addr paddr;
-
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+        Addr paddr;
 
         if (!pTable->translate(gen.addr(), paddr)) {
             if (allocating == Always) {
@@ -160,14 +159,15 @@ SETranslatingPortProxy::memsetBlob(Addr addr, uint8_t val, int size)
 bool
 SETranslatingPortProxy::tryWriteString(Addr addr, const char *str)
 {
-    Addr paddr,vaddr;
     uint8_t c;
 
-    vaddr = addr;
+    Addr vaddr = addr;
 
     do {
         c = *str++;
-        if (!pTable->translate(vaddr++,paddr))
+        Addr paddr;
+
+        if (!pTable->translate(vaddr++, paddr))
             return false;
 
         PortProxy::writeBlob(paddr, &c, 1);
@@ -186,13 +186,14 @@ SETranslatingPortProxy::writeString(Addr addr, const char *str)
 bool
 SETranslatingPortProxy::tryReadString(std::string &str, Addr addr)
 {
-    Addr paddr,vaddr;
     uint8_t c;
 
-    vaddr = addr;
+    Addr vaddr = addr;
 
     do {
-        if (!pTable->translate(vaddr++,paddr))
+        Addr paddr;
+
+        if (!pTable->translate(vaddr++, paddr))
             return false;
 
         PortProxy::readBlob(paddr, &c, 1);
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
index c8555cd31..3478310b1 100644
--- a/src/python/swig/pyobject.cc
+++ b/src/python/swig/pyobject.cc
@@ -34,16 +34,13 @@
 
 #include "base/inifile.hh"
 #include "base/output.hh"
-#include "config/full_system.hh"
-#include "mem/mem_object.hh"
-#include "mem/port.hh"
-#include "sim/sim_object.hh"
-
-#if FULL_SYSTEM
 #include "dev/etherdevice.hh"
 #include "dev/etherint.hh"
 #include "dev/etherobject.hh"
-#endif
+#include "mem/mem_object.hh"
+#include "mem/port.hh"
+#include "sim/full_system.hh"
+#include "sim/sim_object.hh"
 
 using namespace std;
 
@@ -65,8 +62,6 @@ lookupPort(SimObject *so, const std::string &name, int i)
     return p;
 }
 
-#if FULL_SYSTEM
-
 EtherInt *
 lookupEthPort(SimObject *so, const std::string &name, int i)
 {
@@ -84,7 +79,6 @@ lookupEthPort(SimObject *so, const std::string &name, int i)
         p = ed->getEthPort(name, i);
     return p;
 }
-#endif
 
 /**
  * Connect the described MemObject ports.  Called from Python via SWIG.
@@ -94,28 +88,27 @@ int
 connectPorts(SimObject *o1, const std::string &name1, int i1,
              SimObject *o2, const std::string &name2, int i2)
 {
-#if FULL_SYSTEM
-    EtherObject *eo1, *eo2;
-    EtherDevice *ed1, *ed2;
-    eo1 = dynamic_cast<EtherObject*>(o1);
-    ed1 = dynamic_cast<EtherDevice*>(o1);
-
-    eo2 = dynamic_cast<EtherObject*>(o2);
-    ed2 = dynamic_cast<EtherDevice*>(o2);
+    if (FullSystem) {
+        EtherObject *eo1, *eo2;
+        EtherDevice *ed1, *ed2;
+        eo1 = dynamic_cast<EtherObject*>(o1);
+        ed1 = dynamic_cast<EtherDevice*>(o1);
+        eo2 = dynamic_cast<EtherObject*>(o2);
+        ed2 = dynamic_cast<EtherDevice*>(o2);
 
-    if ((eo1 || ed1) && (eo2 || ed2)) {
-        EtherInt *p1 = lookupEthPort(o1, name1, i1);
-        EtherInt *p2 = lookupEthPort(o2, name2, i2);
+        if ((eo1 || ed1) && (eo2 || ed2)) {
+            EtherInt *p1 = lookupEthPort(o1, name1, i1);
+            EtherInt *p2 = lookupEthPort(o2, name2, i2);
 
-        if (p1 != NULL &&  p2 != NULL) {
+            if (p1 != NULL &&  p2 != NULL) {
 
-            p1->setPeer(p2);
-            p2->setPeer(p1);
+                p1->setPeer(p2);
+                p2->setPeer(p1);
 
-            return 1;
+                return 1;
+            }
         }
     }
-#endif
     Port *p1 = lookupPort(o1, name1, i1);
     Port *p2 = lookupPort(o2, name2, i2);
 
diff --git a/src/sim/Root.py b/src/sim/Root.py
index e15de1554..daa0a903f 100644
--- a/src/sim/Root.py
+++ b/src/sim/Root.py
@@ -28,6 +28,7 @@
 # Authors: Nathan Binkert
 
 from m5.SimObject import SimObject
+from m5.defines import buildEnv
 from m5.params import *
 from m5.util import fatal
 
@@ -58,6 +59,8 @@ class Root(SimObject):
 
     type = 'Root'
 
+    full_system = Param.Bool("if this is a full system simulation")
+
     # Time syncing prevents the simulation from running faster than real time.
     time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
     time_sync_period = Param.Clock("100ms", "how often to sync with real time")
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 041c3ac10..25b965d59 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -34,6 +34,7 @@ SimObject('BaseTLB.py')
 SimObject('Root.py')
 SimObject('InstTracer.py')
 
+Source('arguments.cc')
 Source('async.cc')
 Source('core.cc')
 Source('debug.cc')
@@ -46,21 +47,18 @@ Source('sim_events.cc')
 Source('sim_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
+Source('syscall_emul.cc')
 
 if env['TARGET_ISA'] != 'no':
+    SimObject('Process.py')
     SimObject('System.py')
     Source('faults.cc')
+    Source('process.cc')
     Source('pseudo_inst.cc')
     Source('system.cc')
 
-if env['FULL_SYSTEM']:
-    Source('arguments.cc')
-elif env['TARGET_ISA'] != 'no':
+if env['TARGET_ISA'] != 'no':
     Source('tlb.cc')
-    SimObject('Process.py')
-
-    Source('process.cc')
-    Source('syscall_emul.cc')
 
 DebugFlag('Checkpoint')
 DebugFlag('Config')
diff --git a/src/sim/System.py b/src/sim/System.py
index d34a043c1..73124ecb9 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -70,14 +70,10 @@ class System(MemObject):
     work_cpus_ckpt_count = Param.Counter(0,
         "create checkpoint when active cpu count value is reached")
 
-    if buildEnv['FULL_SYSTEM']:
-        abstract = True
-        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
-                                             "boot processor frequency")
-        init_param = Param.UInt64(0, "numerical value to pass into simulator")
-        boot_osflags = Param.String("a", "boot flags to pass to the kernel")
-        kernel = Param.String("", "file that contains the kernel code")
-        readfile = Param.String("", "file to read startup script from")
-        symbolfile = Param.String("", "file to get the symbols from")
-        load_addr_mask = Param.UInt64(0xffffffffff,
-                "Address to mask loading binaries with");
+    init_param = Param.UInt64(0, "numerical value to pass into simulator")
+    boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+    kernel = Param.String("", "file that contains the kernel code")
+    readfile = Param.String("", "file to read startup script from")
+    symbolfile = Param.String("", "file to get the symbols from")
+    load_addr_mask = Param.UInt64(0xffffffffff,
+            "Address to mask loading binaries with");
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 6403953db..c409aa95b 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -36,11 +36,12 @@
 #include "debug/Fault.hh"
 #include "mem/page_table.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
 void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
-    if (FULL_SYSTEM) {
+    if (FullSystem) {
         DPRINTF(Fault, "Fault %s at PC: %s\n", name(), tc->pcState());
         assert(!tc->misspeculating());
     } else {
@@ -61,11 +62,10 @@ void ReExec::invoke(ThreadContext *tc, StaticInstPtr inst)
 void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     bool handled = false;
-#if !FULL_SYSTEM
-    Process *p = tc->getProcessPtr();
-
-    handled = p->fixupStackFault(vaddr);
-#endif
+    if (!FullSystem) {
+        Process *p = tc->getProcessPtr();
+        handled = p->fixupStackFault(vaddr);
+    }
     if (!handled)
         panic("Page table fault when accessing virtual address %#x\n", vaddr);
 
diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index 0b2d3be10..4cdb24aee 100644
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -34,7 +34,6 @@
 
 #include "base/refcnt.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/fault_fwd.hh"
 #include "sim/stats.hh"
diff --git a/src/sim/full_system.hh b/src/sim/full_system.hh
index 911648f3a..e67fc11a9 100644
--- a/src/sim/full_system.hh
+++ b/src/sim/full_system.hh
@@ -31,8 +31,6 @@
 #ifndef __SIM_FULL_SYSTEM_HH__
 #define __SIM_FULL_SYSTEM_HH__
 
-#include "config/full_system.hh"
-
-static const bool FullSystem = FULL_SYSTEM;
+extern bool FullSystem;
 
 #endif // __SIM_FULL_SYSTEM_HH__
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 239b4a3c5..45362fe1b 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -40,7 +40,6 @@
 #include "base/loader/symtab.hh"
 #include "base/intmath.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
@@ -77,15 +76,6 @@
 using namespace std;
 using namespace TheISA;
 
-//
-// The purpose of this code is to fake the loader & syscall mechanism
-// when there's no OS: thus there's no resone to use it in FULL_SYSTEM
-// mode when we do have an OS
-//
-#if FULL_SYSTEM
-#error "process.cc not compatible with FULL_SYSTEM"
-#endif
-
 // current number of allocated processes
 int num_processes = 0;
 
@@ -724,7 +714,6 @@ LiveProcess::create(LiveProcessParams * params)
 #error "THE_ISA not set"
 #endif
 
-
     if (process == NULL)
         fatal("Unknown error creating process object.");
     return process;
diff --git a/src/sim/process.hh b/src/sim/process.hh
index f78ab595c..3896492b7 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -32,15 +32,6 @@
 #ifndef __PROCESS_HH__
 #define __PROCESS_HH__
 
-//
-// The purpose of this code is to fake the loader & syscall mechanism
-// when there's no OS: thus there's no reason to use it in FULL_SYSTEM
-// mode when we do have an OS.
-//
-#include "config/full_system.hh"
-
-#if !FULL_SYSTEM
-
 #include <string>
 #include <vector>
 
@@ -319,6 +310,4 @@ class LiveProcess : public Process
 };
 
 
-#endif // !FULL_SYSTEM
-
 #endif // __PROCESS_HH__
diff --git a/src/sim/process_impl.hh b/src/sim/process_impl.hh
index b1b14d0f3..401e16f52 100644
--- a/src/sim/process_impl.hh
+++ b/src/sim/process_impl.hh
@@ -32,15 +32,6 @@
 #ifndef __SIM_PROCESS_IMPL_HH__
 #define __SIM_PROCESS_IMPL_HH__
 
-//
-// The purpose of this code is to fake the loader & syscall mechanism
-// when there's no OS: thus there's no reason to use it in FULL_SYSTEM
-// mode when we do have an OS.
-//
-#include "config/full_system.hh"
-
-#if !FULL_SYSTEM
-
 #include <string>
 #include <vector>
 
@@ -69,7 +60,4 @@ copyStringArray(std::vector<std::string> &strings,
     memProxy->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType));
 }
 
-
-#endif // !FULL_SYSTEM
-
 #endif
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 647420ca1..b72fdca4a 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -48,9 +48,9 @@
 #include <fstream>
 #include <string>
 
+#include "arch/kernel_stats.hh"
 #include "arch/vtophys.hh"
 #include "base/debug.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/base.hh"
 #include "cpu/quiesce_event.hh"
@@ -59,6 +59,7 @@
 #include "debug/Quiesce.hh"
 #include "debug/WorkItems.hh"
 #include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/pseudo_inst.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_events.hh"
@@ -66,11 +67,7 @@
 #include "sim/stat_control.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
-
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
 #include "sim/vptr.hh"
-#endif
 
 using namespace std;
 
@@ -79,11 +76,18 @@ using namespace TheISA;
 
 namespace PseudoInst {
 
-#if FULL_SYSTEM
+static inline void
+panicFsOnlyPseudoInst(const char *name)
+{
+    panic("Pseudo inst \"%s\" is only available in Full System mode.");
+}
 
 void
 arm(ThreadContext *tc)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("arm");
+
     if (tc->getKernelStats())
         tc->getKernelStats()->arm();
 }
@@ -91,6 +95,9 @@ arm(ThreadContext *tc)
 void
 quiesce(ThreadContext *tc)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("quiesce");
+
     if (!tc->getCpuPtr()->params()->do_quiesce)
         return;
 
@@ -104,6 +111,9 @@ quiesce(ThreadContext *tc)
 void
 quiesceSkip(ThreadContext *tc)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("quiesceSkip");
+
     BaseCPU *cpu = tc->getCpuPtr();
 
     if (!cpu->params()->do_quiesce)
@@ -126,6 +136,9 @@ quiesceSkip(ThreadContext *tc)
 void
 quiesceNs(ThreadContext *tc, uint64_t ns)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("quiesceNs");
+
     BaseCPU *cpu = tc->getCpuPtr();
 
     if (!cpu->params()->do_quiesce || ns == 0)
@@ -148,6 +161,9 @@ quiesceNs(ThreadContext *tc, uint64_t ns)
 void
 quiesceCycles(ThreadContext *tc, uint64_t cycles)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("quiesceCycles");
+
     BaseCPU *cpu = tc->getCpuPtr();
 
     if (!cpu->params()->do_quiesce || cycles == 0)
@@ -170,12 +186,15 @@ quiesceCycles(ThreadContext *tc, uint64_t cycles)
 uint64_t
 quiesceTime(ThreadContext *tc)
 {
+    if (!FullSystem) {
+        panicFsOnlyPseudoInst("quiesceTime");
+        return 0;
+    }
+
     return (tc->readLastActivate() - tc->readLastSuspend()) /
         SimClock::Int::ns;
 }
 
-#endif
-
 uint64_t
 rpns(ThreadContext *tc)
 {
@@ -198,11 +217,12 @@ m5exit(ThreadContext *tc, Tick delay)
     exitSimLoop("m5_exit instruction encountered", 0, when);
 }
 
-#if FULL_SYSTEM
-
 void
 loadsymbol(ThreadContext *tc)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("loadsymbol");
+
     const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
     if (filename.empty()) {
         return;
@@ -251,6 +271,9 @@ loadsymbol(ThreadContext *tc)
 void
 addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
 {
+    if (!FullSystem)
+        panicFsOnlyPseudoInst("addSymbol");
+
     char symb[100];
     CopyStringOut(tc, symb, symbolAddr, 100);
     std::string symbol(symb);
@@ -264,11 +287,14 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
 uint64_t
 initParam(ThreadContext *tc)
 {
+    if (!FullSystem) {
+        panicFsOnlyPseudoInst("initParam");
+        return 0;
+    }
+
     return tc->getCpuPtr()->system->init_param;
 }
 
-#endif
-
 
 void
 resetstats(ThreadContext *tc, Tick delay, Tick period)
@@ -321,11 +347,14 @@ m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
     exitSimLoop("checkpoint", 0, when, repeat);
 }
 
-#if FULL_SYSTEM
-
 uint64_t
 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
 {
+    if (!FullSystem) {
+        panicFsOnlyPseudoInst("readfile");
+        return 0;
+    }
+
     const string &file = tc->getSystemPtr()->params()->readfile;
     if (file.empty()) {
         return ULL(0);
@@ -358,8 +387,6 @@ readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
     return result;
 }
 
-#endif
-
 void
 debugbreak(ThreadContext *tc)
 {
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 673ec6170..399c88a4f 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -45,8 +45,6 @@ extern bool doStatisticsInsts;
 extern bool doCheckpointInsts;
 extern bool doQuiesce;
 
-#if FULL_SYSTEM
-
 void arm(ThreadContext *tc);
 void quiesce(ThreadContext *tc);
 void quiesceSkip(ThreadContext *tc);
@@ -58,71 +56,6 @@ uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
 void loadsymbol(ThreadContext *xc);
 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
 uint64_t initParam(ThreadContext *xc);
-
-#else
-
-static inline void
-panicFsOnlyPseudoInst(const char *name)
-{
-    panic("Pseudo inst \"%s\" is only available in Full System mode.");
-}
-
-static inline void
-arm(ThreadContext *tc)
-{
-    panicFsOnlyPseudoInst("arm");
-}
-static inline void
-quiesce(ThreadContext *tc)
-{
-    panicFsOnlyPseudoInst("quiesce");
-}
-static inline void
-quiesceSkip(ThreadContext *tc)
-{
-    panicFsOnlyPseudoInst("quiesceSkip");
-}
-static inline void
-quiesceNs(ThreadContext *tc, uint64_t ns)
-{
-    panicFsOnlyPseudoInst("quiesceNs");
-}
-static inline void
-quiesceCycles(ThreadContext *tc, uint64_t cycles)
-{
-    panicFsOnlyPseudoInst("quiesceCycles");
-}
-static inline uint64_t
-quiesceTime(ThreadContext *tc)
-{
-    panicFsOnlyPseudoInst("quiesceTime");
-    return 0;
-}
-static inline uint64_t
-readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
-{
-    panicFsOnlyPseudoInst("readFile");
-    return 0;
-}
-static inline void
-loadsymbol(ThreadContext *xc)
-{
-    panicFsOnlyPseudoInst("loadSymbol");
-}
-static inline void
-addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
-{
-    panicFsOnlyPseudoInst("addSymbol");
-}
-static inline uint64_t
-initParam(ThreadContext *tc)
-{
-    panicFsOnlyPseudoInst("initParam");
-    return 0;
-}
-
-#endif
-
 uint64_t rpns(ThreadContext *tc);
 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
 void m5exit(ThreadContext *tc, Tick delay);
diff --git a/src/sim/root.cc b/src/sim/root.cc
index dd7c12077..c47ada30e 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -33,6 +33,7 @@
 
 #include "base/misc.hh"
 #include "debug/TimeSync.hh"
+#include "sim/full_system.hh"
 #include "sim/root.hh"
 
 Root *Root::_root = NULL;
@@ -123,6 +124,8 @@ Root::loadState(Checkpoint *cp)
     timeSyncEnable(params()->time_sync_enable);
 }
 
+bool FullSystem;
+
 Root *
 RootParams::create()
 {
@@ -132,5 +135,7 @@ RootParams::create()
 
     created = true;
 
+    FullSystem = full_system;
+
     return new Root(this);
 }
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 7ea383b29..45c87f0ab 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -65,6 +65,7 @@
 #include "mem/se_translating_port_proxy.hh"
 #include "sim/byteswap.hh"
 #include "sim/process.hh"
+#include "sim/syscallreturn.hh"
 #include "sim/system.hh"
 
 ///
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 35e6da109..83610a102 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -48,28 +48,24 @@
 #include "arch/isa_traits.hh"
 #include "arch/remote_gdb.hh"
 #include "arch/utility.hh"
+#include "arch/vtophys.hh"
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
-#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Loader.hh"
 #include "debug/WorkItems.hh"
+#include "kern/kernel_stats.hh"
+#include "mem/fs_translating_port_proxy.hh"
 #include "mem/mem_object.hh"
 #include "mem/physical.hh"
+#include "params/System.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#include "kern/kernel_stats.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#else
-#include "params/System.hh"
-#endif
-
 using namespace std;
 using namespace TheISA;
 
@@ -81,13 +77,9 @@ System::System(Params *p)
     : MemObject(p), _systemPort("system_port", this),
       physmem(p->physmem),
       _numContexts(0),
-#if FULL_SYSTEM
       init_param(p->init_param),
       loadAddrMask(p->load_addr_mask),
-#else
-      pagePtr(0),
       nextPID(0),
-#endif
       memoryMode(p->mem_mode),
       workItemsBegin(0),
       workItemsEnd(0),
@@ -109,28 +101,23 @@ System::System(Params *p)
                                       p->memories[x]->size()));
     }
 
-#if FULL_SYSTEM
-    kernelSymtab = new SymbolTable;
-    if (!debugSymbolTable)
-        debugSymbolTable = new SymbolTable;
+    if (FullSystem) {
+        kernelSymtab = new SymbolTable;
+        if (!debugSymbolTable)
+            debugSymbolTable = new SymbolTable;
 
-    /**
-     * Get a port proxy to memory
-     */
-    physProxy = new PortProxy(*getSystemPort());
-    virtProxy = new FSTranslatingPortProxy(*getSystemPort());
-#endif
+        /**
+         * Get a port proxy to memory
+         */
+        physProxy = new PortProxy(*getSystemPort());
+        virtProxy = new FSTranslatingPortProxy(*getSystemPort());
+    }
 }
 
 System::~System()
 {
-#if FULL_SYSTEM
     delete kernelSymtab;
     delete kernel;
-#else
-    panic("System::fixFuncEventAddr needs to be rewritten "
-          "to work with syscall emulation");
-#endif // FULL_SYSTEM}
 
     for (uint32_t j = 0; j < numWorkIds; j++)
         delete workItemStats[j];
@@ -231,61 +218,64 @@ System::numRunningContexts()
 void
 System::initState()
 {
-    // Moved from the constructor to here since it relies on the
-    // address map being resolved in the interconnect
-#if FULL_SYSTEM
-    /**
-     * Load the kernel code into memory
-     */
-    if (params()->kernel == "") {
-        inform("No kernel set for full system simulation. Assuming you know what"
-                " you're doing...\n");
-    } else {
-        // Load kernel code
-        kernel = createObjectFile(params()->kernel);
-        inform("kernel located at: %s", params()->kernel);
-
-        if (kernel == NULL)
-            fatal("Could not load kernel file %s", params()->kernel);
-
-        // Load program sections into memory
-        kernel->loadSections(physProxy, loadAddrMask);
-
-        // setup entry points
-        kernelStart = kernel->textBase();
-        kernelEnd = kernel->bssBase() + kernel->bssSize();
-        kernelEntry = kernel->entryPoint();
-
-        // load symbols
-        if (!kernel->loadGlobalSymbols(kernelSymtab))
-            fatal("could not load kernel symbols\n");
-
-        if (!kernel->loadLocalSymbols(kernelSymtab))
-            fatal("could not load kernel local symbols\n");
-
-        if (!kernel->loadGlobalSymbols(debugSymbolTable))
-            fatal("could not load kernel symbols\n");
-
-        if (!kernel->loadLocalSymbols(debugSymbolTable))
-            fatal("could not load kernel local symbols\n");
-
-        DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
-        DPRINTF(Loader, "Kernel end   = %#x\n", kernelEnd);
-        DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
-        DPRINTF(Loader, "Kernel loaded...\n");
+    int i;
+    if (FullSystem) {
+        for (i = 0; i < threadContexts.size(); i++)
+            TheISA::startupCPU(threadContexts[i], i);
+        // Moved from the constructor to here since it relies on the
+        // address map being resolved in the interconnect
+        /**
+         * Load the kernel code into memory
+         */
+        if (params()->kernel == "") {
+            inform("No kernel set for full system simulation. "
+                    "Assuming you know what you're doing...\n");
+        } else {
+            // Load kernel code
+            kernel = createObjectFile(params()->kernel);
+            inform("kernel located at: %s", params()->kernel);
+
+            if (kernel == NULL)
+                fatal("Could not load kernel file %s", params()->kernel);
+
+            // Load program sections into memory
+            kernel->loadSections(physProxy, loadAddrMask);
+
+            // setup entry points
+            kernelStart = kernel->textBase();
+            kernelEnd = kernel->bssBase() + kernel->bssSize();
+            kernelEntry = kernel->entryPoint();
+
+            // load symbols
+            if (!kernel->loadGlobalSymbols(kernelSymtab))
+                fatal("could not load kernel symbols\n");
+
+            if (!kernel->loadLocalSymbols(kernelSymtab))
+                fatal("could not load kernel local symbols\n");
+
+            if (!kernel->loadGlobalSymbols(debugSymbolTable))
+                fatal("could not load kernel symbols\n");
+
+            if (!kernel->loadLocalSymbols(debugSymbolTable))
+                fatal("could not load kernel local symbols\n");
+
+            DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
+            DPRINTF(Loader, "Kernel end   = %#x\n", kernelEnd);
+            DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
+            DPRINTF(Loader, "Kernel loaded...\n");
+        }
     }
-#endif // FULL_SYSTEM
 
     // increment the number of running systms
     numSystemsRunning++;
 
     activeCpus.clear();
 
-#if FULL_SYSTEM
-    int i;
+    if (!FullSystem)
+        return;
+
     for (i = 0; i < threadContexts.size(); i++)
         TheISA::startupCPU(threadContexts[i], i);
-#endif
 }
 
 void
@@ -301,7 +291,6 @@ System::replaceThreadContext(ThreadContext *tc, int context_id)
         remoteGDB[context_id]->replaceThreadContext(tc);
 }
 
-#if !FULL_SYSTEM
 Addr
 System::allocPhysPages(int npages)
 {
@@ -324,8 +313,6 @@ System::freeMemSize()
    return physmem->size() - (pagePtr << LogVMPageSize);
 }
 
-#endif
-
 bool
 System::isMemory(const Addr addr) const
 {
@@ -347,24 +334,20 @@ System::resume()
 void
 System::serialize(ostream &os)
 {
-#if FULL_SYSTEM
-    kernelSymtab->serialize("kernel_symtab", os);
-#else // !FULL_SYSTEM
+    if (FullSystem)
+        kernelSymtab->serialize("kernel_symtab", os);
     SERIALIZE_SCALAR(pagePtr);
     SERIALIZE_SCALAR(nextPID);
-#endif
 }
 
 
 void
 System::unserialize(Checkpoint *cp, const string &section)
 {
-#if FULL_SYSTEM
-    kernelSymtab->unserialize("kernel_symtab", cp, section);
-#else // !FULL_SYSTEM
+    if (FullSystem)
+        kernelSymtab->unserialize("kernel_symtab", cp, section);
     UNSERIALIZE_SCALAR(pagePtr);
     UNSERIALIZE_SCALAR(nextPID);
-#endif
 }
 
 void
@@ -418,12 +401,8 @@ printSystems()
 const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
     "timing"};
 
-#if !FULL_SYSTEM
-
 System *
 SystemParams::create()
 {
     return new System(this);
 }
-
-#endif
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 53f1762c7..eb192fb99 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -53,29 +53,23 @@
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "base/statistics.hh"
-#include "config/full_system.hh"
 #include "cpu/pc_event.hh"
 #include "enums/MemoryMode.hh"
+#include "kern/system_events.hh"
 #include "mem/mem_object.hh"
 #include "mem/port.hh"
 #include "params/System.hh"
 
-#if FULL_SYSTEM
-#include "kern/system_events.hh"
-#endif
-
 class BaseCPU;
-class ThreadContext;
+class BaseRemoteGDB;
+class FSTranslatingPortProxy;
+class GDBListener;
 class ObjectFile;
 class PhysicalMemory;
-
-#if FULL_SYSTEM
 class Platform;
 class PortProxy;
-class FSTranslatingPortProxy;
-#endif
-class GDBListener;
-class BaseRemoteGDB;
+class ThreadContext;
+class VirtualPort;
 
 class System : public MemObject
 {
@@ -181,8 +175,8 @@ class System : public MemObject
      */
     bool isMemory(const Addr addr) const;
 
-#if FULL_SYSTEM
-    Platform *platform;
+    Addr pagePtr;
+
     uint64_t init_param;
 
     /** Port to physical memory used for writing object files into ram at
@@ -213,10 +207,6 @@ class System : public MemObject
      */
     Addr loadAddrMask;
 
-#else
-
-    Addr pagePtr;
-
   protected:
     uint64_t nextPID;
 
@@ -232,9 +222,6 @@ class System : public MemObject
     /** Amount of physical memory that exists */
     Addr memSize();
 
-
-#endif // FULL_SYSTEM
-
   protected:
     Enums::MemoryMode memoryMode;
     uint64_t workItemsBegin;
@@ -290,13 +277,15 @@ class System : public MemObject
 
     void workItemEnd(uint32_t tid, uint32_t workid);
 
-#if FULL_SYSTEM
     /**
      * Fix up an address used to match PCs for hooking simulator
      * events on to target function executions.  See comment in
      * system.cc for details.
      */
-    virtual Addr fixFuncEventAddr(Addr addr) = 0;
+    virtual Addr fixFuncEventAddr(Addr addr)
+    {
+        panic("Base fixFuncEventAddr not implemented.\n");
+    }
 
     /**
      * Add a function-based event to the given function, to be looked
@@ -322,7 +311,6 @@ class System : public MemObject
         return addFuncEvent<T>(kernelSymtab, lbl);
     }
 
-#endif
   public:
     std::vector<BaseRemoteGDB *> remoteGDB;
     std::vector<GDBListener *> gdbListen;
@@ -344,7 +332,6 @@ class System : public MemObject
 
   public:
 
-#if FULL_SYSTEM
     /**
      * Returns the addess the kernel starts at.
      * @return address the kernel starts at
@@ -363,14 +350,10 @@ class System : public MemObject
      */
     Addr getKernelEntry() const { return kernelEntry; }
 
-#else
-
     /// Allocate npages contiguous unused physical pages
     /// @return Starting address of first page
     Addr allocPhysPages(int npages);
 
-#endif // FULL_SYSTEM
-
     int registerThreadContext(ThreadContext *tc, int assigned=-1);
     void replaceThreadContext(ThreadContext *tc, int context_id);
 
diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index 8cde0db2e..86428f168 100644
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -31,23 +31,23 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "sim/faults.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 #include "sim/tlb.hh"
 
 Fault
 GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
 {
-#if FULL_SYSTEM
+    if (FullSystem)
         panic("Generic translation shouldn't be used in full system mode.\n");
-#else
-        Process * p = tc->getProcessPtr();
 
-        Fault fault = p->pTable->translate(req);
-        if(fault != NoFault)
-            return fault;
+    Process * p = tc->getProcessPtr();
 
-        return NoFault;
-#endif
+    Fault fault = p->pTable->translate(req);
+    if(fault != NoFault)
+        return fault;
+
+    return NoFault;
 }
 
 void
diff --git a/tests/SConscript b/tests/SConscript
index 12328c0c1..46d4ca400 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -233,12 +233,12 @@ updateAction = env.Action(update_test, update_test_string)
 def test_builder(env, ref_dir):
     """Define a test."""
 
-    (category, name, _ref, isa, opsys, config) = ref_dir.split('/')
+    (category, mode, name, _ref, isa, opsys, config) = ref_dir.split('/')
     assert(_ref == 'ref')
 
     # target path (where test output goes) is the same except without
     # the 'ref' component
-    tgt_dir = os.path.join(category, name, isa, opsys, config)
+    tgt_dir = os.path.join(category, mode, name, isa, opsys, config)
 
     # prepend file name with tgt_dir
     def tgt(f):
@@ -265,34 +265,32 @@ def test_builder(env, ref_dir):
 
 # Figure out applicable configs based on build type
 configs = []
-if env['FULL_SYSTEM']:
-    if env['TARGET_ISA'] == 'alpha':
-        configs += ['tsunami-simple-atomic',
-                    'tsunami-simple-timing',
-                    'tsunami-simple-atomic-dual',
-                    'tsunami-simple-timing-dual',
-                    'twosys-tsunami-simple-atomic',
-                    'tsunami-o3', 'tsunami-o3-dual',
-                    'tsunami-inorder']
-    if env['TARGET_ISA'] == 'sparc':
-        configs += ['t1000-simple-atomic',
-                    't1000-simple-timing']
-    if env['TARGET_ISA'] == 'arm':
-        configs += ['realview-simple-atomic',
-                    'realview-simple-atomic-dual',
-                    'realview-simple-timing',
-                    'realview-simple-timing-dual',
-                    'realview-o3',
-                    'realview-o3-dual']
-    if env['TARGET_ISA'] == 'x86':
-        configs += ['pc-simple-atomic',
-                    'pc-simple-timing',
-                    'pc-o3-timing']
-
-else:
-    configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
-                'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
-                'inorder-timing', 'rubytest']
+if env['TARGET_ISA'] == 'alpha':
+    configs += ['tsunami-simple-atomic',
+                'tsunami-simple-timing',
+                'tsunami-simple-atomic-dual',
+                'tsunami-simple-timing-dual',
+                'twosys-tsunami-simple-atomic',
+                'tsunami-o3', 'tsunami-o3-dual',
+                'tsunami-inorder']
+if env['TARGET_ISA'] == 'sparc':
+    configs += ['t1000-simple-atomic',
+                't1000-simple-timing']
+if env['TARGET_ISA'] == 'arm':
+    configs += ['realview-simple-atomic',
+                'realview-simple-atomic-dual',
+                'realview-simple-timing',
+                'realview-simple-timing-dual',
+                'realview-o3',
+                'realview-o3-dual']
+if env['TARGET_ISA'] == 'x86':
+    configs += ['pc-simple-atomic',
+                'pc-simple-timing',
+                'pc-o3-timing']
+
+configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
+            'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
+            'inorder-timing', 'rubytest']
 
 if env['PROTOCOL'] != 'None':
     if env['PROTOCOL'] == 'MI_example':
@@ -303,7 +301,7 @@ if env['PROTOCOL'] != 'None':
 cwd = os.getcwd()
 os.chdir(str(Dir('.').srcdir))
 for config in configs:
-    dirs = glob.glob('*/*/ref/%s/*/%s' % (env['TARGET_ISA'], config))
+    dirs = glob.glob('*/*/*/ref/%s/*/%s' % (env['TARGET_ISA'], config))
     for d in dirs:
         if not os.path.exists(os.path.join(d, 'skip')):
             test_builder(env, d)
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 1bab83609..2a87cb663 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 2517e7670..52eb52904 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -33,9 +33,6 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -117,7 +114,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 66e49a63e..c1358eecd 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b14f0e5b1..2f8829db0 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 67aaebd21..9436cf88a 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -86,7 +86,7 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 07851ae9f..b967a5080 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,4 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 395fd24a3..9701b1012 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0fe23d1ee..f3b8e700f 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index eeff17069..62c7c7bd4 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index a1b2f4676..cbfda22a2 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 69c583abd..adab96fcb 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index bab5a193d..f466bc480 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index edfd940ad..5baa3c91a 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 83f85641a..f1de86411 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 7fe0d409b..81646f825 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 90f2539e6..8d1840571 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index a7e598b0a..2531a30c8 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -34,9 +34,6 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need.  It's expected this file is in m5/configs/example.
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -112,7 +109,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 705f13ef3..fe0311801 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index e722ef334..db0c0b9c0 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -85,5 +85,5 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 191230164..eb7415b8d 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e1..c57ffd1f2 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -32,9 +32,6 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -95,7 +92,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f1ebb1939..c82ef0a26 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 359421a49..46436d18c 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -32,9 +32,6 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 import os, optparse, sys
 
-if buildEnv['FULL_SYSTEM']:
-    panic("This script requires system-emulation mode (*_SE).")
-
 # Get paths we might need
 config_path = os.path.dirname(os.path.abspath(__file__))
 config_root = os.path.dirname(config_path)
@@ -82,8 +79,7 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
 # Tie the cpu cache ports to the ruby cpu ports and
 # physmem, respectively
 #
-cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
-cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
+cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
 
 # Connect the system port for loading of binaries etc
 system.system_port = system.ruby._sys_port_proxy.port
@@ -92,7 +88,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cc0d1d207..19b40fe48 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system=False, system = system)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index ae2c59110..217135bf0 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index a08261533..dc30633b3 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index c63637f73..1680be166 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -95,6 +95,6 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index a6bb4b122..accf350b3 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 758dbef09..9a29f5c65 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -93,5 +93,5 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index a2335d763..897b1c946 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index ad466a5c0..6b78b71f4 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -93,7 +93,7 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
 
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 7dc0ded5c..e3a764e16 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 658508fa0..d32e5dd87 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
 drive_sys.iobridge.slave = drive_sys.iobus.port
 drive_sys.iobridge.master = drive_sys.membus.port
 
-root = makeDualRoot(test_sys, drive_sys, "ethertrace")
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 94bfc8925..94bfc8925 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 35f0311de..35f0311de 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index d2e784a3f..d2e784a3f 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 6c5842787..6c5842787 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index b0a37466e..b0a37466e 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 2911b29fc..2911b29fc 100755
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index de8941321..de8941321 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 1b4012ef1..1b4012ef1 100644
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 6f9417ef5..6f9417ef5 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index 04178bb32..04178bb32 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 28da0bb31..28da0bb31 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 11b3b4098..11b3b4098 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
index 48fe3dacf..48fe3dacf 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
index 0453fa273..0453fa273 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index c84a9ea85..c84a9ea85 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index affb69ad6..affb69ad6 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 231dec8b1..231dec8b1 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index ad6b1630f..ad6b1630f 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
index 1dbe30c5e..1dbe30c5e 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 9b8aaf5dd..9b8aaf5dd 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
index fd09f1faf..fd09f1faf 100755
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 9036859eb..9036859eb 100755
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 9cc68e765..9cc68e765 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
index 6cae7ef0f..6cae7ef0f 100644
--- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
diff --git a/tests/long/10.linux-boot/test.py b/tests/long/fs/10.linux-boot/test.py
index 215d63700..215d63700 100644
--- a/tests/long/10.linux-boot/test.py
+++ b/tests/long/fs/10.linux-boot/test.py
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 409b736b6..409b736b6 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
index 179231b2e..179231b2e 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index d81b5c20f..d81b5c20f 100755
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 21a50a501..21a50a501 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
index e69de29bb..e69de29bb 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
index f90a96e24..f90a96e24 100644
--- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
diff --git a/tests/long/80.solaris-boot/test.py b/tests/long/fs/80.solaris-boot/test.py
index 1b9a4c255..1b9a4c255 100644
--- a/tests/long/80.solaris-boot/test.py
+++ b/tests/long/fs/80.solaris-boot/test.py
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index 6c1c0e974..6c1c0e974 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 30b31a527..30b31a527 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index b5662ac02..b5662ac02 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index cc9b0c683..cc9b0c683 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
index ad1c408b1..ad1c408b1 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 8681db468..8681db468 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
index 282141772..282141772 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
index 1dc402141..1dc402141 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
index ad4f39b85..ad4f39b85 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 0bc5277c7..0bc5277c7 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
index 36bd68fb7..36bd68fb7 100755
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index 4d7850adf..4d7850adf 100644
--- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
index 9f24d0367..9f24d0367 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
index d3786fda6..d3786fda6 100755
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 5022d17a1..5022d17a1 100644
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
index 8c7671d34..8c7671d34 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
index 95da0efca..95da0efca 100755
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
index f48dc3640..f48dc3640 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
index 6a1e2b970..6a1e2b970 100644
--- a/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
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diff --git a/tests/long/00.gzip/ref/arm/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
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index 589b03862..589b03862 100755
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index 3846f97fb..3846f97fb 100644
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diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
index dcba73ec2..dcba73ec2 100644
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diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
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index a835cbd79..a835cbd79 100755
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index e4d9fca07..e4d9fca07 100644
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diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
index b52495d06..b52495d06 100644
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diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
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index d2df5cc09..d2df5cc09 100755
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+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 96706c5cc..96706c5cc 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
index 095132477..095132477 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index eb189c10a..eb189c10a 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index e99e16cd0..e99e16cd0 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 008adeebb..008adeebb 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
index 095132477..095132477 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index e89b51a20..e89b51a20 100755
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 59ae818d2..59ae818d2 100644
--- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
diff --git a/tests/long/10.mcf/test.py b/tests/long/se/10.mcf/test.py
index 9bd18a83f..9bd18a83f 100644
--- a/tests/long/10.mcf/test.py
+++ b/tests/long/se/10.mcf/test.py
diff --git a/tests/long/20.parser/ref/alpha/tru64/NOTE b/tests/long/se/20.parser/ref/alpha/tru64/NOTE
index 5e7d8c358..5e7d8c358 100644
--- a/tests/long/20.parser/ref/alpha/tru64/NOTE
+++ b/tests/long/se/20.parser/ref/alpha/tru64/NOTE
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index e2c071016..e2c071016 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index c61c0591a..c61c0591a 100755
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 0cc2b2b8d..0cc2b2b8d 100644
--- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index cbe7d05b4..cbe7d05b4 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index e26a927e8..e26a927e8 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 12a51d6fd..12a51d6fd 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 5a2d86232..5a2d86232 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 8c1353073..8c1353073 100755
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index f9d747bd5..f9d747bd5 100644
--- a/tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 50d3ef009..50d3ef009 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index b3bd7cb12..b3bd7cb12 100755
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index f99849c12..f99849c12 100644
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index b1057156b..b1057156b 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index b86175ab2..b86175ab2 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4e0a10e13..4e0a10e13 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index c570a48d2..c570a48d2 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index a297c4bc8..a297c4bc8 100755
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 28d09902a..28d09902a 100644
--- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
diff --git a/tests/long/20.parser/test.py b/tests/long/se/20.parser/test.py
index c96a46e60..c96a46e60 100644
--- a/tests/long/20.parser/test.py
+++ b/tests/long/se/20.parser/test.py
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index 16e4d1756..16e4d1756 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
index 860580eeb..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 1c2a18294..1c2a18294 100755
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index a04efd18a..a04efd18a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 0fce2844b..0fce2844b 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
index 860580eeb..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 137fd0ee8..137fd0ee8 100755
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 28785f469..28785f469 100644
--- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 8310ba9e4..8310ba9e4 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
index 860580eeb..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index 3a628f576..3a628f576 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 3ed2b47f1..3ed2b47f1 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 63aac5a1a..63aac5a1a 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
index 860580eeb..860580eeb 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index 06075d86e..06075d86e 100755
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index af7a7f90d..af7a7f90d 100644
--- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 297538e80..297538e80 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
index bf930ad43..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 2948fc7c4..2948fc7c4 100755
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 995432cc7..995432cc7 100644
--- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 5628f29f0..5628f29f0 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
index bf930ad43..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 2369bef1b..2369bef1b 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 7857a9031..7857a9031 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 28a0917d8..28a0917d8 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index bf930ad43..bf930ad43 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index 3428f8224..3428f8224 100755
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 3b365c759..3b365c759 100644
--- a/tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/30.eon/test.py b/tests/long/se/30.eon/test.py
index de4d12dd8..de4d12dd8 100644
--- a/tests/long/30.eon/test.py
+++ b/tests/long/se/30.eon/test.py
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index c87170fbe..c87170fbe 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index ca52b457d..ca52b457d 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 2a099e16b..2a099e16b 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 90210da82..90210da82 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index a895468a4..a895468a4 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index ca52b457d..ca52b457d 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 67c7a90bd..67c7a90bd 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 5a9e50b92..5a9e50b92 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index f60b78837..f60b78837 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index ca52b457d..ca52b457d 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index e767ec1c4..e767ec1c4 100755
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 668a6f1dd..668a6f1dd 100644
--- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 7e5e4838d..7e5e4838d 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
index cba73e085..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index af8b043ac..af8b043ac 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 7b72f7ce4..7b72f7ce4 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 6a275dc9a..6a275dc9a 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index cba73e085..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index dd29e750e..dd29e750e 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index 49ae2817e..49ae2817e 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 01aaafc03..01aaafc03 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
index cba73e085..cba73e085 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index df0dd80b9..df0dd80b9 100755
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 117215dc5..117215dc5 100644
--- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/40.perlbmk/test.py b/tests/long/se/40.perlbmk/test.py
index 8fe5d6047..8fe5d6047 100644
--- a/tests/long/40.perlbmk/test.py
+++ b/tests/long/se/40.perlbmk/test.py
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index 1b963b10c..1b963b10c 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 0aab67a06..0aab67a06 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
index 472b08431..472b08431 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 32a07ce20..32a07ce20 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index ea038d4da..ea038d4da 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index 9e435cc97..9e435cc97 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
index 472b08431..472b08431 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 9c4b77b7d..9c4b77b7d 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index d8535707b..d8535707b 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 160c80ddb..160c80ddb 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
index 472b08431..472b08431 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index 4fc91e266..4fc91e266 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index f99b5fb55..f99b5fb55 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index e74b48d2a..e74b48d2a 100755
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
index 472b08431..472b08431 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 59b869a9f..59b869a9f 100644
--- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 1feff9641..1feff9641 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 41153b9d0..41153b9d0 100755
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 858b9d08f..858b9d08f 100644
--- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 321a621c1..321a621c1 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index cba7edc9e..cba7edc9e 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 550377594..550377594 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 62eb4cdbf..62eb4cdbf 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index 4fb750502..4fb750502 100755
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
diff --git a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 2fff6cef5..2fff6cef5 100644
--- a/tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 2df6b792d..2df6b792d 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
index bb51748c6..bb51748c6 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 542479326..542479326 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
index 0ac2d9980..0ac2d9980 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index dc6c31998..dc6c31998 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 5e34ae7a1..5e34ae7a1 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
index bb51748c6..bb51748c6 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 787eaa97a..787eaa97a 100755
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
index 0ac2d9980..0ac2d9980 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
index 726b45c60..726b45c60 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 168a8eefa..168a8eefa 100644
--- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
diff --git a/tests/long/50.vortex/test.py b/tests/long/se/50.vortex/test.py
index 92422c234..92422c234 100644
--- a/tests/long/50.vortex/test.py
+++ b/tests/long/se/50.vortex/test.py
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 0d09e2e14..0d09e2e14 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 8bc14bb8a..8bc14bb8a 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index bf815a6e1..bf815a6e1 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 4951679e2..4951679e2 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 35ea78ab1..35ea78ab1 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 3e098da07..3e098da07 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 52ac7c920..52ac7c920 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 3465b9fda..3465b9fda 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 1f32f6942..1f32f6942 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index b74c06509..b74c06509 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 5e40861f7..5e40861f7 100755
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 99a911858..99a911858 100644
--- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 669a8b83b..669a8b83b 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 1474108e5..1474108e5 100755
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index bd2b3efef..bd2b3efef 100644
--- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index bbede2479..bbede2479 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index e599bde0b..e599bde0b 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index e23300649..e23300649 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 71abd898d..71abd898d 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 8198567b7..8198567b7 100755
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 04e3122e6..04e3122e6 100644
--- a/tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index fe30d10a3..fe30d10a3 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index a5a0064e6..a5a0064e6 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 6725100b8..6725100b8 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index e57f67518..e57f67518 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 5d5232885..5d5232885 100755
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 94c5d24c6..94c5d24c6 100644
--- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
diff --git a/tests/long/60.bzip2/test.py b/tests/long/se/60.bzip2/test.py
index fa74d0860..fa74d0860 100644
--- a/tests/long/60.bzip2/test.py
+++ b/tests/long/se/60.bzip2/test.py
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 64fd65cd8..64fd65cd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index ab1cbef0e..ab1cbef0e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
index 98777e0af..98777e0af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index db43e1bd8..db43e1bd8 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index a6f9e5430..a6f9e5430 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 9901dc40b..9901dc40b 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
index 98777e0af..98777e0af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 55d9dc21f..55d9dc21f 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index c3b5c0104..c3b5c0104 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 887ca3f4e..887ca3f4e 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
index 98777e0af..98777e0af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index af93195e1..af93195e1 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 2fe44f969..2fe44f969 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
index 1b49765a7..1b49765a7 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 84097b1db..84097b1db 100755
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
index 98777e0af..98777e0af 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index ba87aad33..ba87aad33 100644
--- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 8db3f9119..8db3f9119 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index bee9aa417..bee9aa417 100755
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 4282a0231..4282a0231 100644
--- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 01def30a3..01def30a3 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index f2a9f0661..f2a9f0661 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 079a70f11..079a70f11 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 3f54c6512..3f54c6512 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index b21763742..b21763742 100755
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index d861ddab1..d861ddab1 100644
--- a/tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 5551fc718..5551fc718 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 5a1dc45d3..5a1dc45d3 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index fabf573dd..fabf573dd 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 2d0b36d34..2d0b36d34 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index e7f89f9a0..e7f89f9a0 100755
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 16bfeed42..16bfeed42 100644
--- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index b8115d922..b8115d922 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 3d5ba32f2..3d5ba32f2 100755
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.out b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 5be6519a9..5be6519a9 100644
--- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index 4d9868de9..4d9868de9 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 3217ab200..3217ab200 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 39967f660..39967f660 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index d7a510398..d7a510398 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..ac4ad20a5 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index a3170a407..a3170a407 100755
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
index 00387ae5c..00387ae5c 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
index 62b922e4e..62b922e4e 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
index bdc569e39..bdc569e39 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
index 6e2601e82..6e2601e82 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
index 04c8e9935..04c8e9935 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
index 9dd68ecdb..9dd68ecdb 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
index a4c2eac35..a4c2eac35 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 1c9d2c1e6..1c9d2c1e6 100644
--- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
diff --git a/tests/long/70.twolf/test.py b/tests/long/se/70.twolf/test.py
index 761ec8b2e..761ec8b2e 100644
--- a/tests/long/70.twolf/test.py
+++ b/tests/long/se/70.twolf/test.py
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index bd95bae49..bd95bae49 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index dbef4ddb7..dbef4ddb7 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index c3dae4684..c3dae4684 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
index 6129834bd..6129834bd 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index b72ae72cb..b72ae72cb 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 9b658d14c..9b658d14c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 7f4c99b34..7f4c99b34 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
index f17158b67..f17158b67 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 1a4bf8750..1a4bf8750 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 3af3fc1dd..3af3fc1dd 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 628ea2e3e..628ea2e3e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index aa80e0b5e..aa80e0b5e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 54195aa23..54195aa23 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 0bcb6e870..0bcb6e870 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index 826f2c28b..826f2c28b 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index ac9598c08..ac9598c08 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index ff644ed3f..ff644ed3f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 84e5e8c3f..84e5e8c3f 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
index 04178bb32..04178bb32 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 417579719..417579719 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 2ca0aa5cb..2ca0aa5cb 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
index 10632c381..10632c381 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
index ac162c148..ac162c148 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 5b5bd9164..5b5bd9164 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 9a28ceb37..9a28ceb37 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index e355498ce..e355498ce 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index e3050fa31..e3050fa31 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 586cb6b73..586cb6b73 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
index eabb40181..eabb40181 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 82d6c82a5..82d6c82a5 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
index 04178bb32..04178bb32 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 2f40c0e53..2f40c0e53 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 6f6f084e3..6f6f084e3 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
index 9e24c3e8a..9e24c3e8a 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
index 7e7f32a27..7e7f32a27 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index b4466ea53..b4466ea53 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index 9a28ceb37..9a28ceb37 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 661533caf..661533caf 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 543720998..543720998 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
index 8953751c2..8953751c2 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
index 33e436852..33e436852 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 91a089b4b..91a089b4b 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
index fd09f1faf..fd09f1faf 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index 23cf47db2..23cf47db2 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 324bf8929..324bf8929 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
index ab8215fe1..ab8215fe1 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index e3a339662..e3a339662 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
index fd09f1faf..fd09f1faf 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 5dde537a2..5dde537a2 100755
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index c4a248e5e..c4a248e5e 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
index a1c03790e..a1c03790e 100644
--- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
diff --git a/tests/quick/10.linux-boot/test.py b/tests/quick/fs/10.linux-boot/test.py
index 215d63700..215d63700 100644
--- a/tests/quick/10.linux-boot/test.py
+++ b/tests/quick/fs/10.linux-boot/test.py
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 4bff39dc1..4bff39dc1 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
index d501adb38..d501adb38 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index 7390a9ac7..7390a9ac7 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index d1174531e..d1174531e 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
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diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index c3a385a95..c3a385a95 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
index 9468ea620..9468ea620 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
diff --git a/tests/quick/80.netperf-stream/test.py b/tests/quick/fs/80.netperf-stream/test.py
index 1da47fca4..1da47fca4 100644
--- a/tests/quick/80.netperf-stream/test.py
+++ b/tests/quick/fs/80.netperf-stream/test.py
diff --git a/tests/quick/00.hello.mp/test.py b/tests/quick/se/00.hello.mp/test.py
index 91fbfb7ed..91fbfb7ed 100644
--- a/tests/quick/00.hello.mp/test.py
+++ b/tests/quick/se/00.hello.mp/test.py
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index b17544f09..b17544f09 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr
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diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index ba10334c5..ba10334c5 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
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diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 4ce82e64f..4ce82e64f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
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diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index db5baf5c5..db5baf5c5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
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diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
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diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 6e993ab1c..6e993ab1c 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
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diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 3b3d572bb..3b3d572bb 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index df86e7077..df86e7077 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
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index 9f50fe960..9f50fe960 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
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index 7ceb6a8be..7ceb6a8be 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index b9fd9c5f2..b9fd9c5f2 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index c2d3c97af..c2d3c97af 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index c93c8f8af..c93c8f8af 100755
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index 3bba58631..3bba58631 100644
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 607ab419c..607ab419c 100644
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index 03b0eda65..03b0eda65 100644
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index e45cd058f..e45cd058f 100755
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diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index ed47704f6..ed47704f6 100755
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index fdc12b275..fdc12b275 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 23e50fd7f..23e50fd7f 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 89c8aeac1..89c8aeac1 100644
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index 1c4da6ce4..1c4da6ce4 100644
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index 31ae36f2e..31ae36f2e 100755
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index dc0ba2922..dc0ba2922 100755
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index ebac3fa83..ebac3fa83 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index e5748fef4..e5748fef4 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index f2273438f..f2273438f 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 31ae36f2e..31ae36f2e 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 0529ad1d8..0529ad1d8 100755
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 8d97fa8c6..8d97fa8c6 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 4c0569af0..4c0569af0 100644
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index 2d266c770..2d266c770 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 31ae36f2e..31ae36f2e 100755
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 476a0b599..476a0b599 100755
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index fd5600236..fd5600236 100644
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diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 209bb4d8d..209bb4d8d 100644
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index 452952d26..452952d26 100644
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index af1c56980..af1c56980 100755
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index e45cd058f..e45cd058f 100755
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index e45cd058f..e45cd058f 100755
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index e45cd058f..e45cd058f 100755
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index e45cd058f..e45cd058f 100755
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--- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
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diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 6652fe60b..6652fe60b 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index 14970f00a..14970f00a 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 3a1cfc4e9..3a1cfc4e9 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 421dd8a46..421dd8a46 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index df7964c68..df7964c68 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 389636d62..389636d62 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index fb5a1cb83..fb5a1cb83 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index d982745c0..d982745c0 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index f52890637..f52890637 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
diff --git a/tests/quick/02.insttest/test.py b/tests/quick/se/02.insttest/test.py
index 93664fbef..93664fbef 100644
--- a/tests/quick/02.insttest/test.py
+++ b/tests/quick/se/02.insttest/test.py
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
index a442ec572..a442ec572 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr
index 7ded22db8..7ded22db8 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout
index ee0eb672e..ee0eb672e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt
index 119cc8e9d..119cc8e9d 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 1a56ca25e..1a56ca25e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
index 47fb3b40c..47fb3b40c 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index 4c837ce08..4c837ce08 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index aaf712409..aaf712409 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 5293d87cb..5293d87cb 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
index 47fb3b40c..47fb3b40c 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index 596eb6dd7..596eb6dd7 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index e27e0bfbf..e27e0bfbf 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
diff --git a/tests/quick/20.eio-short/test.py b/tests/quick/se/20.eio-short/test.py
index 210f21b14..210f21b14 100644
--- a/tests/quick/20.eio-short/test.py
+++ b/tests/quick/se/20.eio-short/test.py
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 63867abf6..63867abf6 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index c3b5cc937..c3b5cc937 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 6bbd017e9..6bbd017e9 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index f73f5744f..f73f5744f 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index fcea1bc67..fcea1bc67 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 98d9eda34..98d9eda34 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 7540f8e27..7540f8e27 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 16349cad5..16349cad5 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
diff --git a/tests/quick/30.eio-mp/test.py b/tests/quick/se/30.eio-mp/test.py
index 3dbb7614a..3dbb7614a 100644
--- a/tests/quick/30.eio-mp/test.py
+++ b/tests/quick/se/30.eio-mp/test.py
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index eb497bb90..eb497bb90 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 0491d5141..0491d5141 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 191a42060..191a42060 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 65fcae2f7..65fcae2f7 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 8daa6c894..8daa6c894 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 0cc0a830c..0cc0a830c 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
index a2a28909c..a2a28909c 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
index 5758c154e..5758c154e 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
index eabe42249..eabe42249 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
index 24f1aa5ae..24f1aa5ae 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
index 9b90a4abd..9b90a4abd 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
index 977b2c7d7..977b2c7d7 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index ae7e021b5..ae7e021b5 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
index e45cd058f..e45cd058f 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 6f90c0dd1..6f90c0dd1 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 0ce3fe3af..0ce3fe3af 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
diff --git a/tests/quick/40.m5threads-test-atomic/test.py b/tests/quick/se/40.m5threads-test-atomic/test.py
index 50976c771..50976c771 100755
--- a/tests/quick/40.m5threads-test-atomic/test.py
+++ b/tests/quick/se/40.m5threads-test-atomic/test.py
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index b96bfd745..b96bfd745 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index 83d47d194..83d47d194 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
index c4fb7c226..c4fb7c226 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index 20caf030d..20caf030d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index bb265760e..bb265760e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index e0267adf3..e0267adf3 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index 78fcf4ec9..78fcf4ec9 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 5229c9187..5229c9187 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index b246a2d4a..b246a2d4a 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index ec3afa4a7..ec3afa4a7 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index 84c75eb68..84c75eb68 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index 5b7a6fff2..5b7a6fff2 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 5a17811d1..5a17811d1 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index 0dc21efd5..0dc21efd5 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index d79a41535..d79a41535 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 74320f307..74320f307 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index 9f2e0a2cf..9f2e0a2cf 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index 00cab8c91..00cab8c91 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index 8fe5f45d4..8fe5f45d4 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 38761c37f..38761c37f 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index bcc5fa575..bcc5fa575 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index d3193509d..d3193509d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index 8802752c7..8802752c7 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 0a1ec6a6d..0a1ec6a6d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 95c30ab1c..95c30ab1c 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
index ac8d82ede..ac8d82ede 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
index afb940009..afb940009 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index c76c33576..c76c33576 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 82bd7a1b0..82bd7a1b0 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
diff --git a/tests/quick/50.memtest/test.py b/tests/quick/se/50.memtest/test.py
index 90beae0c6..90beae0c6 100644
--- a/tests/quick/50.memtest/test.py
+++ b/tests/quick/se/50.memtest/test.py
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
index ad26765cf..ad26765cf 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 160177fb6..160177fb6 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index bb1def18d..bb1def18d 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index a412dab3a..a412dab3a 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index cc5b405b4..cc5b405b4 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 9cbc6e028..9cbc6e028 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index dfaf3cf5d..dfaf3cf5d 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 59e160c20..59e160c20 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 753a30469..753a30469 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index ef66b37d5..ef66b37d5 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 151753306..151753306 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 35d3a3293..35d3a3293 100644
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index 3ae5a9266..3ae5a9266 100644
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 2e775c964..2e775c964 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 959553323..959553323 100755
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index e2e363d28..e2e363d28 100644
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index e6be42bee..e6be42bee 100644
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index 7421fe4ce..7421fe4ce 100644
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diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index cfdf73ce9..cfdf73ce9 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index c0a210974..c0a210974 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 22332d2ed..22332d2ed 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
diff --git a/tests/quick/60.rubytest/test.py b/tests/quick/se/60.rubytest/test.py
index e5e3d8b1c..e5e3d8b1c 100644
--- a/tests/quick/60.rubytest/test.py
+++ b/tests/quick/se/60.rubytest/test.py
diff --git a/tests/run.py b/tests/run.py
index f4105fb41..d0239b2b1 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -39,7 +39,7 @@ import m5
 m5.disableAllListeners()
 
 # single "path" arg encodes everything we need to know about test
-(category, name, isa, opsys, config) = sys.argv[1].split('/')[-5:]
+(category, mode, name, isa, opsys, config) = sys.argv[1].split('/')[-6:]
 
 # find path to directory containing this file
 tests_root = os.path.dirname(__file__)
@@ -74,8 +74,8 @@ execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
 maxtick = m5.MaxTick
 
 # tweak configuration for specific test
-sys.path.append(joinpath(tests_root, category, name))
-execfile(joinpath(tests_root, category, name, 'test.py'))
+sys.path.append(joinpath(tests_root, category, mode, name))
+execfile(joinpath(tests_root, category, mode, name, 'test.py'))
 
 # instantiate configuration
 m5.instantiate()