diff options
35 files changed, 970 insertions, 80 deletions
@@ -46,6 +46,7 @@ Ronald G. Dreslinski Jr * Caches/Cache coherence * Prefetching * New memory system (port, request, packet, cache porting) +* Tru64 MP support Lisa R. Hsu ----------------------- @@ -56,13 +57,14 @@ Lisa R. Hsu Gabriel Black ----------------------- * Multiple ISA support -* Alpha support reorgization +* Alpha support reorganization * SPARC SE support Korey L. Sewell ----------------------- * O3CPU SMT support -* MIPS support +* MIPS ISA support +* Multiple ISA support in O3CPU Andrew L. Schultz ----------------------- diff --git a/configs/example/fs.py b/configs/example/fs.py index 92d2e29e6..7c888c536 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -102,21 +102,19 @@ else: m5.instantiate(root) -#exit_event = m5.simulate(2600000000000) -#if exit_event.getCause() != "user interrupt received": -# m5.checkpoint(root, 'cpt') -# exit_event = m5.simulate(300000000000) -# if exit_event.getCause() != "user interrupt received": -# m5.checkpoint(root, 'cptA') - - if options.maxtick: - exit_event = m5.simulate(options.maxtick) + arg = options.maxtick elif options.maxtime: simtime = int(options.maxtime * root.clock.value) print "simulating for: ", simtime - exit_event = m5.simulate(simtime) + arg = simtime else: - exit_event = m5.simulate() + arg = -1 + +exit_event = m5.simulate(arg) + +while exit_event.getCause() == "checkpoint": + m5.checkpoint(root, "cpt.%d") + exit_event = m5.simulate(arg) print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause() diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 990db88ac..25be9d455 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -672,9 +672,9 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid) assert(cacheBlocked); cacheBlocked = false; retryTid = -1; - retryPkt = NULL; delete retryPkt->req; delete retryPkt; + retryPkt = NULL; } fetchStatus[tid] = Squashing; diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index db2c253e1..2bbab71f0 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -71,6 +71,11 @@ template <class Impl> void LSQ<Impl>::DcachePort::recvRetry() { + if (lsq->retryTid == -1) + { + //Squashed, so drop it + return; + } lsq->thread[lsq->retryTid].recvRetry(); // Speculatively clear the retry Tid. This will get set again if // the LSQUnit was unable to complete its access. diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 512b5a63c..1358a3699 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -646,6 +646,8 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) // handle it. if (lsq->cacheBlocked()) { ++lsqCacheBlocked; + + iewStage->decrWb(load_inst->seqNum); // There's an older load that's already going to squash. if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) return NoFault; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 4f5dbbf1c..fa716c712 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -626,6 +626,7 @@ LSQUnit<Impl>::writebackStores() ++lsqCacheBlocked; assert(retryPkt == NULL); retryPkt = data_pkt; + lsq->setRetryTid(lsqID); } else { storePostSend(data_pkt); } @@ -869,6 +870,7 @@ LSQUnit<Impl>::recvRetry() storePostSend(retryPkt); retryPkt = NULL; isStoreBlocked = false; + lsq->setRetryTid(-1); } else { // Still blocked! ++lsqCacheBlocked; diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 9b1034577..8978fef02 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -73,6 +73,7 @@ BaseCache::CachePort::recvTiming(Packet *pkt) { if (blocked) { + DPRINTF(Cache,"Scheduling a retry while blocked\n"); mustSendRetry = true; return false; } @@ -92,20 +93,62 @@ BaseCache::CachePort::recvFunctional(Packet *pkt) } void +BaseCache::CachePort::recvRetry() +{ + Packet *pkt; + + if (!isCpuSide) + { + pkt = cache->getPacket(); + bool success = sendTiming(pkt); + DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + pkt->getAddr(), success ? "succesful" : "unsuccesful"); + cache->sendResult(pkt, success); + if (success && cache->doMasterRequest()) + { + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + reqCpu->schedule(curTick + 1); + } + } + else + { + pkt = cache->getCoherencePacket(); + bool success = sendTiming(pkt); + if (success && cache->doSlaveRequest()) + { + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + reqCpu->schedule(curTick + 1); + } + + } + return; +} +void BaseCache::CachePort::setBlocked() { + assert(!blocked); + DPRINTF(Cache, "Cache Blocking\n"); blocked = true; + //Clear the retry flag + mustSendRetry = false; } void BaseCache::CachePort::clearBlocked() { + assert(blocked); + DPRINTF(Cache, "Cache Unblocking\n"); + blocked = false; if (mustSendRetry) { + DPRINTF(Cache, "Cache Sending Retry\n"); mustSendRetry = false; sendRetry(); } - blocked = false; } BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort) @@ -128,6 +171,7 @@ BaseCache::CacheEvent::process() { if (!cachePort->isCpuSide) { + //MSHR pkt = cachePort->cache->getPacket(); bool success = cachePort->sendTiming(pkt); DPRINTF(Cache, "Address %x was %s in sending the timing request\n", @@ -142,11 +186,19 @@ BaseCache::CacheEvent::process() } else { + //CSHR pkt = cachePort->cache->getCoherencePacket(); - cachePort->sendTiming(pkt); + bool success = cachePort->sendTiming(pkt); + if (success && cachePort->cache->doSlaveRequest()) + { + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + this->schedule(curTick+1); + } } return; } + //Response //Know the packet to send, no need to mark in service (must succed) bool success = cachePort->sendTiming(pkt); assert(success); diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 9fb790cee..069dbab58 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -98,6 +98,8 @@ class BaseCache : public MemObject virtual int deviceBlockSize(); + virtual void recvRetry(); + public: void setBlocked(); @@ -407,17 +409,23 @@ class BaseCache : public MemObject void clearBlocked(BlockedCause cause) { uint8_t flag = 1 << cause; - blocked &= ~flag; - blockedSnoop &= ~flag; DPRINTF(Cache,"Unblocking for cause %s, causes left=%i\n", cause, blocked); - if (!isBlocked()) { - blocked_cycles[cause] += curTick - blockedCycle; - DPRINTF(Cache,"Unblocking from all causes\n"); - cpuSidePort->clearBlocked(); + if (blocked & flag) + { + blocked &= ~flag; + if (!isBlocked()) { + blocked_cycles[cause] += curTick - blockedCycle; + DPRINTF(Cache,"Unblocking from all causes\n"); + cpuSidePort->clearBlocked(); + } } - if (!isBlockedForSnoop()) { - memSidePort->clearBlocked(); + if (blockedSnoop & flag) + { + blockedSnoop &= ~flag; + if (!isBlockedForSnoop()) { + memSidePort->clearBlocked(); + } } } diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 9e961b0dc..c8b0cdaed 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -217,7 +217,7 @@ class Packet bool isRequest() { return (cmd & IsRequest) != 0; } bool isResponse() { return (cmd & IsResponse) != 0; } bool needsResponse() { return (cmd & NeedsResponse) != 0; } - bool isInvalidate() { return (cmd * IsInvalidate) != 0; } + bool isInvalidate() { return (cmd & IsInvalidate) != 0; } bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; } bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; } diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 7906156a2..01458aeb4 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -49,5 +49,5 @@ class BaseCPU(SimObject): self.toL2Bus = Bus() self.connectMemPorts(self.toL2Bus) self.l2cache = l2c - self.l2cache.cpu_side = toL2Bus.port + self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] diff --git a/tests/SConscript b/tests/SConscript index 8720939de..5aa507285 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -61,10 +61,12 @@ def check_test(target, source, env): # Exclude m5stats.txt since we will use diff-out on that. Execute(env.subst('diff -ubr ${SOURCES[0].dir} ${SOURCES[1].dir} ' + '-I "^command line:" ' + # for stdout file - '-I "^M5 compiled on" ' + # for stderr file - '-I "^M5 simulation started" ' + # for stderr file + '-I "^M5 compiled " ' + # for stderr file + '-I "^M5 started " ' + # for stderr file + '-I "^M5 executing on " ' + # for stderr file '-I "^Simulation complete at" ' + # for stderr file '-I "^Listening for" ' + # for stderr file + '-I "listening for remote gdb" ' + # for stderr file '--exclude=m5stats.txt --exclude=SCCS ' + '--exclude=${TARGETS[0].file} ' + '> ${TARGETS[0]}', target=target, source=source), None) diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 823a8aec1..8be0c0b3b 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -37,8 +37,8 @@ class MyCache(BaseCache): tgts_per_mshr = 5 cpu = TimingSimpleCPU() -cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) +#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), +# MyCache(size = '2MB')) system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..9a2f2a6cd --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +system=system +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..995699bf8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..fda0cd849 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 57948 # Simulator instruction rate (inst/s) +host_mem_usage 146660 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 73225 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2578 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 3287 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 2578 # Number of instructions executed +system.cpu.num_refs 710 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..c2154cff2 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..a1978675e --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 16 2006 17:47:32 +M5 started Wed Aug 16 18:40:03 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Exiting @ tick 3287 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini new file mode 100644 index 000000000..904e1a3b6 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -0,0 +1,97 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out new file mode 100644 index 000000000..5c623b6e7 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 5659ba97e..d3be9a857 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 6870 # Simulator instruction rate (inst/s) +host_inst_rate 199422 # Simulator instruction rate (inst/s) host_mem_usage 147292 # Number of bytes of host memory used -host_seconds 0.82 # Real time elapsed on the host -host_tick_rate 6865 # Simulator tick rate (ticks/s) +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 196594 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 9414b5014..bce6a498b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:10:25 -M5 started Wed Aug 16 14:41:57 2006 +M5 compiled Aug 16 2006 18:15:37 +M5 started Wed Aug 16 18:33:21 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/test/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini new file mode 100644 index 000000000..7254a0d48 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -0,0 +1,95 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +system=system +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out new file mode 100644 index 000000000..8d928077e --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/mips/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..a058b5e6e --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 45259 # Simulator instruction rate (inst/s) +host_mem_usage 147292 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 61490 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5657 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 7711 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 5657 # Number of instructions executed +system.cpu.num_refs 2055 # Number of memory references +system.cpu.workload.PROG:num_syscalls 13 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr new file mode 100644 index 000000000..f33d007a7 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stderr @@ -0,0 +1,2 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout new file mode 100644 index 000000000..177c64d91 --- /dev/null +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello World! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Aug 16 2006 18:15:37 +M5 started Wed Aug 16 18:40:06 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/test/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +Exiting @ tick 7711 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini new file mode 100644 index 000000000..039e9a8f2 --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -0,0 +1,97 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=workload +clock=1 +defer_registration=false +function_trace=false +function_trace_start=0 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.physmem +simulate_stalls=false +system=system +width=1 +workload=system.cpu.workload + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/sparc/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out new file mode 100644 index 000000000..2e6016beb --- /dev/null +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -0,0 +1,93 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +// range not specified +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/sparc/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu] +type=AtomicSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +mem=system.physmem +system=system +workload=system.cpu.workload +clock=1 +defer_registration=false +width=1 +function_trace=false +function_trace_start=0 +simulate_stalls=false + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 27de77ab6..98ff86bd8 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3565 # Simulator instruction rate (inst/s) -host_mem_usage 147204 # Number of bytes of host memory used -host_seconds 1.25 # Real time elapsed on the host -host_tick_rate 3564 # Simulator tick rate (ticks/s) +host_inst_rate 94707 # Simulator instruction rate (inst/s) +host_mem_usage 147208 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 93873 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4450 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 6c17750cc..84a06356a 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:15:12 -M5 started Wed Aug 16 14:42:01 2006 +M5 compiled Aug 16 2006 18:18:07 +M5 started Wed Aug 16 18:32:47 2006 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/test/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Exiting @ tick 4449 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index c4c381b93..5a34fde5e 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -48,13 +48,13 @@ text_file=m5stats.txt [system] type=System -children=cpu physmem workload +children=cpu membus physmem mem_mode=atomic physmem=system.physmem [system.cpu] type=TimingSimpleCPU -children=mem +children=workload clock=1 defer_registration=false function_trace=false @@ -63,11 +63,18 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.mem +mem=system.physmem system=system -workload=system.workload +workload=system.cpu.workload -[system.cpu.mem] +[system.cpu.workload] +type=EioProcess +chkpt= +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz +output=cout +system=system + +[system.membus] type=Bus bus_id=0 @@ -76,13 +83,6 @@ type=PhysicalMemory file= latency=1 -[system.workload] -type=EioProcess -chkpt= -file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz -output=cout -system=system - [trace] bufsize=0 dump_on_exit=false diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index 882db9c06..7032b9607 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -16,26 +16,26 @@ type=System physmem=system.physmem mem_mode=atomic -[system.workload] +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] type=EioProcess -file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz +file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz chkpt= output=cout system=system -[system.cpu.mem] -type=Bus -bus_id=0 - [system.cpu] type=TimingSimpleCPU max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -mem=system.cpu.mem +mem=system.physmem system=system -workload=system.workload +workload=system.cpu.workload clock=1 defer_registration=false // width not specified @@ -81,6 +81,7 @@ print_data=true print_iregs=false print_fetchseq=false print_cpseq=false +print_reg_delta=false pc_symbol=true intel_format=false trace_system=client diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 5f7766bac..51ee5923a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 781730 # Simulator instruction rate (inst/s) -host_mem_usage 147616 # Number of bytes of host memory used -host_seconds 0.64 # Real time elapsed on the host -host_tick_rate 1063244 # Simulator tick rate (ticks/s) +host_inst_rate 833953 # Simulator instruction rate (inst/s) +host_mem_usage 146496 # Number of bytes of host memory used +host_seconds 0.60 # Real time elapsed on the host +host_tick_rate 1134676 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -13,6 +13,6 @@ system.cpu.not_idle_fraction 1 # Pe system.cpu.numCycles 0 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references -system.workload.PROG:num_syscalls 18 # Number of system calls +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr index 6f99fb456..4e444fa6b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr @@ -1,11 +1,3 @@ -Traceback (most recent call last): - File "<string>", line 1, in ? - File "build/ALPHA_SE/python/m5/main.py", line 314, in main - execfile(sys.argv[0], scope) - File "tests/run.py", line 18, in ? - execfile(os.path.join(tests_root, 'configs', config + '.py')) - File "tests/configs/simple-timing.py", line 13, in ? - MyCache(size = '2MB')) - File "build/ALPHA_SE/python/m5/objects/BaseCPU.py", line 52, in addTwoLevelCacheHierarchy - self.l2cache.cpu_side = toL2Bus.port -NameError: global name 'toL2Bus' is not defined +warn: Entering event queue @ 0. Starting simulation... + +gzip: stdout: Broken pipe diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index bb29247b4..2157d4af6 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -1,11 +1,14 @@ -M5 Simulator System +main dictionary has 1245 entries +49508 bytes wasted +>M5 Simulator System Copyright (c) 2001-2006 The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 16 2006 13:05:10 -M5 started Wed Aug 16 14:41:54 2006 +M5 compiled Aug 16 2006 17:47:32 +M5 started Wed Aug 16 18:40:03 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Exiting @ tick 680774 because a thread reached the max instruction count |