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-rw-r--r--src/arch/mips/isa/decoder.isa3
-rw-r--r--src/arch/mips/isa/formats/mem.isa71
-rw-r--r--src/arch/mips/isa/formats/util.isa6
-rw-r--r--src/base/traceflags.py276
-rw-r--r--src/cpu/exetrace.cc181
-rw-r--r--src/cpu/exetrace.hh45
-rw-r--r--src/dev/alpha/tsunamireg.h21
-rw-r--r--src/dev/platform.hh3
-rw-r--r--src/dev/simconsole.cc7
-rw-r--r--src/dev/uart.cc1
-rw-r--r--src/dev/uart8250.hh13
-rw-r--r--src/python/SConscript1
-rw-r--r--src/python/m5/main.py92
-rw-r--r--src/python/m5/objects/Root.py2
-rw-r--r--src/python/m5/objects/T1000.py5
15 files changed, 347 insertions, 380 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 99c9e1604..3a8688797 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -1093,6 +1093,9 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
{{ uint64_t tmp = write_result;
Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
+ if (tmp == 1) {
+ xc->setStCondFailures(0);
+ }
}}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
format StoreMemory {
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index fccda2775..df80e7a1f 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -325,6 +325,41 @@ def template StoreMemAccExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ EA = xc->getEA();
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondMemAccExecute {{
+ Fault
+ %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -361,6 +396,40 @@ def template StoreExecute {{
{
Addr EA;
Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreCondExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
uint64_t write_result = 0;
%(fp_enable_check)s;
@@ -449,7 +518,7 @@ def template StoreCondCompleteAcc {{
%(fp_enable_check)s;
%(op_dest_decl)s;
- uint64_t write_result = pkt->req->getScResult();
+ uint64_t write_result = pkt->req->getExtraData();
if (fault == NoFault) {
%(postacc_code)s;
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index ec524113d..884e6f727 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -66,10 +66,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# select templates
- # define aliases... most StoreCond templates are the same as the
- # corresponding Store templates (only CompleteAcc is different).
- StoreCondMemAccExecute = StoreMemAccExecute
- StoreCondExecute = StoreExecute
+ # The InitiateAcc template is the same for StoreCond templates as the
+ # corresponding Store template..
StoreCondInitiateAcc = StoreInitiateAcc
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 800c24dee..897bf0023 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -29,19 +29,7 @@
# Authors: Nathan Binkert
# Steve Reinhardt
-#
-# This file generates the header and source files for the flags
-# that control the tracing facility.
-#
-
-import sys
-
-if len(sys.argv) != 2:
- print "%s: Need argument (basename of cc/hh files)" % sys.argv[0]
- sys.exit(1)
-
-hhfilename = sys.argv[1] + '.hh'
-ccfilename = sys.argv[1] + '.cc'
+__all__ = [ 'allFlags', 'baseFlags', 'compoundFlagsMap', 'compoundFlags' ]
#
# The list of trace flags that can be used to condition DPRINTFs etc.
@@ -89,6 +77,20 @@ baseFlags = [
'EthernetPIO',
'EthernetSM',
'Event',
+ 'ExecEnable',
+ 'ExecCPSeq',
+ 'ExecEffAddr',
+ 'ExecFetchSeq',
+ 'ExecIntRegs',
+ 'ExecIntel',
+ 'ExecLegion',
+ 'ExecOpClass',
+ 'ExecRegDelta',
+ 'ExecResult',
+ 'ExecSpeculative',
+ 'ExecSymbol',
+ 'ExecThread',
+ 'ExecTicks',
'FE',
'Fault',
'Fetch',
@@ -114,7 +116,6 @@ baseFlags = [
'ISP',
'IdeCtrl',
'IdeDisk',
- 'InstExec',
'Interrupt',
'LLSC',
'LSQ',
@@ -185,6 +186,9 @@ compoundFlagMap = {
'EthernetSM', 'EthernetCksum' ],
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
+ 'Exec' : [ 'ExecEnable', 'ExecTicks', 'ExecOpClass',
+ 'ExecThread', 'ExecEffAddr', 'ExecResult',
+ 'ExecSymbol' ],
'GDBAll' : [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend',
'GDBRecv', 'GDBExtra' ],
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
@@ -196,100 +200,98 @@ compoundFlagMap = {
'ScsiAll' : [ 'ScsiDisk', 'ScsiCtrl', 'ScsiNone' ]
}
-#############################################################
-#
-# Everything below this point generates the appropriate C++
-# declarations and definitions for the trace flags. If you are simply
-# adding or modifying flag definitions, you should not have to change
-# anything below.
-#
-
-import sys
-
# extract just the compound flag names into a list
compoundFlags = []
compoundFlags.extend(compoundFlagMap.keys())
compoundFlags.sort()
-#
-# First generate the header file. This defines the Flag enum
-# and some extern declarations for the .cc file.
-#
-try:
- hhfile = file(hhfilename, 'w')
-except IOError, e:
- sys.exit("can't open %s: %s" % (hhfilename, e))
-
-# file header boilerplate
-print >>hhfile, '''
-/*
- * DO NOT EDIT THIS FILE!
- *
- * Automatically generated from traceflags.py
- */
+allFlags = frozenset(baseFlags + compoundFlags)
-#ifndef __BASE_TRACE_FLAGS_HH__
-#define __BASE_TRACE_FLAGS_HH__
-
-namespace Trace {
-
-enum Flags {
-''',
-
-# Generate the enum. Base flags come first, then compound flags.
-idx = 0
-for flag in baseFlags:
- print >>hhfile, ' %s = %d,' % (flag, idx)
- idx += 1
-
-numBaseFlags = idx
-print >>hhfile, ' NumFlags = %d,' % idx
-
-# put a comment in here to separate base from compound flags
-print >>hhfile, '''
- // The remaining enum values are *not* valid indices for Trace::flags.
- // They are "compound" flags, which correspond to sets of base
- // flags, and are used only by TraceParamContext::setFlags().
-''',
-
-for flag in compoundFlags:
- print >>hhfile, ' %s = %d,' % (flag, idx)
- idx += 1
-
-numCompoundFlags = idx - numBaseFlags
-print >>hhfile, ' NumCompoundFlags = %d' % numCompoundFlags
-
-# trailer boilerplate
-print >>hhfile, '''\
-}; // enum Flags
-
-// Array of strings for SimpleEnumParam
-extern const char *flagStrings[];
-extern const int numFlagStrings;
-
-// Array of arraay pointers: for each compound flag, gives the list of
-// base flags to set. Inidividual flag arrays are terminated by -1.
-extern const Flags *compoundFlags[];
-
-/* namespace Trace */ }
-
-#endif // __BASE_TRACE_FLAGS_HH__
-''',
-
-hhfile.close()
-
-#
-#
-# Print out .cc file with array definitions.
+#############################################################
#
+# Everything below this point generates the appropriate C++
+# declarations and definitions for the trace flags. If you are simply
+# adding or modifying flag definitions, you should not have to change
+# anything below.
#
-try:
- ccfile = file(ccfilename, 'w')
-except OSError, e:
- sys.exit("can't open %s: %s" % (ccfilename, e))
-
-# file header
-print >>ccfile, '''
+def gen_hh(filename):
+ #
+ # First generate the header file. This defines the Flag enum
+ # and some extern declarations for the .cc file.
+ #
+ try:
+ hhfile = file(filename, 'w')
+ except IOError, e:
+ sys.exit("can't open %s: %s" % (hhfilename, e))
+
+ # file header boilerplate
+ print >>hhfile, '''
+ /*
+ * DO NOT EDIT THIS FILE!
+ *
+ * Automatically generated from traceflags.py
+ */
+
+ #ifndef __BASE_TRACE_FLAGS_HH__
+ #define __BASE_TRACE_FLAGS_HH__
+
+ namespace Trace {
+
+ enum Flags {
+ ''',
+
+ # Generate the enum. Base flags come first, then compound flags.
+ idx = 0
+ for flag in baseFlags:
+ print >>hhfile, ' %s = %d,' % (flag, idx)
+ idx += 1
+
+ numBaseFlags = idx
+ print >>hhfile, ' NumFlags = %d,' % idx
+
+ # put a comment in here to separate base from compound flags
+ print >>hhfile, '''
+ // The remaining enum values are *not* valid indices for Trace::flags.
+ // They are "compound" flags, which correspond to sets of base
+ // flags, and are used only by TraceParamContext::setFlags().
+ ''',
+
+ for flag in compoundFlags:
+ print >>hhfile, ' %s = %d,' % (flag, idx)
+ idx += 1
+
+ numCompoundFlags = idx - numBaseFlags
+ print >>hhfile, ' NumCompoundFlags = %d' % numCompoundFlags
+
+ # trailer boilerplate
+ print >>hhfile, '''\
+ }; // enum Flags
+
+ // Array of strings for SimpleEnumParam
+ extern const char *flagStrings[];
+ extern const int numFlagStrings;
+
+ // Array of arraay pointers: for each compound flag, gives the list of
+ // base flags to set. Inidividual flag arrays are terminated by -1.
+ extern const Flags *compoundFlags[];
+
+ /* namespace Trace */ }
+
+ #endif // __BASE_TRACE_FLAGS_HH__
+ \n''',
+
+ hhfile.close()
+
+def gen_cc(filename):
+ '''Print out .cc file with array definitions.'''
+
+ try:
+ ccfile = file(filename, 'w')
+ except OSError, e:
+ sys.exit("can't open %s: %s" % (ccfilename, e))
+
+ # file header
+ print >>ccfile, '''
/*
* DO NOT EDIT THIS FILE!
*
@@ -304,45 +306,57 @@ const char *Trace::flagStrings[] =
{
''',
-# The string array is used by SimpleEnumParam to map the strings
-# provided by the user to enum values.
-for flag in baseFlags:
- print >>ccfile, ' "%s",' % flag
+ # The string array is used by SimpleEnumParam to map the strings
+ # provided by the user to enum values.
+ for flag in baseFlags:
+ print >>ccfile, ' "%s",' % flag
-for flag in compoundFlags:
- print >>ccfile, ' "%s",' % flag
+ for flag in compoundFlags:
+ print >>ccfile, ' "%s",' % flag
-print >>ccfile, '};\n'
+ print >>ccfile, '};\n'
-numFlagStrings = len(baseFlags) + len(compoundFlags);
+ numFlagStrings = len(baseFlags) + len(compoundFlags);
-print >>ccfile, 'const int Trace::numFlagStrings = %d;' % numFlagStrings
-print >>ccfile
+ print >>ccfile, 'const int Trace::numFlagStrings = %d;' % numFlagStrings
+ print >>ccfile
-#
-# Now define the individual compound flag arrays. There is an array
-# for each compound flag listing the component base flags.
-#
+ #
+ # Now define the individual compound flag arrays. There is an array
+ # for each compound flag listing the component base flags.
+ #
-for flag in compoundFlags:
- flags = compoundFlagMap[flag]
- flags.append('(Flags)-1')
- print >>ccfile, 'static const Flags %sMap[] =' % flag
- print >>ccfile, '{ %s };' % (', '.join(flags))
- print >>ccfile
+ for flag in compoundFlags:
+ flags = compoundFlagMap[flag]
+ flags.append('(Flags)-1')
+ print >>ccfile, 'static const Flags %sMap[] =' % flag
+ print >>ccfile, '{ %s };' % (', '.join(flags))
+ print >>ccfile
-#
-# Finally the compoundFlags[] array maps the compound flags
-# to their individual arrays/
-#
-print >>ccfile, 'const Flags *Trace::compoundFlags[] ='
-print >>ccfile, '{'
+ #
+ # Finally the compoundFlags[] array maps the compound flags
+ # to their individual arrays/
+ #
+ print >>ccfile, 'const Flags *Trace::compoundFlags[] ='
+ print >>ccfile, '{'
+
+ for flag in compoundFlags:
+ print >>ccfile, ' %sMap,' % flag
+
+ # file trailer
+ print >>ccfile, '};'
+
+ ccfile.close()
-for flag in compoundFlags:
- print >>ccfile, ' %sMap,' % flag
+if __name__ == '__main__':
+ # This file generates the header and source files for the flags
+ # that control the tracing facility.
-# file trailer
-print >>ccfile, '};'
+ import sys
-ccfile.close()
+ if len(sys.argv) != 2:
+ print "%s: Need argument (basename of cc/hh files)" % sys.argv[0]
+ sys.exit(1)
+ gen_hh(sys.argv[1] + '.hh')
+ gen_cc(sys.argv[1] + '.cc')
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 683cb138e..c4d3ae505 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -64,6 +64,27 @@ static bool wasMicro = false;
namespace Trace {
SharedData *shared_data = NULL;
+
+void
+setupSharedData()
+{
+ int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
+ if (shmfd < 0)
+ fatal("Couldn't get shared memory fd. Is Legion running?");
+
+ shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
+ if (shared_data == (SharedData*)-1)
+ fatal("Couldn't allocate shared memory");
+
+ if (shared_data->flags != OWN_M5)
+ fatal("Shared memory has invalid owner");
+
+ if (shared_data->version != VERSION)
+ fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
+ shared_data->version);
+
+ // step legion forward one cycle so we can get register values
+ shared_data->flags = OWN_LEGION;
}
////////////////////////////////////////////////////////////////////////
@@ -128,7 +149,7 @@ Trace::InstRecord::dump()
ostream &outs = Trace::output();
DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
- if (flags[PRINT_REG_DELTA])
+ if (IsOn(ExecRegDelta))
{
#if THE_ISA == SPARC_ISA
//Don't print what happens for each micro-op, just print out
@@ -189,34 +210,25 @@ Trace::InstRecord::dump()
}
#endif
}
- else if (flags[INTEL_FORMAT]) {
-#if FULL_SYSTEM
- bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
-#else
- bool is_trace_system = true;
-#endif
- if (is_trace_system) {
- ccprintf(outs, "%7d ) ", when);
- outs << "0x" << hex << PC << ":\t";
- if (staticInst->isLoad()) {
- outs << "<RD 0x" << hex << addr;
- outs << ">";
- } else if (staticInst->isStore()) {
- outs << "<WR 0x" << hex << addr;
- outs << ">";
- }
- outs << endl;
+ else if (IsOn(ExecIntel)) {
+ ccprintf(outs, "%7d ) ", when);
+ outs << "0x" << hex << PC << ":\t";
+ if (staticInst->isLoad()) {
+ ccprintf(outs, "<RD %#x>", addr);
+ } else if (staticInst->isStore()) {
+ ccprintf(outs, "<WR %#x>", addr);
}
+ outs << endl;
} else {
- if (flags[PRINT_TICKS])
+ if (IsOn(ExecTicks))
ccprintf(outs, "%7d: ", when);
outs << thread->getCpuPtr()->name() << " ";
- if (flags[TRACE_MISSPEC])
+ if (IsOn(ExecSpeculative))
outs << (misspeculating ? "-" : "+") << " ";
- if (flags[PRINT_THREAD_NUM])
+ if (IsOn(ExecThread))
outs << "T" << thread->getThreadNum() << " : ";
@@ -224,7 +236,7 @@ Trace::InstRecord::dump()
Addr sym_addr;
if (debugSymbolTable
&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
- && flags[PC_SYMBOL]) {
+ && IsOn(ExecSymbol)) {
if (PC != sym_addr)
sym_str += csprintf("+%d", PC - sym_addr);
outs << "@" << sym_str << " : ";
@@ -250,11 +262,11 @@ Trace::InstRecord::dump()
outs << " : ";
- if (flags[PRINT_OP_CLASS]) {
+ if (IsOn(ExecOpClass)) {
outs << opClassStrings[staticInst->opClass()] << " : ";
}
- if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
+ if (IsOn(ExecResult) && data_status != DataInvalid) {
outs << " D=";
#if 0
if (data_status == DataDouble)
@@ -266,10 +278,10 @@ Trace::InstRecord::dump()
#endif
}
- if (flags[PRINT_EFF_ADDR] && addr_valid)
+ if (IsOn(ExecEffAddr) && addr_valid)
outs << " A=0x" << hex << addr;
- if (flags[PRINT_INT_REGS] && regs_valid) {
+ if (IsOn(ExecIntRegs) && regs_valid) {
for (int i = 0; i < TheISA::NumIntRegs;)
for (int j = i + 1; i <= j; i++)
ccprintf(outs, "r%02d = %#018x%s", i,
@@ -278,10 +290,10 @@ Trace::InstRecord::dump()
outs << "\n";
}
- if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
+ if (IsOn(ExecFetchSeq) && fetch_seq_valid)
outs << " FetchSeq=" << dec << fetch_seq;
- if (flags[PRINT_CP_SEQ] && cp_seq_valid)
+ if (IsOn(ExecCPSeq) && cp_seq_valid)
outs << " CPSeq=" << dec << cp_seq;
//
@@ -291,7 +303,7 @@ Trace::InstRecord::dump()
}
#if THE_ISA == SPARC_ISA && FULL_SYSTEM
// Compare
- if (flags[LEGION_LOCKSTEP])
+ if (IsOn(ExecLegion))
{
bool compared = false;
bool diffPC = false;
@@ -323,6 +335,9 @@ Trace::InstRecord::dump()
bool diffTlb = false;
Addr m5Pc, lgnPc;
+ if (!shared_data)
+ setupSharedData();
+
// We took a trap on a micro-op...
if (wasMicro && !staticInst->isMicroOp())
{
@@ -686,110 +701,4 @@ Trace::InstRecord::dump()
#endif
}
-
-vector<bool> Trace::InstRecord::flags(NUM_BITS);
-string Trace::InstRecord::trace_system;
-
-////////////////////////////////////////////////////////////////////////
-//
-// Parameter space for per-cycle execution address tracing options.
-// Derive from ParamContext so we can override checkParams() function.
-//
-class ExecutionTraceParamContext : public ParamContext
-{
- public:
- ExecutionTraceParamContext(const string &_iniSection)
- : ParamContext(_iniSection)
- {
- }
-
- void checkParams(); // defined at bottom of file
-};
-
-ExecutionTraceParamContext exeTraceParams("exetrace");
-
-Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
- "capture speculative instructions", true);
-
-Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
- "print cycle number", true);
-Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
- "print op class", true);
-Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
- "print thread number", true);
-Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
- "print effective address", true);
-Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
- "print result data", true);
-Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
- "print all integer regs", false);
-Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
- "print fetch sequence number", false);
-Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
- "print correct-path sequence number", false);
-Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
- "print which registers changed to what", false);
-Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
- "Use symbols for the PC if available", true);
-Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
- "print trace in intel compatible format", false);
-Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
- "Compare sim state to legion state every cycle",
- false);
-Param<string> exe_trace_system(&exeTraceParams, "trace_system",
- "print trace of which system (client or server)",
- "client");
-
-
-//
-// Helper function for ExecutionTraceParamContext::checkParams() just
-// to get us into the InstRecord namespace
-//
-void
-Trace::InstRecord::setParams()
-{
- flags[TRACE_MISSPEC] = exe_trace_spec;
-
- flags[PRINT_TICKS] = exe_trace_print_cycle;
- flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
- flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
- flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
- flags[PRINT_EFF_ADDR] = exe_trace_print_data;
- flags[PRINT_INT_REGS] = exe_trace_print_iregs;
- flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
- flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
- flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
- flags[PC_SYMBOL] = exe_trace_pc_symbol;
- flags[INTEL_FORMAT] = exe_trace_intel_format;
- flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep;
- trace_system = exe_trace_system;
-
- // If were going to be in lockstep with Legion
- // Setup shared memory, and get otherwise ready
- if (flags[LEGION_LOCKSTEP]) {
- int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
- if (shmfd < 0)
- fatal("Couldn't get shared memory fd. Is Legion running?");
-
- shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
- if (shared_data == (SharedData*)-1)
- fatal("Couldn't allocate shared memory");
-
- if (shared_data->flags != OWN_M5)
- fatal("Shared memory has invalid owner");
-
- if (shared_data->version != VERSION)
- fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
- shared_data->version);
-
- // step legion forward one cycle so we can get register values
- shared_data->flags = OWN_LEGION;
- }
-}
-
-void
-ExecutionTraceParamContext::checkParams()
-{
- Trace::InstRecord::setParams();
-}
-
+/* namespace Trace */ }
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 95a142f3c..be10b4a6a 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -137,30 +137,6 @@ class InstRecord
void setRegs(const IntRegFile &regs);
void dump();
-
- enum InstExecFlagBits {
- TRACE_MISSPEC = 0,
- PRINT_TICKS,
- PRINT_OP_CLASS,
- PRINT_THREAD_NUM,
- PRINT_RESULT_DATA,
- PRINT_EFF_ADDR,
- PRINT_INT_REGS,
- PRINT_FETCH_SEQ,
- PRINT_CP_SEQ,
- PRINT_REG_DELTA,
- PC_SYMBOL,
- INTEL_FORMAT,
- LEGION_LOCKSTEP,
- NUM_BITS
- };
-
- static std::vector<bool> flags;
- static std::string trace_system;
-
- static void setParams();
-
- static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
};
@@ -174,22 +150,19 @@ InstRecord::setRegs(const IntRegFile &regs)
regs_valid = true;
}
-inline
-InstRecord *
-getInstRecord(Tick when, ThreadContext *tc,
- const StaticInstPtr staticInst,
+inline InstRecord *
+getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
Addr pc)
{
- if (DTRACE(InstExec) &&
- (InstRecord::traceMisspec() || !tc->misspeculating())) {
- return new InstRecord(when, tc, staticInst, pc,
- tc->misspeculating());
- }
-
- return NULL;
-}
+ if (!IsOn(ExecEnable))
+ return NULL;
+ if (!IsOn(ExecSpeculative) && tc->misspeculating())
+ return NULL;
+ return new InstRecord(when, tc, staticInst, pc, tc->misspeculating());
}
+/* namespace Trace */ }
+
#endif // __EXETRACE_HH__
diff --git a/src/dev/alpha/tsunamireg.h b/src/dev/alpha/tsunamireg.h
index d603972be..a2742e36d 100644
--- a/src/dev/alpha/tsunamireg.h
+++ b/src/dev/alpha/tsunamireg.h
@@ -136,15 +136,6 @@
/* Added for keyboard accesses */
#define TSDEV_KBD 0x64
-/* Added for ATA PCI DMA */
-#define ATA_PCI_DMA 0x00
-#define ATA_PCI_DMA2 0x02
-#define ATA_PCI_DMA3 0x16
-#define ATA_PCI_DMA4 0x17
-#define ATA_PCI_DMA5 0x1a
-#define ATA_PCI_DMA6 0x11
-#define ATA_PCI_DMA7 0x14
-
#define TSDEV_RTC_ADDR 0x70
#define TSDEV_RTC_DATA 0x71
@@ -155,18 +146,6 @@
#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
-// UART Defines
-#define UART_IER_RDI 0x01
-#define UART_IER_THRI 0x02
-#define UART_IER_RLSI 0x04
-
-
-#define UART_LSR_TEMT 0x40
-#define UART_LSR_THRE 0x20
-#define UART_LSR_DR 0x01
-
-#define UART_MCR_LOOP 0x10
-
// System Control PortB Status Bits
#define PORTB_SPKR_HIGH 0x20
diff --git a/src/dev/platform.hh b/src/dev/platform.hh
index 1940dcad6..aceec0970 100644
--- a/src/dev/platform.hh
+++ b/src/dev/platform.hh
@@ -55,9 +55,6 @@ class Platform : public SimObject
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
- /** Pointer to the UART, set by the uart */
- Uart *uart;
-
/** Pointer to the system for info about the memory system. */
System *system;
diff --git a/src/dev/simconsole.cc b/src/dev/simconsole.cc
index 77aafd9fa..903368491 100644
--- a/src/dev/simconsole.cc
+++ b/src/dev/simconsole.cc
@@ -364,7 +364,12 @@ ConsoleListener::listen(int port)
port++;
}
- ccprintf(cerr, "Listening for console connection on port %d\n", port);
+
+ int p1, p2;
+ p2 = name().rfind('.') - 1;
+ p1 = name().rfind('.', p2);
+ ccprintf(cerr, "Listening for %s connection on port %d\n",
+ name().substr(p1+1,p2-p1), port);
event = new Event(this, listener.getfd(), POLLIN);
pollQueue.schedule(event);
diff --git a/src/dev/uart.cc b/src/dev/uart.cc
index f769b720b..1c781f76d 100644
--- a/src/dev/uart.cc
+++ b/src/dev/uart.cc
@@ -47,7 +47,6 @@ Uart::Uart(Params *p)
// set back pointers
cons->uart = this;
- platform->uart = this;
}
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index a0620c7e0..c28200592 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -35,7 +35,6 @@
#ifndef __DEV_UART8250_HH__
#define __DEV_UART8250_HH__
-#include "dev/alpha/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
@@ -54,6 +53,18 @@ const uint8_t IIR_TXID = 0x02; /* Tx Data */
const uint8_t IIR_RXID = 0x04; /* Rx Data */
const uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/
+const uint8_t UART_IER_RDI = 0x01;
+const uint8_t UART_IER_THRI = 0x02;
+const uint8_t UART_IER_RLSI = 0x04;
+
+
+const uint8_t UART_LSR_TEMT = 0x40;
+const uint8_t UART_LSR_THRE = 0x20;
+const uint8_t UART_LSR_DR = 0x01;
+
+const uint8_t UART_MCR_LOOP = 0x10;
+
+
class SimConsole;
class Platform;
diff --git a/src/python/SConscript b/src/python/SConscript
index 61cab45f3..51271650f 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -97,6 +97,7 @@ addPkg('m5')
pyzip_files.append('m5/defines.py')
pyzip_files.append('m5/info.py')
pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py'))
+pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py'))
def swig_it(basename):
env.Command(['swig/%s_wrap.cc' % basename, 'm5/internal/%s.py' % basename],
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index d02bc466b..25b52e830 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -29,6 +29,7 @@
import code, optparse, os, socket, sys
from datetime import datetime
from attrdict import attrdict
+import traceflags
__all__ = [ 'options', 'arguments', 'main' ]
@@ -40,6 +41,19 @@ The Regents of The University of Michigan
All Rights Reserved
'''
+def print_list(items, indent=4):
+ line = ' ' * indent
+ for i,item in enumerate(items):
+ if len(line) + len(item) > 76:
+ print line
+ line = ' ' * indent
+
+ if i < len(items) - 1:
+ line += '%s, ' % item
+ else:
+ line += item
+ print line
+
# there's only one option parsing done, so make it global and add some
# helper functions to make it work well.
parser = optparse.OptionParser(usage=usage, version=version,
@@ -135,8 +149,10 @@ add_option("--debug-break", metavar="TIME[,TIME]", action='append', split=',',
# Tracing options
set_group("Trace Options")
+add_option("--trace-help", action='store_true',
+ help="Print help on trace flags")
add_option("--trace-flags", metavar="FLAG[,FLAG]", action='append', split=',',
- help="Sets the flags for tracing")
+ help="Sets the flags for tracing (-FLAG disables a flag)")
add_option("--trace-start", metavar="TIME", type='int',
help="Start tracing at TIME (must be in ticks)")
add_option("--trace-file", metavar="FILE", default="cout",
@@ -144,33 +160,6 @@ add_option("--trace-file", metavar="FILE", default="cout",
add_option("--trace-ignore", metavar="EXPR", action='append', split=':',
help="Ignore EXPR sim objects")
-# Execution Trace options
-set_group("Execution Trace Options")
-bool_option("speculative", default=True,
- help="Don't capture speculative instructions")
-bool_option("print-cycle", default=True,
- help="Don't print cycle numbers in trace output")
-bool_option("print-symbol", default=True,
- help="Disable PC symbols in trace output")
-bool_option("print-opclass", default=True,
- help="Don't print op class type in trace output")
-bool_option("print-thread", default=True,
- help="Don't print thread number in trace output")
-bool_option("print-effaddr", default=True,
- help="Don't print effective address in trace output")
-bool_option("print-data", default=True,
- help="Don't print result data in trace output")
-bool_option("print-iregs", default=False,
- help="Print fetch sequence numbers in trace output")
-bool_option("print-fetch-seq", default=False,
- help="Print fetch sequence numbers in trace output")
-bool_option("print-cpseq", default=False,
- help="Print correct path sequence numbers in trace output")
-#bool_option("print-reg-delta", default=False,
-# help="Print which registers changed to what in trace output")
-bool_option("legion-lock", default=False,
- help="Compare simulator state with Legion simulator every cycle")
-
options = attrdict()
arguments = []
@@ -231,6 +220,19 @@ def main():
print info.RELEASE_NOTES
print
+ if options.trace_help:
+ done = True
+ print "Base Flags:"
+ print_list(traceflags.baseFlags, indent=4)
+ print
+ print "Compound Flags:"
+ for flag in traceflags.compoundFlags:
+ if flag == 'All':
+ continue
+ print " %s:" % flag
+ print_list(traceflags.compoundFlagMap[flag], indent=8)
+ print
+
if done:
sys.exit(0)
@@ -250,6 +252,7 @@ def main():
if not arguments or not os.path.isfile(arguments[0]):
if arguments and not os.path.isfile(arguments[0]):
print "Script %s not found" % arguments[0]
+
usage(2)
# tell C++ about output directory
@@ -267,9 +270,28 @@ def main():
for when in options.debug_break:
internal.debug.schedBreakCycle(int(when))
+ on_flags = []
+ off_flags = []
for flag in options.trace_flags:
+ off = False
+ if flag.startswith('-'):
+ flag = flag[1:]
+ off = True
+ if flag not in traceflags.allFlags:
+ print >>sys.stderr, "invalid trace flag '%s'" % flag
+ sys.exit(1)
+
+ if off:
+ off_flags.append(flag)
+ else:
+ on_flags.append(flag)
+
+ for flag in on_flags:
internal.trace.set(flag)
+ for flag in off_flags:
+ internal.trace.clear(flag)
+
if options.trace_start is not None:
internal.trace.enabled = False
def enable_trace():
@@ -281,20 +303,6 @@ def main():
for ignore in options.trace_ignore:
internal.trace.ignore(ignore)
- # set execution trace options
- objects.ExecutionTrace.speculative = options.speculative
- objects.ExecutionTrace.print_cycle = options.print_cycle
- objects.ExecutionTrace.pc_symbol = options.print_symbol
- objects.ExecutionTrace.print_opclass = options.print_opclass
- objects.ExecutionTrace.print_thread = options.print_thread
- objects.ExecutionTrace.print_effaddr = options.print_effaddr
- objects.ExecutionTrace.print_data = options.print_data
- objects.ExecutionTrace.print_iregs = options.print_iregs
- objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
- objects.ExecutionTrace.print_cpseq = options.print_cpseq
- #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
- objects.ExecutionTrace.legion_lockstep = options.legion_lock
-
sys.argv = arguments
sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 81482c1de..c78ae6ccb 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -3,7 +3,6 @@ from m5.params import *
from Serialize import Serialize
from Serialize import Statreset
from Statistics import Statistics
-from ExeTrace import ExecutionTrace
class Root(SimObject):
type = 'Root'
@@ -16,5 +15,4 @@ class Root(SimObject):
# stats = Param.Statistics(Statistics(), "statistics object")
# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
stats = Statistics()
- exetrace = ExecutionTrace()
serialize = Serialize()
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 85c4db6df..3ab6d4283 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -69,16 +69,19 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
+ hconsole = SimConsole(listener = ConsoleListener())
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
+ pconsole = SimConsole(listener = ConsoleListener())
puart0 = Uart8250(pio_addr=0x1f10000000)
- console = SimConsole(listener = ConsoleListener())
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
+ self.hvuart.sim_console = self.hconsole
+ self.puart0.sim_console = self.pconsole
self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port
self.fake_iob.pio = bus.port
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-25 18:07:54 +0000