diff options
43 files changed, 1427 insertions, 1104 deletions
diff --git a/SConstruct b/SConstruct index 259b6c583..fd912fc03 100644 --- a/SConstruct +++ b/SConstruct @@ -302,6 +302,8 @@ sticky_opts.AddOptions( # Non-sticky options only apply to the current build. nonsticky_opts = Options(args=ARGUMENTS) nonsticky_opts.AddOptions( + ListOption('TEST_CPU_MODELS', 'CPU models to test if regression is being run', '', + env['ALL_CPU_LIST']), BoolOption('update_ref', 'Update test reference outputs', False) ) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py new file mode 100644 index 000000000..bf6817c7a --- /dev/null +++ b/configs/common/FSConfig.py @@ -0,0 +1,104 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +import m5 +from m5.objects import * +from FullO3Config import * +from SysPaths import * +from Util import * + +script.dir = '/z/saidi/work/m5.newmem/configs/boot' +linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img')) + +class CowIdeDisk(IdeDisk): + image = CowDiskImage(child=RawDiskImage(read_only=True), + read_only=False) + + def childImage(self, ci): + self.image.child.image_file = ci + +class BaseTsunami(Tsunami): + ethernet = NSGigE(configdata=NSGigEPciData(), + pci_bus=0, pci_dev=1, pci_func=0) + etherint = NSGigEInt(device=Parent.ethernet) + ide = IdeController(disks=[Parent.disk0, Parent.disk2], + pci_func=0, pci_dev=0, pci_bus=0) + +def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None): + self = LinuxAlphaSystem() + self.iobus = Bus(bus_id=0) + self.membus = Bus(bus_id=1) + self.bridge = Bridge() + self.physmem = PhysicalMemory(range = AddrRange('128MB')) + self.bridge.side_a = self.iobus.port + self.bridge.side_b = self.membus.port + self.physmem.port = self.membus.port + self.disk0 = CowIdeDisk(driveID='master') + self.disk2 = CowIdeDisk(driveID='master') + self.disk0.childImage(linux_image) + self.disk2.childImage(disk('linux-bigswap2.img')) + self.tsunami = BaseTsunami() + self.tsunami.attachIO(self.iobus) + self.tsunami.ide.pio = self.iobus.port + self.tsunami.ide.dma = self.iobus.port + self.tsunami.ide.config = self.iobus.port + self.tsunami.ethernet.pio = self.iobus.port + self.tsunami.ethernet.dma = self.iobus.port + self.tsunami.ethernet.config = self.iobus.port + self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image, + read_only = True)) + self.intrctrl = IntrControl() + self.cpu = cpu + self.mem_mode = mem_mode + connectCpu(self.cpu, self.membus, icache, dcache, l2cache) + for each_cpu in listWrapper(self.cpu): + each_cpu.itb = AlphaITB() + each_cpu.dtb = AlphaDTB() + self.cpu.clock = '2GHz' + self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) + self.kernel = binary('vmlinux') + self.pal = binary('ts_osfpal') + self.console = binary('console') + self.boot_osflags = 'root=/dev/hda1 console=ttyS0' + + return self + +class TsunamiRoot(Root): + pass + +def DualRoot(clientSystem, serverSystem): + self = Root() + self.client = clientSystem + self.server = serverSystem + + self.etherdump = EtherDump(file='ethertrace') + self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0], + int2 = Parent.server.tsunami.etherint[0], + dump = Parent.etherdump) + self.clock = '1THz' + return self diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py new file mode 100644 index 000000000..2070d11f8 --- /dev/null +++ b/configs/common/SysPaths.py @@ -0,0 +1,68 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +import os, sys +from os.path import isdir, join as joinpath +from os import environ as env + +def disk(file): + system() + return joinpath(disk.dir, file) + +def binary(file): + system() + return joinpath(binary.dir, file) + +def script(file): + system() + return joinpath(script.dir, file) + +def system(): + if not system.dir: + try: + path = env['M5_PATH'].split(':') + except KeyError: + path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ] + + for system.dir in path: + if os.path.isdir(system.dir): + break + else: + raise ImportError, "Can't find a path to system files." + + if not binary.dir: + binary.dir = joinpath(system.dir, 'binaries') + if not disk.dir: + disk.dir = joinpath(system.dir, 'disks') + if not script.dir: + script.dir = joinpath(system.dir, 'boot') + +system.dir = None +binary.dir = None +disk.dir = None +script.dir = None diff --git a/configs/test/SysPaths.py b/configs/test/SysPaths.py deleted file mode 100644 index 3f96a546f..000000000 --- a/configs/test/SysPaths.py +++ /dev/null @@ -1,40 +0,0 @@ -import os, sys -from os.path import isdir, join as joinpath -from os import environ as env - -def disk(file): - system() - return joinpath(disk.dir, file) - -def binary(file): - system() - return joinpath(binary.dir, file) - -def script(file): - system() - return joinpath(script.dir, file) - -def system(): - if not system.dir: - try: - path = env['M5_PATH'].split(':') - except KeyError: - path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ] - - for system.dir in path: - if os.path.isdir(system.dir): - break - else: - raise ImportError, "Can't find a path to system files." - - if not binary.dir: - binary.dir = joinpath(system.dir, 'binaries') - if not disk.dir: - disk.dir = joinpath(system.dir, 'disks') - if not script.dir: - script.dir = joinpath(system.dir, 'boot') - -system.dir = None -binary.dir = None -disk.dir = None -script.dir = None diff --git a/configs/test/fs.py b/configs/test/fs.py index f4c50fc23..004edda79 100644 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@ -2,14 +2,17 @@ import optparse, os, sys import m5 from m5.objects import * +m5.AddToPath('../common') +from FSConfig import * from SysPaths import * -from FullO3Config import * +from Util import * parser = optparse.OptionParser() parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-m", "--maxtick", type="int") +parser.add_option("--maxtime", type="float") parser.add_option("--dual", help="Run full system using dual systems", action="store_true") @@ -19,90 +22,27 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -# Base for tests is directory containing this file. -test_base = os.path.dirname(__file__) - -script.dir = '/z/saidi/work/m5.newmem/configs/boot' - -linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img')) - -class CowIdeDisk(IdeDisk): - image = CowDiskImage(child=RawDiskImage(read_only=True), - read_only=False) - - def childImage(self, ci): - self.image.child.image_file = ci - -class BaseTsunami(Tsunami): - ethernet = NSGigE(configdata=NSGigEPciData(), - pci_bus=0, pci_dev=1, pci_func=0) - etherint = NSGigEInt(device=Parent.ethernet) - ide = IdeController(disks=[Parent.disk0, Parent.disk2], - pci_func=0, pci_dev=0, pci_bus=0) - -class MyLinuxAlphaSystem(LinuxAlphaSystem): - iobus = Bus(bus_id=0) - membus = Bus(bus_id=1) - bridge = Bridge() - physmem = PhysicalMemory(range = AddrRange('128MB')) - bridge.side_a = iobus.port - bridge.side_b = membus.port - physmem.port = membus.port - disk0 = CowIdeDisk(driveID='master') - disk2 = CowIdeDisk(driveID='master') - disk0.childImage(linux_image) - disk2.childImage(disk('linux-bigswap2.img')) - tsunami = BaseTsunami() - tsunami.attachIO(iobus) - tsunami.ide.pio = iobus.port - tsunami.ide.dma = iobus.port - tsunami.ide.config = iobus.port - tsunami.ethernet.pio = iobus.port - tsunami.ethernet.dma = iobus.port - tsunami.ethernet.config = iobus.port - simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image, - read_only = True)) - intrctrl = IntrControl() - if options.detailed: - cpu = DetailedO3CPU() - elif options.timing: - cpu = TimingSimpleCPU() - mem_mode = 'timing' - else: - cpu = AtomicSimpleCPU() - cpu.mem = membus - cpu.icache_port = membus.port - cpu.dcache_port = membus.port - cpu.itb = AlphaITB() - cpu.dtb = AlphaDTB() - cpu.clock = '2GHz' - sim_console = SimConsole(listener=ConsoleListener(port=3456)) - kernel = binary('vmlinux') - pal = binary('ts_osfpal') - console = binary('console') - boot_osflags = 'root=/dev/hda1 console=ttyS0' - -class TsunamiRoot(Root): - pass - -def DualRoot(clientSystem, serverSystem): - self = Root() - self.client = clientSystem - self.server = serverSystem - - self.etherdump = EtherDump(file='ethertrace') - self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0], - int2 = Parent.server.tsunami.etherint[0], - dump = Parent.etherdump) - self.clock = '1THz' - return self +if options.detailed: + cpu = DetailedO3CPU() + cpu2 = DetailedO3CPU() + mem_mode = 'timing' +elif options.timing: + cpu = TimingSimpleCPU() + cpu2 = TimingSimpleCPU() + mem_mode = 'timing' +else: + cpu = AtomicSimpleCPU() + cpu2 = AtomicSimpleCPU() + mem_mode = 'atomic' if options.dual: root = DualRoot( - MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), - MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) + MyLinuxAlphaSystem(cpu, mem_mode, linux_image), + MyLinuxAlphaSystem(cpu2, mem_mode, linux_image)) + root.client.readfile = script('netperf-stream-nt-client.rcS') + root.server.readfile = script('netperf-server.rcS') else: - root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem()) + root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem(cpu, mem_mode, linux_image)) m5.instantiate(root) @@ -116,6 +56,10 @@ m5.instantiate(root) if options.maxtick: exit_event = m5.simulate(options.maxtick) +elif options.maxtime: + simtime = int(options.maxtime * root.clock.value) + print "simulating for: ", simtime + exit_event = m5.simulate(simtime) else: exit_event = m5.simulate() diff --git a/configs/test/hello_sparc b/configs/test/sparc_tests/hello_sparc Binary files differindex e254ae33f..e254ae33f 100755 --- a/configs/test/hello_sparc +++ b/configs/test/sparc_tests/hello_sparc diff --git a/configs/test/test.py b/configs/test/test.py index 3b637f70f..9d780547b 100644 --- a/configs/test/test.py +++ b/configs/test/test.py @@ -7,8 +7,28 @@ import m5 import os, optparse, sys m5.AddToPath('../common') from SEConfig import * +from FullO3Config import * from m5.objects import * +parser = optparse.OptionParser() + +parser.add_option("-c", "--cmd", default="hello", + help="The binary to run in syscall emulation mode.") +parser.add_option("-o", "--options", default="", + help="The options to pass to the binary, use \" \" around the entire\ + string.") +parser.add_option("-i", "--input", default="", + help="A file of input to give to the binary.") +parser.add_option("-d", "--detailed", action="store_true") +parser.add_option("-t", "--timing", action="store_true") +parser.add_option("-m", "--maxtick", type="int") + +(options, args) = parser.parse_args() + +if args: + print "Error: script doesn't take any positional arguments" + sys.exit(1) + this_dir = os.path.dirname(__file__) process = LiveProcess() @@ -37,7 +57,15 @@ if options.detailed: process += [smt_process, ] smt_idx += 1 -root = MySESystem(process) + +if options.timing: + cpu = TimingSimpleCPU() +elif options.detailed: + cpu = DetailedO3CPU() +else: + cpu = AtomicSimpleCPU() + +root = MySESystem(cpu, process) if options.timing or options.detailed: root.system.mem_mode = 'timing' diff --git a/src/SConscript b/src/SConscript index 10faf5aaf..812089a00 100644 --- a/src/SConscript +++ b/src/SConscript @@ -98,6 +98,7 @@ base_sources = Split(''' mem/packet.cc mem/physical.cc mem/port.cc + mem/tport.cc mem/cache/base_cache.cc mem/cache/cache.cc diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa index 02f7cf61a..b518265aa 100644 --- a/src/arch/sparc/isa/base.isa +++ b/src/arch/sparc/isa/base.isa @@ -86,6 +86,11 @@ output header {{ const SymbolTable *symtab) const; void printReg(std::ostream &os, int reg) const; + void printSrcReg(std::ostream &os, int reg) const; + void printDestReg(std::ostream &os, int reg) const; + + void printRegArray(std::ostream &os, + const RegIndex indexArray[], int num) const; }; bool passesCondition(uint32_t codes, uint32_t condition); @@ -150,6 +155,33 @@ output decoder {{ ccprintf(os, "\t%s ", mnemonic); } + void SparcStaticInst::printRegArray(std::ostream &os, + const RegIndex indexArray[], int num) const + { + if(num <= 0) + return; + printReg(os, indexArray[0]); + for(int x = 1; x < num; x++) + { + os << ", "; + printReg(os, indexArray[x]); + } + } + + void + SparcStaticInst::printSrcReg(std::ostream &os, int reg) const + { + if(_numSrcRegs > reg) + printReg(os, _srcRegIdx[reg]); + } + + void + SparcStaticInst::printDestReg(std::ostream &os, int reg) const + { + if(_numDestRegs > reg) + printReg(os, _destRegIdx[reg]); + } + void SparcStaticInst::printReg(std::ostream &os, int reg) const { diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index fa8832920..274d51fc5 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -39,30 +39,30 @@ decode OP default Unknown::unknown() { //Throw an illegal instruction acception 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); - 0x1: decode BPCC + format BranchN { - format Branch19 + 0x1: decode BPCC { - 0x0: bpcci({{ + 0x0: bpcci(19, {{ if(passesCondition(Ccr<3:0>, COND2)) NNPC = xc->readPC() + disp; else handle_annul }}); - 0x2: bpccx({{ + 0x2: bpccx(19, {{ if(passesCondition(Ccr<7:4>, COND2)) NNPC = xc->readPC() + disp; else handle_annul }}); } + 0x2: bicc(22, {{ + if(passesCondition(Ccr<3:0>, COND2)) + NNPC = xc->readPC() + disp; + else + handle_annul + }}); } - 0x2: Branch22::bicc({{ - if(passesCondition(Ccr<3:0>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); 0x3: decode RCOND2 { format BranchSplit @@ -110,7 +110,7 @@ decode OP default Unknown::unknown() 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); } - 0x1: Branch30::call({{ + 0x1: BranchN::call(30, {{ R15 = xc->readPC(); NNPC = R15 + disp; }}); @@ -134,7 +134,7 @@ decode OP default Unknown::unknown() Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; Y = Rd.sdw; }}); - 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}}); + 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 0x0D: udivx({{ if(Rs2_or_imm13 == 0) fault = new DivisionByZero; else Rd.udw = Rs1.udw / Rs2_or_imm13; @@ -208,7 +208,7 @@ decode OP default Unknown::unknown() 0x1C: subccc({{ int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = Ccr<0:0>; - Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, + Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, @@ -272,8 +272,9 @@ decode OP default Unknown::unknown() ); 0x22: taddcctv({{ int64_t resTemp, val2 = Rs2_or_imm13; - Rd = resTemp = Rs1 + val2; - int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); + Rd = Rs1 + val2; + int32_t overflow = Rs1<1:0> || val2<1:0> || + (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); if(overflow) fault = new TagOverflow;}}, {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, {{overflow}}, @@ -322,15 +323,21 @@ decode OP default Unknown::unknown() 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); } // XXX might want a format rdipr thing here - 0x28: rdasr({{ + 0x28: decode RS1 { + 0xF: decode I { + 0x0: Nop::stbar({{/*stuff*/}}); + 0x1: Nop::membar({{/*stuff*/}}); + } + default: rdasr({{ Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault); - }}); - 0x29: rdhpr({{ + }}); + } + 0x29: HPriv::rdhpr({{ // XXX Need to protect with format that traps non-priv/priv // access Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); }}); - 0x2A: rdpr({{ + 0x2A: Priv::rdpr({{ // XXX Need to protect with format that traps non-priv // access Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); @@ -397,18 +404,152 @@ decode OP default Unknown::unknown() 0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); } - 0x32: wrpr({{ + 0x32: Priv::wrpr({{ // XXX Need to protect with format that traps non-priv // access - xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); + fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); }}); - 0x33: wrhpr({{ + 0x33: HPriv::wrhpr({{ // XXX Need to protect with format that traps non-priv/priv // access - xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); + fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); }}); - 0x34: Trap::fpop1({{fault = new FpDisabled;}}); + 0x34: decode OPF{ + 0x01: Trap::fmovs({{fault = new FpDisabled;}}); + 0x02: Trap::fmovd({{fault = new FpDisabled;}}); + 0x03: Trap::fmovq({{fault = new FpDisabled;}}); + 0x05: Trap::fnegs({{fault = new FpDisabled;}}); + 0x06: Trap::fnegd({{fault = new FpDisabled;}}); + 0x07: Trap::fnegq({{fault = new FpDisabled;}}); + 0x09: Trap::fabss({{fault = new FpDisabled;}}); + 0x0A: Trap::fabsd({{fault = new FpDisabled;}}); + 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); + 0x29: Trap::fsqrts({{fault = new FpDisabled;}}); + 0x2A: Trap::fsqrtd({{fault = new FpDisabled;}}); + 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); + 0x41: Trap::fadds({{fault = new FpDisabled;}}); + 0x42: BasicOperate::faddd({{Frd = Frs1 + Frs2;}}); + 0x43: Trap::faddq({{fault = new FpDisabled;}}); + 0x45: Trap::fsubs({{fault = new FpDisabled;}}); + 0x46: Trap::fsubd({{fault = new FpDisabled;}}); + 0x47: Trap::fsubq({{fault = new FpDisabled;}}); + 0x49: Trap::fmuls({{fault = new FpDisabled;}}); + 0x4A: BasicOperate::fmuld({{Frd = Frs1.sf * Frs2.sf;}}); + 0x4B: Trap::fmulq({{fault = new FpDisabled;}}); + 0x4D: Trap::fdivs({{fault = new FpDisabled;}}); + 0x4E: Trap::fdivd({{fault = new FpDisabled;}}); + 0x4F: Trap::fdivq({{fault = new FpDisabled;}}); + 0x69: Trap::fsmuld({{fault = new FpDisabled;}}); + 0x6E: Trap::fdmulq({{fault = new FpDisabled;}}); + 0x81: Trap::fstox({{fault = new FpDisabled;}}); + 0x82: Trap::fdtox({{fault = new FpDisabled;}}); + 0x83: Trap::fqtox({{fault = new FpDisabled;}}); + 0x84: Trap::fxtos({{fault = new FpDisabled;}}); + 0x88: Trap::fxtod({{fault = new FpDisabled;}}); + 0x8C: Trap::fxtoq({{fault = new FpDisabled;}}); + 0xC4: Trap::fitos({{fault = new FpDisabled;}}); + 0xC6: Trap::fdtos({{fault = new FpDisabled;}}); + 0xC7: Trap::fqtos({{fault = new FpDisabled;}}); + 0xC8: Trap::fitod({{fault = new FpDisabled;}}); + 0xC9: Trap::fstod({{fault = new FpDisabled;}}); + 0xCB: Trap::fqtod({{fault = new FpDisabled;}}); + 0xCC: Trap::fitoq({{fault = new FpDisabled;}}); + 0xCD: Trap::fstoq({{fault = new FpDisabled;}}); + 0xCE: Trap::fdtoq({{fault = new FpDisabled;}}); + 0xD1: Trap::fstoi({{fault = new FpDisabled;}}); + 0xD2: Trap::fdtoi({{fault = new FpDisabled;}}); + 0xD3: Trap::fqtoi({{fault = new FpDisabled;}}); + default: Trap::fpop1({{fault = new FpDisabled;}}); + } 0x35: Trap::fpop2({{fault = new FpDisabled;}}); + //This used to be just impdep1, but now it's a whole bunch + //of instructions + 0x36: decode OPF{ + 0x00: Trap::edge8({{fault = new IllegalInstruction;}}); + 0x01: Trap::edge8n({{fault = new IllegalInstruction;}}); + 0x02: Trap::edge8l({{fault = new IllegalInstruction;}}); + 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}}); + 0x04: Trap::edge16({{fault = new IllegalInstruction;}}); + 0x05: Trap::edge16n({{fault = new IllegalInstruction;}}); + 0x06: Trap::edge16l({{fault = new IllegalInstruction;}}); + 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}}); + 0x08: Trap::edge32({{fault = new IllegalInstruction;}}); + 0x09: Trap::edge32n({{fault = new IllegalInstruction;}}); + 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}}); + 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}}); + 0x10: Trap::array8({{fault = new IllegalInstruction;}}); + 0x12: Trap::array16({{fault = new IllegalInstruction;}}); + 0x14: Trap::array32({{fault = new IllegalInstruction;}}); + 0x18: Trap::alignaddress({{fault = new IllegalInstruction;}}); + 0x19: Trap::bmask({{fault = new IllegalInstruction;}}); + 0x1A: Trap::alignaddresslittle({{fault = new IllegalInstruction;}}); + 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}}); + 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}}); + 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}}); + 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}}); + 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}}); + 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}}); + 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}}); + 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}}); + 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}}); + 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}}); + 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}}); + 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}}); + 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}}); + 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}}); + 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}}); + 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); + 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); + 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); + 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); + 0x48: Trap::faligndata({{fault = new IllegalInstruction;}}); + 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); + 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}}); + 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}}); + 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}}); + 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}}); + 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}}); + 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}}); + 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}}); + 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}}); + 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}}); + 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}}); + 0x60: BasicOperate::fzero({{Frd = 0;}}); + 0x61: Trap::fzeros({{fault = new IllegalInstruction;}}); + 0x62: Trap::fnor({{fault = new IllegalInstruction;}}); + 0x63: Trap::fnors({{fault = new IllegalInstruction;}}); + 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}}); + 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}}); + 0x66: Trap::fnot2({{fault = new IllegalInstruction;}}); + 0x67: Trap::fnot2s({{fault = new IllegalInstruction;}}); + 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}}); + 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}}); + 0x6A: Trap::fnot1({{fault = new IllegalInstruction;}}); + 0x6B: Trap::fnot1s({{fault = new IllegalInstruction;}}); + 0x6C: Trap::fxor({{fault = new IllegalInstruction;}}); + 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); + 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); + 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); + 0x70: Trap::fand({{fault = new IllegalInstruction;}}); + 0x71: Trap::fands({{fault = new IllegalInstruction;}}); + 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); + 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); + 0x74: Trap::fsrc1({{fault = new IllegalInstruction;}}); + 0x75: Trap::fsrc1s({{fault = new IllegalInstruction;}}); + 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); + 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); + 0x78: Trap::fsrc2({{fault = new IllegalInstruction;}}); + 0x79: Trap::fsrc2s({{fault = new IllegalInstruction;}}); + 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); + 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); + 0x7C: Trap::for({{fault = new IllegalInstruction;}}); + 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); + 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); + 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); + 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); + 0x81: Trap::siam({{fault = new IllegalInstruction;}}); + } + 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 0x38: Branch::jmpl({{ Addr target = Rs1 + Rs2_or_imm13; if(target & 0x3) @@ -549,7 +690,7 @@ decode OP default Unknown::unknown() NNPC = Tnpc + 4; Tl = Tl - 1; }}); - 0x1: BasicOperate::retry({{ + 0x1: Priv::retry({{ if(Tl == 0) return new IllegalInstruction; Cwp = Tstate<4:0>; @@ -645,12 +786,13 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: stdf({{fault = new FpDisabled;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: ldfa({{return new FpDisabled;}}); + 0x30: ldfa({{fault = new FpDisabled;}}); 0x32: ldqfa({{fault = new FpDisabled;}}); 0x33: lddfa({{fault = new FpDisabled;}}); 0x34: stfa({{fault = new FpDisabled;}}); - 0x35: stqfa({{fault = new FpDisabled;}}); - 0x36: stdfa({{fault = new FpDisabled;}}); + 0x36: stqfa({{fault = new FpDisabled;}}); + //XXX need to work in the ASI thing + 0x37: Store::stdfa({{Mem = ((uint64_t)Frd);}}, {{64}}); 0x3C: Cas::casa({{ uint64_t val = Mem.uw; if(Rs2.uw == val) diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 60432cb6b..0a47a7ffe 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -63,7 +63,6 @@ def template BasicExecute {{ { Fault fault = NoFault; - %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; %(code)s; @@ -81,11 +80,6 @@ def template BasicDecode {{ return new %(class_name)s(machInst); }}; -// Basic decode template, passing mnemonic in as string arg to constructor. -def template BasicDecodeWithMnemonic {{ - return new %(class_name)s("%(mnemonic)s", machInst); -}}; - // The most basic instruction format... used only for a few misc. insts def format BasicOperate(code, *flags) {{ iop = InstObjParams(name, Name, 'SparcStaticInst', diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa index 7d46ce739..8a3f05173 100644 --- a/src/arch/sparc/isa/formats/branch.isa +++ b/src/arch/sparc/isa/formats/branch.isa @@ -69,47 +69,18 @@ output header {{ }; /** - * Base class for branches with 19 bit displacements. + * Base class for branches with n bit displacements. */ - class Branch19 : public BranchDisp + template<int bits> + class BranchNBits : public BranchDisp { protected: // Constructor - Branch19(const char *mnem, MachInst _machInst, + BranchNBits(const char *mnem, MachInst _machInst, OpClass __opClass) : BranchDisp(mnem, _machInst, __opClass) { - disp = sign_ext(DISP19 << 2, 21); - } - }; - - /** - * Base class for branches with 22 bit displacements. - */ - class Branch22 : public BranchDisp - { - protected: - // Constructor - Branch22(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext(DISP22 << 2, 24); - } - }; - - /** - * Base class for branches with 30 bit displacements. - */ - class Branch30 : public BranchDisp - { - protected: - // Constructor - Branch30(const char *mnem, MachInst _machInst, - OpClass __opClass) : - BranchDisp(mnem, _machInst, __opClass) - { - disp = sign_ext(DISP30 << 2, 32); + disp = sign_ext(_machInst << 2, bits + 2); } }; @@ -149,29 +120,23 @@ output header {{ }}; output decoder {{ + + template class BranchNBits<19>; + + template class BranchNBits<22>; + + template class BranchNBits<30>; + std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; printMnemonic(response, mnemonic); - - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { + printRegArray(response, _srcRegIdx, _numSrcRegs); + if(_numDestRegs && _numSrcRegs) response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - - if (_numDestRegs > 0) - { - if(_numSrcRegs > 0) - response << ", "; - printReg(response, _destRegIdx[0]); - } + printDestReg(response, 0); return response.str(); } @@ -182,27 +147,13 @@ output decoder {{ std::stringstream response; printMnemonic(response, mnemonic); - - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - + printRegArray(response, _srcRegIdx, _numSrcRegs); if(_numSrcRegs > 0) response << ", "; - ccprintf(response, "0x%x", imm); - if (_numDestRegs > 0) - { response << ", "; - printReg(response, _destRegIdx[0]); - } + printDestReg(response, 0); return response.str(); } @@ -292,32 +243,10 @@ def format Branch(code, *opt_flags) {{ }}; // Primary format for branch instructions: -def format Branch19(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format Branch22(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) -}}; - -// Primary format for branch instructions: -def format Branch30(code, *opt_flags) {{ +def format BranchN(bits, code, *opt_flags) {{ code = re.sub(r'handle_annul', handle_annul, code) codeBlk = CodeBlock(code) - iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags) + iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = BranchExecute.subst(iop) diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 1894ce541..27616216e 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -132,7 +132,7 @@ output header {{ OpClass __opClass) : IntOpImm(mnem, _machInst, __opClass) { - imm = (IMM22 << 10) & 0xFFFFFC00; + imm = (IMM22 & 0x3FFFFF) << 10; } std::string generateDisassembly(Addr pc, @@ -157,12 +157,9 @@ output decoder {{ if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0) { printMnemonic(os, "mov"); - if(_numSrcRegs > 0) - printReg(os, _srcRegIdx[1]); + printSrcReg(os, 1); ccprintf(os, ", "); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - + printDestReg(os, 0); return true; } return false; @@ -173,32 +170,24 @@ output decoder {{ { if(!strcmp(mnemonic, "or")) { - if(_srcRegIdx[0] == 0) + if(_numSrcRegs > 0 && _srcRegIdx[0] == 0) { if(imm == 0) - { printMnemonic(os, "clr"); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - return true; - } else { printMnemonic(os, "mov"); - ccprintf(os, ", 0x%x, ", imm); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); - return true; + ccprintf(os, " 0x%x, ", imm); } + printDestReg(os, 0); + return true; } else if(imm == 0) { printMnemonic(os, "mov"); - if(_numSrcRegs > 0) - printReg(os, _srcRegIdx[0]); + printSrcReg(os, 0); ccprintf(os, ", "); - if(_numDestRegs > 0) - printReg(os, _destRegIdx[0]); + printDestReg(os, 0); return true; } } @@ -210,25 +199,13 @@ output decoder {{ { std::stringstream response; - if(!printPseudoOps(response, pc, symtab)) - { - printMnemonic(response, mnemonic); - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - if (_numDestRegs > 0) - { - if(_numSrcRegs > 0) - response << ", "; - printReg(response, _destRegIdx[0]); - } - } + if(printPseudoOps(response, pc, symtab)) + return response.str(); + printMnemonic(response, mnemonic); + printRegArray(response, _srcRegIdx, _numSrcRegs); + if(_numDestRegs && _numSrcRegs) + response << ", "; + printDestReg(response, 0); return response.str(); } @@ -237,27 +214,16 @@ output decoder {{ { std::stringstream response; - if(!printPseudoOps(response, pc, symtab)) - { - printMnemonic(response, mnemonic); - if (_numSrcRegs > 0) - { - printReg(response, _srcRegIdx[0]); - for(int x = 1; x < _numSrcRegs - 1; x++) - { - response << ", "; - printReg(response, _srcRegIdx[x]); - } - } - if(_numSrcRegs > 0) - response << ", "; - ccprintf(response, "0x%x", imm); - if (_numDestRegs > 0) - { - response << ", "; - printReg(response, _destRegIdx[0]); - } - } + if(printPseudoOps(response, pc, symtab)) + return response.str(); + printMnemonic(response, mnemonic); + printRegArray(response, _srcRegIdx, _numSrcRegs); + if(_numSrcRegs > 0) + response << ", "; + ccprintf(response, "0x%x", imm); + if(_numDestRegs > 0) + response << ", "; + printDestReg(response, 0); return response.str(); } @@ -267,10 +233,8 @@ output decoder {{ std::stringstream response; printMnemonic(response, mnemonic); - if(_numSrcRegs > 0) - response << ", "; ccprintf(response, "%%hi(0x%x), ", imm); - printReg(response, _destRegIdx[0]); + printDestReg(response, 0); return response.str(); } }}; @@ -316,38 +280,29 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) calcCcCode = ''' - uint8_t tmp_ccriccc; - uint8_t tmp_ccriccv; - uint8_t tmp_ccriccz; - uint8_t tmp_ccriccn; - uint8_t tmp_ccrxccc; - uint8_t tmp_ccrxccv; - uint8_t tmp_ccrxccz; - uint8_t tmp_ccrxccn; - - tmp_ccriccn = (Rd >> 31) & 1; - tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0); - tmp_ccrxccn = (Rd >> 63) & 1; - tmp_ccrxccz = (Rd == 0); - tmp_ccriccv = %(ivValue)s & 1; - tmp_ccriccc = %(icValue)s & 1; - tmp_ccrxccv = %(xvValue)s & 1; - tmp_ccrxccc = %(xcValue)s & 1; - - Ccr = tmp_ccriccc | tmp_ccriccv << 1 | - tmp_ccriccz << 2 | tmp_ccriccn << 3| - tmp_ccrxccc << 4 | tmp_ccrxccv << 5| - tmp_ccrxccz << 6| tmp_ccrxccn << 7; - - - DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn); - DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz); - DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn); - DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz); - DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv); - DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc); - DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv); - DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc); + uint16_t _ic, _iv, _iz, _in, _xc, _xv, _xz, _xn; + + _in = (Rd >> 31) & 1; + _iz = ((Rd & 0xFFFFFFFF) == 0); + _xn = (Rd >> 63) & 1; + _xz = (Rd == 0); + _iv = %(ivValue)s & 1; + _ic = %(icValue)s & 1; + _xv = %(xvValue)s & 1; + _xc = %(xcValue)s & 1; + + Ccr = _ic << 0 | _iv << 1 | _iz << 2 | _in << 3 | + _xc << 4 | _xv << 5 | _xz << 6 | _xn << 7; + + + DPRINTF(Sparc, "in = %%d\\n", _in); + DPRINTF(Sparc, "iz = %%d\\n", _iz); + DPRINTF(Sparc, "xn = %%d\\n", _xn); + DPRINTF(Sparc, "xz = %%d\\n", _xz); + DPRINTF(Sparc, "iv = %%d\\n", _iv); + DPRINTF(Sparc, "ic = %%d\\n", _ic); + DPRINTF(Sparc, "xv = %%d\\n", _xv); + DPRINTF(Sparc, "xc = %%d\\n", _xc); ''' }}; diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 7df59d736..d7ee01519 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -72,7 +72,11 @@ output decoder {{ std::string Priv::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return "Privileged Instruction"; + std::stringstream response; + + printMnemonic(response, mnemonic); + + return response.str(); } }}; @@ -87,9 +91,10 @@ def template PrivExecute {{ if(%(check)s) return new PrivilegedAction; + Fault fault = NoFault; %(code)s; %(op_wb)s; - return NoFault; + return fault; } }}; @@ -116,10 +121,17 @@ let {{ // Primary format for integer operate instructions: def format Priv(code, *opt_flags) {{ - checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)" + checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) || + ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)''' (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) + checkCode, name, Name, opt_flags + ('IprAccessOp',)) }}; +def format HPriv(code, *opt_flags) {{ + checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)" + (header_output, decoder_output, + exec_output, decode_block) = doPrivFormat(code, + checkCode, name, Name, opt_flags + ('IprAccessOp',)) +}}; diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 40afb3722..3783051c4 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -36,7 +36,6 @@ output header {{ #include <sstream> #include <iostream> -#include <iomanip> #include "cpu/static_inst.hh" #include "arch/sparc/faults.hh" @@ -50,7 +49,6 @@ output decoder {{ #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() -#include <math.h> #if defined(linux) #include <fenv.h> #endif @@ -59,14 +57,10 @@ using namespace SparcISA; }}; output exec {{ -#include <math.h> #if defined(linux) #include <fenv.h> #endif -#ifdef FULL_SYSTEM -//#include "sim/pseudo_inst.hh" -#endif #include "cpu/base.hh" #include "cpu/exetrace.hh" #include "sim/sim_exit.hh" diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 9e5c783e8..d250d3672 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -51,12 +51,12 @@ def operands {{ 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), - #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), - #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), - #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4), - 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4), + 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10), + 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), + 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20), + 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), + 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 'R0': ('IntReg', 'udw', '0', None, 6), @@ -65,24 +65,24 @@ def operands {{ 'R16': ('IntReg', 'udw', '16', None, 9), # Control registers - 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12), - 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17), - 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26), + 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), + 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), + 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), - 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28), - 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 28), - 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 28), - 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), - 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27), + 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), + 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), + 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), + 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), + 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), - 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15), - 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34), - 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35), - 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37), - 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36), - 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38), - 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 12), + 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), + 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), + 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), + 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), + 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), + 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), + 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), - 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47) + 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55) }}; diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index cbeb3c7b9..db48b2d78 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -55,14 +55,12 @@ namespace SparcISA // NWINDOWS - number of register windows, can be 3 to 32 const int NWindows = 32; - const int AsrStart = 0; const int PrStart = 32; const int HprStart = 64; const int MiscStart = 96; const uint64_t Bit64 = (1ULL << 63); - class IntRegFile { protected: @@ -182,7 +180,7 @@ namespace SparcISA //Since the floating point registers overlap each other, //A generic storage space is used. The float to be returned is //pulled from the appropriate section of this region. - char regSpace[SingleWidth / 8 * NumFloatRegs]; + char regSpace[(SingleWidth / 8) * NumFloatRegs]; public: @@ -200,15 +198,15 @@ namespace SparcISA { case SingleWidth: float32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, width); + memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); return htog(result32); case DoubleWidth: float64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, width); + memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); return htog(result64); case QuadWidth: float128_t result128; - memcpy(&result128, regSpace + 4 * floatReg, width); + memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); return htog(result128); default: panic("Attempted to read a %d bit floating point register!", width); @@ -224,15 +222,15 @@ namespace SparcISA { case SingleWidth: uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, width); + memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); return htog(result32); case DoubleWidth: uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, width); + memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); return htog(result64); case QuadWidth: uint64_t result128; - memcpy(&result128, regSpace + 4 * floatReg, width); + memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); return htog(result128); default: panic("Attempted to read a %d bit floating point register!", width); @@ -247,15 +245,16 @@ namespace SparcISA uint32_t result32; uint64_t result64; + DPRINTF(Sparc, "Setting floating point register %d\n", floatReg); switch(width) { case SingleWidth: result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, width); + memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); break; case DoubleWidth: result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, width); + memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); break; case QuadWidth: panic("Quad width FP not implemented."); @@ -277,11 +276,11 @@ namespace SparcISA { case SingleWidth: result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, width); + memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); break; case DoubleWidth: result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, width); + memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); break; case QuadWidth: panic("Quad width FP not implemented."); @@ -625,11 +624,9 @@ namespace SparcISA hpstateFields.red = 1; hpstateFields.hpriv = 1; hpstateFields.tlz = 0; // this is a guess - hintp = 0; // no interrupts pending hstick_cmprFields.int_dis = 1; // disable timer compare interrupts hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing - #else /* //This sets up the initial state of the processor for usermode processes pstateFields.priv = 0; //Process runs in user mode @@ -687,6 +684,8 @@ namespace SparcISA void copyMiscRegs(ThreadContext * tc); + protected: + bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } bool isNonPriv() { return !isPriv(); } diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 7d45c7870..2bb9a2399 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -160,7 +160,8 @@ if 'O3CPU' in env['CPU_MODELS']: ''') if env['USE_CHECKER']: sources += Split('o3/checker_builder.cc') - env['SMT_CPU_MODELS'].append('O3CPU') + else: + env['SMT_CPU_MODELS'].append('O3CPU') # Checker doesn't support SMT right now if 'OzoneCPU' in env['CPU_MODELS']: need_bp_unit = True diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 246bcec05..5c1654f7e 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status) panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); } + +void +TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) +{ + pkt = _pkt; + Event::schedule(t); +} + TimingSimpleCPU::TimingSimpleCPU(Params *p) - : BaseSimpleCPU(p), icachePort(this), dcachePort(this) + : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) { _status = Idle; ifetch_pkt = dcache_pkt = NULL; @@ -462,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt) } } +void +TimingSimpleCPU::IcachePort::ITickEvent::process() +{ + cpu->completeIfetch(pkt); +} bool TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { - cpu->completeIfetch(pkt); + // These next few lines could be replaced with something faster + // who knows what though + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, time); + return true; } @@ -523,11 +546,25 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - cpu->completeDataAccess(pkt); + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeDataAccess(pkt); + else + tickEvent.schedule(pkt, time); + return true; } void +TimingSimpleCPU::DcachePort::DTickEvent::process() +{ + cpu->completeDataAccess(pkt); +} + +void TimingSimpleCPU::DcachePort::recvRetry() { // we shouldn't get a retry unless we have a packet that we're diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ac36e5c99..d03fa4bc0 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU { protected: TimingSimpleCPU *cpu; + Tick lat; public: - CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) - : Port(_name), cpu(_cpu) + CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) + : Port(_name), cpu(_cpu), lat(_lat) { } protected: @@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { resp.clear(); snoop.clear(); } + + struct TickEvent : public Event + { + Packet *pkt; + TimingSimpleCPU *cpu; + + TickEvent(TimingSimpleCPU *_cpu) + :Event(&mainEventQueue), cpu(_cpu) {} + const char *description() { return "Timing CPU clock event"; } + void schedule(Packet *_pkt, Tick t); + }; + }; class IcachePort : public CpuPort { public: - IcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-iport", _cpu) + IcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct ITickEvent : public TickEvent + { + + ITickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + ITickEvent tickEvent; + }; class DcachePort : public CpuPort { public: - DcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-dport", _cpu) + DcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct DTickEvent : public TickEvent + { + DTickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + DTickEvent tickEvent; + }; IcachePort icachePort; diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 660efabfd..b51a93190 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -36,8 +36,7 @@ PioPort::PioPort(PioDevice *dev, System *s, std::string pname) - : Port(dev->name() + pname), device(dev), sys(s), - outTiming(0), drainEvent(NULL) + : SimpleTimingPort(dev->name() + pname), device(dev), sys(s) { } @@ -61,48 +60,6 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) } -void -PioPort::recvRetry() -{ - bool result = true; - while (result && transmitList.size()) { - result = Port::sendTiming(transmitList.front()); - if (result) - transmitList.pop_front(); - } - if (transmitList.size() == 0 && drainEvent) { - drainEvent->process(); - drainEvent = NULL; - } -} - -void -PioPort::SendEvent::process() -{ - port->outTiming--; - assert(port->outTiming >= 0); - if (port->Port::sendTiming(packet)) - if (port->transmitList.size() == 0 && port->drainEvent) { - port->drainEvent->process(); - port->drainEvent = NULL; - } - return; - - port->transmitList.push_back(packet); -} - -void -PioPort::resendNacked(Packet *pkt) { - pkt->reinitNacked(); - if (transmitList.size()) { - transmitList.push_front(pkt); - } else { - if (!Port::sendTiming(pkt)) - transmitList.push_front(pkt); - } -}; - - bool PioPort::recvTiming(Packet *pkt) { @@ -117,15 +74,6 @@ PioPort::recvTiming(Packet *pkt) return true; } -unsigned int -PioPort::drain(Event *de) -{ - if (outTiming == 0 && transmitList.size() == 0) - return 0; - drainEvent = de; - return 1; -} - PioDevice::~PioDevice() { if (pioPort) diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index fa3f98247..22a32e73a 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -37,6 +37,7 @@ #include "mem/packet_impl.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" +#include "mem/tport.hh" class Platform; class PioDevice; @@ -48,13 +49,9 @@ class System; * sensitive to an address range use. The port takes all the memory * access types and roles them into one read() and write() call that the device * must respond to. The device must also provide the addressRanges() function - * with which it returns the address ranges it is interested in. An extra - * sendTiming() function is implemented which takes an delay. In this way the - * device can immediatly call sendTiming(pkt, time) after processing a request - * and the request will be handled by the port even if the port bus the device - * connects to is blocked. - */ -class PioPort : public Port + * with which it returns the address ranges it is interested in. */ + +class PioPort : public SimpleTimingPort { protected: /** The device that this port serves. */ @@ -64,10 +61,6 @@ class PioPort : public Port * we are currently operating in. */ System *sys; - /** A list of outgoing timing response packets that haven't been serviced - * yet. */ - std::list<Packet*> transmitList; - /** The current status of the peer(bus) that we are connected to. */ Status peerStatus; @@ -82,53 +75,9 @@ class PioPort : public Port virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); - void resendNacked(Packet *pkt); - - /** - * This class is used to implemented sendTiming() with a delay. When a delay - * is requested a new event is created. When the event time expires it - * attempts to send the packet. If it cannot, the packet is pushed onto the - * transmit list to be sent when recvRetry() is called. */ - class SendEvent : public Event - { - PioPort *port; - Packet *packet; - - SendEvent(PioPort *p, Packet *pkt, Tick t) - : Event(&mainEventQueue), port(p), packet(pkt) - { schedule(curTick + t); } - - virtual void process(); - - virtual const char *description() - { return "Future scheduled sendTiming event"; } - - friend class PioPort; - }; - - /** Number of timing requests that are emulating the device timing before - * attempting to end up on the bus. - */ - int outTiming; - - /** If we need to drain, keep the drain event around until we're done - * here.*/ - Event *drainEvent; - - /** Schedule a sendTiming() event to be called in the future. */ - void sendTiming(Packet *pkt, Tick time) - { outTiming++; new PioPort::SendEvent(this, pkt, time); } - - /** This function is notification that the device should attempt to send a - * packet again. */ - virtual void recvRetry(); - public: PioPort(PioDevice *dev, System *s, std::string pname = "-pioport"); - unsigned int drain(Event *de); - - friend class PioPort::SendEvent; }; diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 2d66602ab..291c70d8c 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Ron Dreslinski + * Ali Saidi */ #include <sys/types.h> @@ -52,24 +53,6 @@ using namespace std; using namespace TheISA; -PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet *pkt, MemoryPort* _m) - : Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m) -{ - - this->setFlags(AutoDelete); -} - -void -PhysicalMemory::MemResponseEvent::process() -{ - memoryPort->sendTiming(pkt); -} - -const char * -PhysicalMemory::MemResponseEvent::description() -{ - return "Physical Memory Timing Access respnse event"; -} PhysicalMemory::PhysicalMemory(const string &n, Tick latency) : MemObject(n),base_addr(0), pmem_addr(NULL), port(NULL), lat(latency) @@ -124,27 +107,8 @@ PhysicalMemory::deviceBlockSize() return 0; } -bool -PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort) -{ - doFunctionalAccess(pkt); - - // turn packet around to go back to requester - pkt->makeTimingResponse(); - MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort); - response->schedule(curTick + lat); - - return true; -} Tick -PhysicalMemory::doAtomicAccess(Packet *pkt) -{ - doFunctionalAccess(pkt); - return lat; -} - -void PhysicalMemory::doFunctionalAccess(Packet *pkt) { assert(pkt->getAddr() + pkt->getSize() < pmem_size); @@ -170,6 +134,7 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) } pkt->result = Packet::Success; + return lat; } Port * @@ -195,7 +160,7 @@ PhysicalMemory::recvStatusChange(Port::Status status) PhysicalMemory::MemoryPort::MemoryPort(const std::string &_name, PhysicalMemory *_memory) - : Port(_name), memory(_memory) + : SimpleTimingPort(_name), memory(_memory) { } void @@ -228,13 +193,20 @@ PhysicalMemory::MemoryPort::deviceBlockSize() bool PhysicalMemory::MemoryPort::recvTiming(Packet *pkt) { - return memory->doTimingAccess(pkt, this); + assert(pkt->result != Packet::Nacked); + + Tick latency = memory->doFunctionalAccess(pkt); + + pkt->makeTimingResponse(); + sendTiming(pkt, latency); + + return true; } Tick PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt) { - return memory->doAtomicAccess(pkt); + return memory->doFunctionalAccess(pkt); } void @@ -243,7 +215,16 @@ PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt) memory->doFunctionalAccess(pkt); } - +unsigned int +PhysicalMemory::drain(Event *de) +{ + int count = port->drain(de); + if (count) + changeState(Draining); + else + changeState(Drained); + return count; +} void PhysicalMemory::serialize(ostream &os) diff --git a/src/mem/physical.hh b/src/mem/physical.hh index 50fa75ed3..b549c1f8b 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -37,7 +37,7 @@ #include "base/range.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" -#include "mem/port.hh" +#include "mem/tport.hh" #include "sim/eventq.hh" #include <map> #include <string> @@ -47,7 +47,7 @@ // class PhysicalMemory : public MemObject { - class MemoryPort : public Port + class MemoryPort : public SimpleTimingPort { PhysicalMemory *memory; @@ -74,16 +74,6 @@ class PhysicalMemory : public MemObject int numPorts; - struct MemResponseEvent : public Event - { - Packet *pkt; - MemoryPort *memoryPort; - - MemResponseEvent(Packet *pkt, MemoryPort *memoryPort); - void process(); - const char *description(); - }; - private: // prevent copying of a MainMemory object PhysicalMemory(const PhysicalMemory &specmem); @@ -110,13 +100,10 @@ class PhysicalMemory : public MemObject void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); virtual Port *getPort(const std::string &if_name, int idx = -1); void virtual init(); + unsigned int drain(Event *de); - // fast back-door memory access for vtophys(), remote gdb, etc. - // uint64_t phys_read_qword(Addr addr) const; private: - bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort); - Tick doAtomicAccess(Packet *pkt); - void doFunctionalAccess(Packet *pkt); + Tick doFunctionalAccess(Packet *pkt); void recvStatusChange(Port::Status status); diff --git a/src/mem/tport.cc b/src/mem/tport.cc new file mode 100644 index 000000000..90cf68f02 --- /dev/null +++ b/src/mem/tport.cc @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include "mem/tport.hh" + +void +SimpleTimingPort::recvRetry() +{ + bool result = true; + while (result && transmitList.size()) { + result = Port::sendTiming(transmitList.front()); + if (result) + transmitList.pop_front(); + } + if (transmitList.size() == 0 && drainEvent) { + drainEvent->process(); + drainEvent = NULL; + } +} + +void +SimpleTimingPort::SendEvent::process() +{ + port->outTiming--; + assert(port->outTiming >= 0); + if (port->Port::sendTiming(packet)) + if (port->transmitList.size() == 0 && port->drainEvent) { + port->drainEvent->process(); + port->drainEvent = NULL; + } + return; + + port->transmitList.push_back(packet); +} + +void +SimpleTimingPort::resendNacked(Packet *pkt) { + pkt->reinitNacked(); + if (transmitList.size()) { + transmitList.push_front(pkt); + } else { + if (!Port::sendTiming(pkt)) + transmitList.push_front(pkt); + } +}; + + +unsigned int +SimpleTimingPort::drain(Event *de) +{ + if (outTiming == 0 && transmitList.size() == 0) + return 0; + drainEvent = de; + return 1; +} diff --git a/src/mem/tport.hh b/src/mem/tport.hh new file mode 100644 index 000000000..5473e945e --- /dev/null +++ b/src/mem/tport.hh @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +/** + * @file + * Implement a port which adds simple support of a sendTiming() function that + * takes a delay. In this way the * device can immediatly call + * sendTiming(pkt, time) after processing a request and the request will be + * handled by the port even if the port bus the device connects to is blocked. + */ + +/** recvTiming and drain should be implemented something like this when this + * class is used. + +bool +PioPort::recvTiming(Packet *pkt) +{ + if (pkt->result == Packet::Nacked) { + resendNacked(pkt); + } else { + Tick latency = device->recvAtomic(pkt); + // turn packet around to go back to requester + pkt->makeTimingResponse(); + sendTiming(pkt, latency); + } + return true; +} + +PioDevice::drain(Event *de) +{ + unsigned int count; + count = SimpleTimingPort->drain(de); + if (count) + changeState(Draining); + else + changeState(Drained); + return count; +} +*/ + +#ifndef __MEM_TPORT_HH__ +#define __MEM_TPORT_HH__ + +#include "mem/port.hh" +#include "sim/eventq.hh" +#include <list> +#include <string> + +class SimpleTimingPort : public Port +{ + protected: + /** A list of outgoing timing response packets that haven't been serviced + * yet. */ + std::list<Packet*> transmitList; + /** + * This class is used to implemented sendTiming() with a delay. When a delay + * is requested a new event is created. When the event time expires it + * attempts to send the packet. If it cannot, the packet is pushed onto the + * transmit list to be sent when recvRetry() is called. */ + class SendEvent : public Event + { + SimpleTimingPort *port; + Packet *packet; + + SendEvent(SimpleTimingPort *p, Packet *pkt, Tick t) + : Event(&mainEventQueue), port(p), packet(pkt) + { setFlags(AutoDelete); schedule(curTick + t); } + + virtual void process(); + + virtual const char *description() + { return "Future scheduled sendTiming event"; } + + friend class SimpleTimingPort; + }; + + + /** Number of timing requests that are emulating the device timing before + * attempting to end up on the bus. + */ + int outTiming; + + /** If we need to drain, keep the drain event around until we're done + * here.*/ + Event *drainEvent; + + /** Schedule a sendTiming() event to be called in the future. */ + void sendTiming(Packet *pkt, Tick time) + { outTiming++; new SimpleTimingPort::SendEvent(this, pkt, time); } + + /** This function is notification that the device should attempt to send a + * packet again. */ + virtual void recvRetry(); + + void resendNacked(Packet *pkt); + public: + + SimpleTimingPort(std::string pname) + : Port(pname), outTiming(0), drainEvent(NULL) + {} + + unsigned int drain(Event *de); + + friend class SimpleTimingPort::SendEvent; +}; + +#endif // __MEM_TPORT_HH__ diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index 222f750da..f72c8e73f 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -12,7 +12,7 @@ class BasicPioDevice(PioDevice): type = 'BasicPioDevice' abstract = True pio_addr = Param.Addr("Device Address") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") class DmaDevice(PioDevice): type = 'DmaDevice' diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index d6bc454ad..41208929a 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -1,91 +1,101 @@ from m5 import build_env from m5.config import * from BaseCPU import BaseCPU +from Checker import O3Checker class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' - activity = Param.Unsigned("Initial count") - numThreads = Param.Unsigned("number of HW thread contexts") - - checker = Param.BaseCPU(NULL, "checker") + activity = Param.Unsigned(0, "Initial count") + numThreads = Param.Unsigned(1, "number of HW thread contexts") + + if build_env['USE_CHECKER']: + if not build_env['FULL_SYSTEM']: + checker = Param.BaseCPU(O3Checker(workload=Parent.workload, + exitOnError=True, + warnOnlyOnLoadError=False), + "checker") + else: + checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker") + checker.itb = Parent.itb + checker.dtb = Parent.dtb cachePorts = Param.Unsigned("Cache Ports") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") + decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") + renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") + iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") + fetchWidth = Param.Unsigned(8, "Fetch width") - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay") + iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode " "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") + commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay") + decodeWidth = Param.Unsigned(8, "Decode width") - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename " "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") + commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay") + decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay") + renameWidth = Param.Unsigned(8, "Rename width") - commitToIEWDelay = Param.Unsigned("Commit to " + commitToIEWDelay = Param.Unsigned(1, "Commit to " "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " + renameToIEWDelay = Param.Unsigned(2, "Rename to " "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal " "to the IEW stage)") - dispatchWidth = Param.Unsigned("Dispatch width") - issueWidth = Param.Unsigned("Issue width") - wbWidth = Param.Unsigned("Writeback width") - wbDepth = Param.Unsigned("Writeback depth") - fuPool = Param.FUPool(NULL, "Functional Unit pool") + dispatchWidth = Param.Unsigned(8, "Dispatch width") + issueWidth = Param.Unsigned(8, "Issue width") + wbWidth = Param.Unsigned(8, "Writeback width") + wbDepth = Param.Unsigned(1, "Writeback depth") + fuPool = Param.FUPool("Functional Unit pool") - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit " "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - trapLatency = Param.Tick("Trap latency") - fetchTrapLatency = Param.Tick("Fetch trap latency") - - backComSize = Param.Unsigned("Time buffer size for backwards communication") - forwardComSize = Param.Unsigned("Time buffer size for forward communication") - - predType = Param.String("Branch predictor type ('local', 'tournament')") - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numRobs = Param.Unsigned("Number of Reorder Buffers"); - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay") + commitWidth = Param.Unsigned(8, "Commit width") + squashWidth = Param.Unsigned(8, "Squash width") + trapLatency = Param.Tick(13, "Trap latency") + fetchTrapLatency = Param.Tick(1, "Fetch trap latency") + + backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") + forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") + + predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") + localPredictorSize = Param.Unsigned(2048, "Size of local predictor") + localCtrBits = Param.Unsigned(2, "Bits per counter") + localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") + localHistoryBits = Param.Unsigned(11, "Bits for the local history") + globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") + globalCtrBits = Param.Unsigned(2, "Bits per counter") + globalHistoryBits = Param.Unsigned(4096, "Bits of history") + choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") + choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") + + BTBEntries = Param.Unsigned(4096, "Number of BTB entries") + BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") + + RASSize = Param.Unsigned(16, "RAS size") + + LQEntries = Param.Unsigned(32, "Number of load queue entries") + SQEntries = Param.Unsigned(32, "Number of store queue entries") + LFSTSize = Param.Unsigned(1024, "Last fetched store table size") + SSITSize = Param.Unsigned(1024, "Store set ID table size") + + numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); + + numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") + numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py index 29014bb37..cc0d1cf4a 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/python/m5/objects/Pci.py @@ -52,7 +52,7 @@ class PciDevice(DmaDevice): pci_bus = Param.Int("PCI bus") pci_dev = Param.Int("PCI device number") pci_func = Param.Int("PCI function code") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") configdata = Param.PciConfigData(Parent.any, "PCI Config data") class PciFake(PciDevice): diff --git a/tests/SConscript b/tests/SConscript index 5eadce6d4..7ccb77759 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -1,6 +1,6 @@ # -*- mode:python -*- -# Copyright (c) 2004-2005 The Regents of The University of Michigan +# Copyright (c) 2004-2006 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -25,6 +25,9 @@ # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt +# Kevin Lim import os import sys @@ -136,7 +139,8 @@ def update_test_string(target, source, env): updateAction = env.Action(update_test, update_test_string) -def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=15): +def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', + timeout=15): """Define a test. Args: @@ -151,14 +155,31 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 default_refdir = False if refdir == 'ref': default_refdir = True + valid_cpu_list = [] if len(cpu_list) == 0: - cpu_list = env['CPU_MODELS'] + valid_cpu_list = env['CPU_MODELS'] + else: + for i in cpu_list: + if i in env['CPU_MODELS']: + valid_cpu_list.append(i) + cpu_list = valid_cpu_list + if env['TEST_CPU_MODELS']: + valid_cpu_list = [] + for i in env['TEST_CPU_MODELS']: + if i in cpu_list: + valid_cpu_list.append(i) + cpu_list = valid_cpu_list +# Code commented out that shows the general structure if we want to test +# different OS's as well. # if len(os_list) == 0: -# raise RuntimeError, "No OS specified" +# for test_cpu in cpu_list: +# build_cpu_test(env, category, '', test_cpu, refdir, timeout) # else: # for test_os in os_list: -# build_cpu_test(env, category, test_os, cpu_list, refdir, timeout) - # Loop through CPU models and generate proper options, ref directories for each +# for test_cpu in cpu_list: +# build_cpu_test(env, category, test_os, test_cpu, refdir, +# timeout) + # Loop through CPU models and generate proper options, ref directories for cpu in cpu_list: test_os = '' if cpu == "AtomicSimpleCPU": @@ -171,7 +192,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 raise TypeError, "Unknown CPU model specified" if default_refdir: - # Reference stats located in ref/arch/os/cpu or ref/arch/cpu if no OS specified + # Reference stats located in ref/arch/os/cpu or ref/arch/cpu + # if no OS specified test_refdir = os.path.join(refdir, env['TARGET_ISA']) if test_os != '': test_refdir = os.path.join(test_refdir, test_os) @@ -202,8 +224,8 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 else: cmd = [base_cmd, '>', cmd_stdout, '2>', cmd_stderr] - env.Command([stdout_string, stderr_string, m5stats_string], [env.M5Binary, 'run.py'], - ' '.join(cmd)) + env.Command([stdout_string, stderr_string, m5stats_string], + [env.M5Binary, 'run.py'], ' '.join(cmd)) # order of targets is important... see check_test env.Command([outdiff_string, statsdiff_string, status_string], @@ -212,10 +234,12 @@ def test_builder(env, category, cpu_list=[], os_list=[], refdir='ref', timeout=1 # phony target to echo status if env['update_ref']: - p = env.Command(cpu_option[1] + '_update', [ref_stats, m5stats_string, status_string], + p = env.Command(cpu_option[1] + '_update', + [ref_stats, m5stats_string, status_string], updateAction) else: - p = env.Command(cpu_option[1] + '_print', [status_string], printAction) + p = env.Command(cpu_option[1] + '_print', [status_string], + printAction) env.AlwaysBuild(p) env.Tests.setdefault(category, []) diff --git a/tests/halt.sh b/tests/halt.sh new file mode 100644 index 000000000..b1332ebab --- /dev/null +++ b/tests/halt.sh @@ -0,0 +1 @@ +m5 exit diff --git a/tests/test1/ref/alpha/atomic/config.ini b/tests/test1/ref/alpha/atomic/config.ini index 9961fe389..4cbe1fce6 100644 --- a/tests/test1/ref/alpha/atomic/config.ini +++ b/tests/test1/ref/alpha/atomic/config.ini @@ -48,11 +48,11 @@ text_file=m5stats.txt [system] type=System -children=cpu0 physmem workload +children=cpu physmem workload mem_mode=atomic physmem=system.physmem -[system.cpu0] +[system.cpu] type=AtomicSimpleCPU children=mem clock=1 @@ -63,13 +63,13 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu0.mem +mem=system.cpu.mem simulate_stalls=false system=system width=1 workload=system.workload -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 diff --git a/tests/test1/ref/alpha/atomic/config.out b/tests/test1/ref/alpha/atomic/config.out index a9c04ceff..65a9f6f7f 100644 --- a/tests/test1/ref/alpha/atomic/config.out +++ b/tests/test1/ref/alpha/atomic/config.out @@ -23,17 +23,17 @@ chkpt= output=cout system=system -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 -[system.cpu0] +[system.cpu] type=AtomicSimpleCPU max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -mem=system.cpu0.mem +mem=system.cpu.mem system=system workload=system.workload clock=1 diff --git a/tests/test1/ref/alpha/atomic/m5stats.txt b/tests/test1/ref/alpha/atomic/m5stats.txt index 09e94d639..29c0b91ac 100644 --- a/tests/test1/ref/alpha/atomic/m5stats.txt +++ b/tests/test1/ref/alpha/atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1301768 # Simulator instruction rate (inst/s) -host_mem_usage 147756 # Number of bytes of host memory used +host_inst_rate 1310554 # Simulator instruction rate (inst/s) +host_mem_usage 147620 # Number of bytes of host memory used host_seconds 0.38 # Real time elapsed on the host -host_tick_rate 1300060 # Simulator tick rate (ticks/s) +host_tick_rate 1308843 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated sim_ticks 499999 # Number of ticks simulated -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 500000 # number of cpu cycles simulated -system.cpu0.num_insts 500000 # Number of instructions executed -system.cpu0.num_refs 182204 # Number of memory references +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 500000 # number of cpu cycles simulated +system.cpu.num_insts 500000 # Number of instructions executed +system.cpu.num_refs 182204 # Number of memory references system.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/atomic/stdout b/tests/test1/ref/alpha/atomic/stdout index 78ab05bdd..66d1c50da 100644 --- a/tests/test1/ref/alpha/atomic/stdout +++ b/tests/test1/ref/alpha/atomic/stdout @@ -7,8 +7,7 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 19 2006 15:49:01 -M5 started Wed Jul 19 15:49:10 2006 +M5 compiled Jul 21 2006 16:19:30 +M5 started Fri Jul 21 16:40:43 2006 M5 executing on zamp.eecs.umich.edu -Creating SE system Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/test1/ref/alpha/detailed/config.ini b/tests/test1/ref/alpha/detailed/config.ini index 192833c8b..a442ec572 100644 --- a/tests/test1/ref/alpha/detailed/config.ini +++ b/tests/test1/ref/alpha/detailed/config.ini @@ -48,13 +48,13 @@ text_file=m5stats.txt [system] type=System -children=cpu0 physmem workload +children=cpu physmem workload mem_mode=atomic physmem=system.physmem -[system.cpu0] +[system.cpu] type=DerivO3CPU -children=checker fuPool mem +children=fuPool mem BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -64,7 +64,6 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 -checker=system.cpu0.checker choiceCtrBits=2 choicePredictorSize=8192 clock=1 @@ -79,9 +78,10 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 fetchToDecodeDelay=1 +fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 -fuPool=system.cpu0.fuPool +fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 globalCtrBits=2 @@ -102,11 +102,12 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu0.mem +mem=system.cpu.mem numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 +numRobs=1 numThreads=1 predType=tournament renameToDecodeDelay=1 @@ -116,163 +117,149 @@ renameToROBDelay=1 renameWidth=8 squashWidth=8 system=system +trapLatency=13 wbDepth=1 wbWidth=8 workload=system.workload -[system.cpu0.checker] -type=O3Checker -clock=1 -defer_registration=false -exitOnError=true -function_trace=false -function_trace_start=0 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -system=system -warnOnlyOnLoadError=false -workload=system.workload - -[system.cpu0.fuPool] +[system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 -[system.cpu0.fuPool.FUList0] +[system.cpu.fuPool.FUList0] type=FUDesc children=opList0 count=6 -opList=system.cpu0.fuPool.FUList0.opList0 +opList=system.cpu.fuPool.FUList0.opList0 -[system.cpu0.fuPool.FUList0.opList0] +[system.cpu.fuPool.FUList0.opList0] type=OpDesc issueLat=1 opClass=IntAlu opLat=1 -[system.cpu0.fuPool.FUList1] +[system.cpu.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 -opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -[system.cpu0.fuPool.FUList1.opList0] +[system.cpu.fuPool.FUList1.opList0] type=OpDesc issueLat=1 opClass=IntMult opLat=3 -[system.cpu0.fuPool.FUList1.opList1] +[system.cpu.fuPool.FUList1.opList1] type=OpDesc issueLat=19 opClass=IntDiv opLat=20 -[system.cpu0.fuPool.FUList2] +[system.cpu.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 -opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -[system.cpu0.fuPool.FUList2.opList0] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc issueLat=1 opClass=FloatAdd opLat=2 -[system.cpu0.fuPool.FUList2.opList1] +[system.cpu.fuPool.FUList2.opList1] type=OpDesc issueLat=1 opClass=FloatCmp opLat=2 -[system.cpu0.fuPool.FUList2.opList2] +[system.cpu.fuPool.FUList2.opList2] type=OpDesc issueLat=1 opClass=FloatCvt opLat=2 -[system.cpu0.fuPool.FUList3] +[system.cpu.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 count=2 -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -[system.cpu0.fuPool.FUList3.opList0] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc issueLat=1 opClass=FloatMult opLat=4 -[system.cpu0.fuPool.FUList3.opList1] +[system.cpu.fuPool.FUList3.opList1] type=OpDesc issueLat=12 opClass=FloatDiv opLat=12 -[system.cpu0.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList2] type=OpDesc issueLat=24 opClass=FloatSqrt opLat=24 -[system.cpu0.fuPool.FUList4] +[system.cpu.fuPool.FUList4] type=FUDesc children=opList0 count=0 -opList=system.cpu0.fuPool.FUList4.opList0 +opList=system.cpu.fuPool.FUList4.opList0 -[system.cpu0.fuPool.FUList4.opList0] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu0.fuPool.FUList5] +[system.cpu.fuPool.FUList5] type=FUDesc children=opList0 count=0 -opList=system.cpu0.fuPool.FUList5.opList0 +opList=system.cpu.fuPool.FUList5.opList0 -[system.cpu0.fuPool.FUList5.opList0] +[system.cpu.fuPool.FUList5.opList0] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList6] +[system.cpu.fuPool.FUList6] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu0.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu0.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList6.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList7] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 count=1 -opList=system.cpu0.fuPool.FUList7.opList0 +opList=system.cpu.fuPool.FUList7.opList0 -[system.cpu0.fuPool.FUList7.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=3 opClass=IprAccess opLat=3 -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 diff --git a/tests/test1/ref/alpha/detailed/config.out b/tests/test1/ref/alpha/detailed/config.out index 07c092a2b..c92557696 100644 --- a/tests/test1/ref/alpha/detailed/config.out +++ b/tests/test1/ref/alpha/detailed/config.out @@ -23,160 +23,146 @@ chkpt= output=cout system=system -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 -[system.cpu0.checker] -type=O3Checker -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -workload=system.workload -clock=1 -defer_registration=false -exitOnError=true -warnOnlyOnLoadError=false -function_trace=false -function_trace_start=0 - -[system.cpu0.fuPool.FUList0.opList0] +[system.cpu.fuPool.FUList0.opList0] type=OpDesc opClass=IntAlu opLat=1 issueLat=1 -[system.cpu0.fuPool.FUList0] +[system.cpu.fuPool.FUList0] type=FUDesc -opList=system.cpu0.fuPool.FUList0.opList0 +opList=system.cpu.fuPool.FUList0.opList0 count=6 -[system.cpu0.fuPool.FUList1.opList0] +[system.cpu.fuPool.FUList1.opList0] type=OpDesc opClass=IntMult opLat=3 issueLat=1 -[system.cpu0.fuPool.FUList1.opList1] +[system.cpu.fuPool.FUList1.opList1] type=OpDesc opClass=IntDiv opLat=20 issueLat=19 -[system.cpu0.fuPool.FUList1] +[system.cpu.fuPool.FUList1] type=FUDesc -opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 count=2 -[system.cpu0.fuPool.FUList2.opList0] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc opClass=FloatAdd opLat=2 issueLat=1 -[system.cpu0.fuPool.FUList2.opList1] +[system.cpu.fuPool.FUList2.opList1] type=OpDesc opClass=FloatCmp opLat=2 issueLat=1 -[system.cpu0.fuPool.FUList2.opList2] +[system.cpu.fuPool.FUList2.opList2] type=OpDesc opClass=FloatCvt opLat=2 issueLat=1 -[system.cpu0.fuPool.FUList2] +[system.cpu.fuPool.FUList2] type=FUDesc -opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 count=4 -[system.cpu0.fuPool.FUList3.opList0] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc opClass=FloatMult opLat=4 issueLat=1 -[system.cpu0.fuPool.FUList3.opList1] +[system.cpu.fuPool.FUList3.opList1] type=OpDesc opClass=FloatDiv opLat=12 issueLat=12 -[system.cpu0.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList2] type=OpDesc opClass=FloatSqrt opLat=24 issueLat=24 -[system.cpu0.fuPool.FUList3] +[system.cpu.fuPool.FUList3] type=FUDesc -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 count=2 -[system.cpu0.fuPool.FUList4.opList0] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc opClass=MemRead opLat=1 issueLat=1 -[system.cpu0.fuPool.FUList4] +[system.cpu.fuPool.FUList4] type=FUDesc -opList=system.cpu0.fuPool.FUList4.opList0 +opList=system.cpu.fuPool.FUList4.opList0 count=0 -[system.cpu0.fuPool.FUList5.opList0] +[system.cpu.fuPool.FUList5.opList0] type=OpDesc opClass=MemWrite opLat=1 issueLat=1 -[system.cpu0.fuPool.FUList5] +[system.cpu.fuPool.FUList5] type=FUDesc -opList=system.cpu0.fuPool.FUList5.opList0 +opList=system.cpu.fuPool.FUList5.opList0 count=0 -[system.cpu0.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc opClass=MemRead opLat=1 issueLat=1 -[system.cpu0.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList6.opList1] type=OpDesc opClass=MemWrite opLat=1 issueLat=1 -[system.cpu0.fuPool.FUList6] +[system.cpu.fuPool.FUList6] type=FUDesc -opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 count=4 -[system.cpu0.fuPool.FUList7.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc opClass=IprAccess opLat=3 issueLat=3 -[system.cpu0.fuPool.FUList7] +[system.cpu.fuPool.FUList7] type=FUDesc -opList=system.cpu0.fuPool.FUList7.opList0 +opList=system.cpu.fuPool.FUList7.opList0 count=1 -[system.cpu0.fuPool] +[system.cpu.fuPool] type=FUPool -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 -[system.cpu0] +[system.cpu] type=DerivO3CPU clock=1 numThreads=1 activity=0 workload=system.workload -mem=system.cpu0.mem -checker=system.cpu0.checker +mem=system.cpu.mem +checker=null max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 @@ -203,12 +189,12 @@ dispatchWidth=8 issueWidth=8 wbWidth=8 wbDepth=1 -fuPool=system.cpu0.fuPool +fuPool=system.cpu.fuPool iewToCommitDelay=1 renameToROBDelay=1 commitWidth=8 squashWidth=8 -trapLatency=6 +trapLatency=13 backComSize=5 forwardComSize=5 predType=tournament diff --git a/tests/test1/ref/alpha/detailed/m5stats.txt b/tests/test1/ref/alpha/detailed/m5stats.txt index 8ff727085..119cc8e9d 100644 --- a/tests/test1/ref/alpha/detailed/m5stats.txt +++ b/tests/test1/ref/alpha/detailed/m5stats.txt @@ -1,136 +1,135 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 45390 # Number of BTB hits -global.BPredUnit.BTBLookups 59902 # Number of BTB lookups -global.BPredUnit.RASInCorrect 85 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 3098 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 46029 # Number of conditional branches predicted -global.BPredUnit.lookups 70231 # Number of BP lookups -global.BPredUnit.usedRAS 7755 # Number of times the RAS was used to get a target. -host_inst_rate 69741 # Simulator instruction rate (inst/s) -host_mem_usage 148316 # Number of bytes of host memory used -host_seconds 7.17 # Real time elapsed on the host -host_tick_rate 36160 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15235 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 2693 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 145639 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 60928 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 47245 # Number of BTB hits +global.BPredUnit.BTBLookups 62226 # Number of BTB lookups +global.BPredUnit.RASInCorrect 88 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 3133 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 48198 # Number of conditional branches predicted +global.BPredUnit.lookups 72853 # Number of BP lookups +global.BPredUnit.usedRAS 7892 # Number of times the RAS was used to get a target. +host_inst_rate 90438 # Simulator instruction rate (inst/s) +host_mem_usage 148172 # Number of bytes of host memory used +host_seconds 5.53 # Real time elapsed on the host +host_tick_rate 35958 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 15372 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 1808 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 147140 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 63225 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500002 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 259259 # Number of ticks simulated -system.cpu0.checker.numCycles 518940 # number of cpu cycles simulated -system.cpu0.commit.COM:branches 61160 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 17172 # number cycles where commit BW limit reached -system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 251997 -system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 70509 2798.01% - 1 75489 2995.63% - 2 28876 1145.89% - 3 23224 921.60% - 4 21222 842.15% - 5 3198 126.91% - 6 8368 332.07% - 7 3939 156.31% - 8 17172 681.44% -system.cpu0.commit.COM:committed_per_cycle.max_value 8 -system.cpu0.commit.COM:committed_per_cycle.end_dist +sim_ticks 198813 # Number of ticks simulated +system.cpu.commit.COM:branches 61160 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 24524 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 189916 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 37455 1972.19% + 1 50343 2650.80% + 2 29014 1527.73% + 3 12786 673.25% + 4 19808 1042.99% + 5 2516 132.48% + 6 10075 530.50% + 7 3395 178.76% + 8 24524 1291.31% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu0.commit.COM:count 518948 # Number of instructions committed -system.cpu0.commit.COM:loads 131376 # Number of loads committed -system.cpu0.commit.COM:membars 0 # Number of memory barriers committed -system.cpu0.commit.COM:refs 189772 # Number of memory references committed -system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 2836 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 518948 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 44297 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 500002 # Number of Instructions Simulated -system.cpu0.committedInsts_total 500002 # Number of Instructions Simulated -system.cpu0.cpi 0.518516 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.518516 # CPI: Total CPI of All Threads -system.cpu0.decode.DECODE:BlockedCycles 743 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 281 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 16033 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 586219 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 143055 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 108199 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 7263 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 989 # Number of squashed instructions handled by decode -system.cpu0.fetch.Branches 70231 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 71036 # Number of cache lines fetched -system.cpu0.fetch.Cycles 180480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 962 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 594968 # Number of instructions fetch has processed -system.cpu0.fetch.SquashCycles 3140 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.270890 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 71036 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 53145 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 2.294870 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 259260 -system.cpu0.fetch.rateDist.min_value 0 - 0 149817 5778.64% - 1 3603 138.97% - 2 9058 349.38% - 3 10685 412.13% - 4 8455 326.12% - 5 18775 724.18% - 6 25664 989.89% - 7 6109 235.63% - 8 27094 1045.05% -system.cpu0.fetch.rateDist.max_value 8 -system.cpu0.fetch.rateDist.end_dist +system.cpu.commit.COM:count 518948 # Number of instructions committed +system.cpu.commit.COM:loads 131376 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 189772 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 2863 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 518948 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 18 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 59006 # The number of squashed insts skipped by commit +system.cpu.committedInsts 500002 # Number of Instructions Simulated +system.cpu.committedInsts_total 500002 # Number of Instructions Simulated +system.cpu.cpi 0.397624 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.397624 # CPI: Total CPI of All Threads +system.cpu.decode.DECODE:BlockedCycles 2191 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 297 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 16283 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 604200 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 76141 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 110735 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8898 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1017 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 849 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 72853 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 72795 # Number of cache lines fetched +system.cpu.fetch.Cycles 186280 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Insts 616104 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3180 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.366438 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 72795 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 55137 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 3.098896 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 198814 +system.cpu.fetch.rateDist.min_value 0 + 0 85330 4291.95% + 1 3737 187.96% + 2 9626 484.17% + 3 11018 554.19% + 4 8626 433.87% + 5 19021 956.72% + 6 27490 1382.70% + 7 6216 312.65% + 8 27750 1395.78% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist -system.cpu0.iew.EXEC:branches 64672 # Number of branches executed -system.cpu0.iew.EXEC:insts 526242 # Number of executed instructions -system.cpu0.iew.EXEC:loads 140576 # Number of load instructions executed -system.cpu0.iew.EXEC:nop 19405 # number of nop insts executed -system.cpu0.iew.EXEC:rate 2.029785 # Inst execution rate -system.cpu0.iew.EXEC:refs 200121 # number of memory reference insts executed -system.cpu0.iew.EXEC:squashedInsts 5760 # Number of squashed instructions skipped in execute -system.cpu0.iew.EXEC:stores 59545 # Number of stores executed -system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 394903 # num instructions consuming a value -system.cpu0.iew.WB:count 523588 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.746115 # average fanout of values written-back -system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 294643 # num instructions producing a value -system.cpu0.iew.WB:rate 2.019548 # insts written-back per cycle -system.cpu0.iew.WB:sent 524223 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 2948 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 145639 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 1523 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 60928 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 563297 # Number of instructions dispatched to IQ -system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 7263 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 18223 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 14246 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 2528 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 1750 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 1198 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 1.928581 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.928581 # IPC: Total IPC of All Threads -system.cpu0.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:(null).samples 0 -system.cpu0.iq.IQ:residence:(null).min_value 0 +system.cpu.iew.EXEC:branches 65998 # Number of branches executed +system.cpu.iew.EXEC:insts 534582 # Number of executed instructions +system.cpu.iew.EXEC:loads 141825 # Number of load instructions executed +system.cpu.iew.EXEC:nop 21827 # number of nop insts executed +system.cpu.iew.EXEC:rate 2.688855 # Inst execution rate +system.cpu.iew.EXEC:refs 202010 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 7038 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 60185 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 413743 # num instructions consuming a value +system.cpu.iew.WB:count 532886 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745847 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 308589 # num instructions producing a value +system.cpu.iew.WB:rate 2.680324 # insts written-back per cycle +system.cpu.iew.WB:sent 533753 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3004 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 147140 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1292 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 63225 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 578006 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8898 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 22061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 15747 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4825 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 48 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1801 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1203 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 2.514936 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.514936 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 0 0 2 0 4 0 @@ -181,12 +180,12 @@ system.cpu0.iq.IQ:residence:(null).min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:(null).max_value 0 -system.cpu0.iq.IQ:residence:(null).end_dist +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist -system.cpu0.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:IntAlu.samples 0 -system.cpu0.iq.IQ:residence:IntAlu.min_value 0 +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 0 0 2 0 4 0 @@ -237,12 +236,12 @@ system.cpu0.iq.IQ:residence:IntAlu.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:IntAlu.max_value 0 -system.cpu0.iq.IQ:residence:IntAlu.end_dist +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist -system.cpu0.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:IntMult.samples 0 -system.cpu0.iq.IQ:residence:IntMult.min_value 0 +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 0 0 2 0 4 0 @@ -293,12 +292,12 @@ system.cpu0.iq.IQ:residence:IntMult.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:IntMult.max_value 0 -system.cpu0.iq.IQ:residence:IntMult.end_dist +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist -system.cpu0.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:IntDiv.samples 0 -system.cpu0.iq.IQ:residence:IntDiv.min_value 0 +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 0 0 2 0 4 0 @@ -349,12 +348,12 @@ system.cpu0.iq.IQ:residence:IntDiv.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:IntDiv.max_value 0 -system.cpu0.iq.IQ:residence:IntDiv.end_dist +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist -system.cpu0.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatAdd.samples 0 -system.cpu0.iq.IQ:residence:FloatAdd.min_value 0 +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 0 0 2 0 4 0 @@ -405,12 +404,12 @@ system.cpu0.iq.IQ:residence:FloatAdd.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu0.iq.IQ:residence:FloatAdd.end_dist +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist -system.cpu0.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatCmp.samples 0 -system.cpu0.iq.IQ:residence:FloatCmp.min_value 0 +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 0 0 2 0 4 0 @@ -461,12 +460,12 @@ system.cpu0.iq.IQ:residence:FloatCmp.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu0.iq.IQ:residence:FloatCmp.end_dist +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist -system.cpu0.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatCvt.samples 0 -system.cpu0.iq.IQ:residence:FloatCvt.min_value 0 +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 0 0 2 0 4 0 @@ -517,12 +516,12 @@ system.cpu0.iq.IQ:residence:FloatCvt.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu0.iq.IQ:residence:FloatCvt.end_dist +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist -system.cpu0.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatMult.samples 0 -system.cpu0.iq.IQ:residence:FloatMult.min_value 0 +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 0 0 2 0 4 0 @@ -573,12 +572,12 @@ system.cpu0.iq.IQ:residence:FloatMult.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatMult.max_value 0 -system.cpu0.iq.IQ:residence:FloatMult.end_dist +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist -system.cpu0.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatDiv.samples 0 -system.cpu0.iq.IQ:residence:FloatDiv.min_value 0 +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 0 0 2 0 4 0 @@ -629,12 +628,12 @@ system.cpu0.iq.IQ:residence:FloatDiv.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu0.iq.IQ:residence:FloatDiv.end_dist +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist -system.cpu0.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu0.iq.IQ:residence:FloatSqrt.min_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 0 0 2 0 4 0 @@ -685,12 +684,12 @@ system.cpu0.iq.IQ:residence:FloatSqrt.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu0.iq.IQ:residence:FloatSqrt.end_dist +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist -system.cpu0.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:MemRead.samples 0 -system.cpu0.iq.IQ:residence:MemRead.min_value 0 +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 0 0 2 0 4 0 @@ -741,12 +740,12 @@ system.cpu0.iq.IQ:residence:MemRead.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:MemRead.max_value 0 -system.cpu0.iq.IQ:residence:MemRead.end_dist +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist -system.cpu0.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:MemWrite.samples 0 -system.cpu0.iq.IQ:residence:MemWrite.min_value 0 +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 0 0 2 0 4 0 @@ -797,12 +796,12 @@ system.cpu0.iq.IQ:residence:MemWrite.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:MemWrite.max_value 0 -system.cpu0.iq.IQ:residence:MemWrite.end_dist +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist -system.cpu0.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:IprAccess.samples 0 -system.cpu0.iq.IQ:residence:IprAccess.min_value 0 +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 0 0 2 0 4 0 @@ -853,12 +852,12 @@ system.cpu0.iq.IQ:residence:IprAccess.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:IprAccess.max_value 0 -system.cpu0.iq.IQ:residence:IprAccess.end_dist +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist -system.cpu0.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu0.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu0.iq.IQ:residence:InstPrefetch.min_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 0 0 2 0 4 0 @@ -909,12 +908,12 @@ system.cpu0.iq.IQ:residence:InstPrefetch.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu0.iq.IQ:residence:InstPrefetch.end_dist +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist -system.cpu0.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:(null)_delay.samples 0 -system.cpu0.iq.ISSUE:(null)_delay.min_value 0 +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 0 0 2 0 4 0 @@ -965,12 +964,12 @@ system.cpu0.iq.ISSUE:(null)_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:(null)_delay.max_value 0 -system.cpu0.iq.ISSUE:(null)_delay.end_dist +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist -system.cpu0.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu0.iq.ISSUE:IntAlu_delay.min_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 0 0 2 0 4 0 @@ -1021,12 +1020,12 @@ system.cpu0.iq.ISSUE:IntAlu_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu0.iq.ISSUE:IntAlu_delay.end_dist +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist -system.cpu0.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:IntMult_delay.samples 0 -system.cpu0.iq.ISSUE:IntMult_delay.min_value 0 +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 0 0 2 0 4 0 @@ -1077,12 +1076,12 @@ system.cpu0.iq.ISSUE:IntMult_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu0.iq.ISSUE:IntMult_delay.end_dist +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist -system.cpu0.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu0.iq.ISSUE:IntDiv_delay.min_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 0 0 2 0 4 0 @@ -1133,12 +1132,12 @@ system.cpu0.iq.ISSUE:IntDiv_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu0.iq.ISSUE:IntDiv_delay.end_dist +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist -system.cpu0.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu0.iq.ISSUE:FloatAdd_delay.min_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 0 0 2 0 4 0 @@ -1189,12 +1188,12 @@ system.cpu0.iq.ISSUE:FloatAdd_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatAdd_delay.end_dist +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist -system.cpu0.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu0.iq.ISSUE:FloatCmp_delay.min_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 0 0 2 0 4 0 @@ -1245,12 +1244,12 @@ system.cpu0.iq.ISSUE:FloatCmp_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatCmp_delay.end_dist +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist -system.cpu0.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu0.iq.ISSUE:FloatCvt_delay.min_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 0 0 2 0 4 0 @@ -1301,12 +1300,12 @@ system.cpu0.iq.ISSUE:FloatCvt_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatCvt_delay.end_dist +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist -system.cpu0.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu0.iq.ISSUE:FloatMult_delay.min_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 0 0 2 0 4 0 @@ -1357,12 +1356,12 @@ system.cpu0.iq.ISSUE:FloatMult_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatMult_delay.end_dist +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist -system.cpu0.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu0.iq.ISSUE:FloatDiv_delay.min_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 0 0 2 0 4 0 @@ -1413,12 +1412,12 @@ system.cpu0.iq.ISSUE:FloatDiv_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatDiv_delay.end_dist +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist -system.cpu0.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 0 0 2 0 4 0 @@ -1469,12 +1468,12 @@ system.cpu0.iq.ISSUE:FloatSqrt_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu0.iq.ISSUE:FloatSqrt_delay.end_dist +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist -system.cpu0.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:MemRead_delay.samples 0 -system.cpu0.iq.ISSUE:MemRead_delay.min_value 0 +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 0 0 2 0 4 0 @@ -1525,12 +1524,12 @@ system.cpu0.iq.ISSUE:MemRead_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu0.iq.ISSUE:MemRead_delay.end_dist +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist -system.cpu0.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu0.iq.ISSUE:MemWrite_delay.min_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 0 0 2 0 4 0 @@ -1581,12 +1580,12 @@ system.cpu0.iq.ISSUE:MemWrite_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu0.iq.ISSUE:MemWrite_delay.end_dist +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist -system.cpu0.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu0.iq.ISSUE:IprAccess_delay.min_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 0 0 2 0 4 0 @@ -1637,12 +1636,12 @@ system.cpu0.iq.ISSUE:IprAccess_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu0.iq.ISSUE:IprAccess_delay.end_dist +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist -system.cpu0.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu0.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 0 0 2 0 4 0 @@ -1693,13 +1692,13 @@ system.cpu0.iq.ISSUE:InstPrefetch_delay.min_value 0 94 0 96 0 98 0 -system.cpu0.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu0.iq.ISSUE:InstPrefetch_delay.end_dist +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist -system.cpu0.iq.ISSUE:FU_type_0 532005 # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.start_dist +system.cpu.iq.ISSUE:FU_type_0 541621 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 329259 61.89% # Type of FU issued + IntAlu 336144 62.06% # Type of FU issued IntMult 10 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 13 0.00% # Type of FU issued @@ -1708,16 +1707,16 @@ system.cpu0.iq.ISSUE:FU_type_0.start_dist FloatMult 2 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 142868 26.85% # Type of FU issued - MemWrite 59850 11.25% # Type of FU issued + MemRead 144008 26.59% # Type of FU issued + MemWrite 61441 11.34% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.end_dist -system.cpu0.iq.ISSUE:fu_busy_cnt 5510 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.010357 # FU busy rate (busy events/executed inst) -system.cpu0.iq.ISSUE:fu_full.start_dist +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 10389 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.019181 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1663 30.18% # attempts to use FU when none available + IntAlu 6229 59.96% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -1726,50 +1725,50 @@ system.cpu0.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 2693 48.87% # attempts to use FU when none available - MemWrite 1154 20.94% # attempts to use FU when none available + MemRead 2497 24.04% # attempts to use FU when none available + MemWrite 1663 16.01% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle.samples 259260 -system.cpu0.iq.ISSUE:issued_per_cycle.min_value 0 - 0 59185 2282.84% - 1 72964 2814.32% - 2 38364 1479.75% - 3 33144 1278.41% - 4 19818 764.41% - 5 14624 564.07% - 6 18233 703.27% - 7 2333 89.99% - 8 595 22.95% -system.cpu0.iq.ISSUE:issued_per_cycle.max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle.end_dist +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 198814 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 27333 1374.80% + 1 36906 1856.31% + 2 35716 1796.45% + 3 28916 1454.42% + 4 31868 1602.91% + 5 13027 655.24% + 6 21677 1090.32% + 7 3102 156.03% + 8 269 13.53% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu0.iq.ISSUE:rate 2.052013 # Inst issue rate -system.cpu0.iq.iqInstsAdded 543865 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 532005 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 42716 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 611 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 21818 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.numCycles 259260 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 191 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 144885 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 336 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 753146 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 577319 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 432146 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 106374 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 7263 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 302 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 46034 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 245 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 34 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 421 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 32 # count of temporary serializing insts renamed +system.cpu.iq.ISSUE:rate 2.724260 # Inst issue rate +system.cpu.iq.iqInstsAdded 556152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 541621 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 55198 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 404 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 27398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.numCycles 198814 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 266 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 386063 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 78342 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1401 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 775201 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 594947 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 443127 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 109388 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8898 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1662 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 57015 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 258 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 41 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4872 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed system.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/detailed/stdout b/tests/test1/ref/alpha/detailed/stdout index 2c46aa4f2..464796932 100644 --- a/tests/test1/ref/alpha/detailed/stdout +++ b/tests/test1/ref/alpha/detailed/stdout @@ -7,8 +7,7 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 19 2006 15:49:01 -M5 started Wed Jul 19 15:49:12 2006 +M5 compiled Jul 21 2006 16:19:30 +M5 started Fri Jul 21 16:41:07 2006 M5 executing on zamp.eecs.umich.edu -Creating SE system -Exiting @ tick 259259 because a thread reached the max instruction count +Exiting @ tick 198813 because a thread reached the max instruction count diff --git a/tests/test1/ref/alpha/timing/config.ini b/tests/test1/ref/alpha/timing/config.ini index 58dc6741b..c4c381b93 100644 --- a/tests/test1/ref/alpha/timing/config.ini +++ b/tests/test1/ref/alpha/timing/config.ini @@ -48,11 +48,11 @@ text_file=m5stats.txt [system] type=System -children=cpu0 physmem workload +children=cpu physmem workload mem_mode=atomic physmem=system.physmem -[system.cpu0] +[system.cpu] type=TimingSimpleCPU children=mem clock=1 @@ -63,11 +63,11 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu0.mem +mem=system.cpu.mem system=system workload=system.workload -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 diff --git a/tests/test1/ref/alpha/timing/config.out b/tests/test1/ref/alpha/timing/config.out index b28de6f74..882db9c06 100644 --- a/tests/test1/ref/alpha/timing/config.out +++ b/tests/test1/ref/alpha/timing/config.out @@ -23,17 +23,17 @@ chkpt= output=cout system=system -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 -[system.cpu0] +[system.cpu] type=TimingSimpleCPU max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 -mem=system.cpu0.mem +mem=system.cpu.mem system=system workload=system.workload clock=1 diff --git a/tests/test1/ref/alpha/timing/m5stats.txt b/tests/test1/ref/alpha/timing/m5stats.txt index 64d05099f..5f7766bac 100644 --- a/tests/test1/ref/alpha/timing/m5stats.txt +++ b/tests/test1/ref/alpha/timing/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 739858 # Simulator instruction rate (inst/s) -host_mem_usage 147760 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host -host_tick_rate 1006609 # Simulator tick rate (ticks/s) +host_inst_rate 781730 # Simulator instruction rate (inst/s) +host_mem_usage 147616 # Number of bytes of host memory used +host_seconds 0.64 # Real time elapsed on the host +host_tick_rate 1063244 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 680774 # Number of ticks simulated -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 500000 # Number of instructions executed -system.cpu0.num_refs 182203 # Number of memory references +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.num_insts 500000 # Number of instructions executed +system.cpu.num_refs 182203 # Number of memory references system.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/test1/ref/alpha/timing/stdout b/tests/test1/ref/alpha/timing/stdout index 980af1477..c5591df61 100644 --- a/tests/test1/ref/alpha/timing/stdout +++ b/tests/test1/ref/alpha/timing/stdout @@ -7,8 +7,7 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 19 2006 15:49:01 -M5 started Wed Jul 19 15:49:19 2006 +M5 compiled Jul 21 2006 16:19:30 +M5 started Fri Jul 21 16:19:43 2006 M5 executing on zamp.eecs.umich.edu -Creating SE system Exiting @ tick 680774 because a thread reached the max instruction count |