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-rw-r--r--src/arch/arm/intregs.hh2
-rw-r--r--src/arch/arm/isa/operands.isa6
2 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 191965c55..78ad39ee2 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -102,6 +102,8 @@ enum IntRegIndex
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
+ INTREG_RHI,
+ INTREG_RLO,
NUM_INTREGS,
NUM_ARCH_INTREGS = INTREG_PC + 1,
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index a4c404bd5..4ac6790e5 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -63,9 +63,9 @@ def operands {{
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
- 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
- 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
- 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
+ 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
+ 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
+ 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),