diff options
| -rw-r--r-- | arch/alpha/isa_desc | 4 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 12 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 40 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 11 |
4 files changed, 57 insertions, 10 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index a7665210f..56e7cb31c 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -5,7 +5,7 @@ let {{ global rcs_id - rcs_id = "$Id$" + rcs_id = "$Id: s.isa_desc 1.43 04/02/29 22:41:10-05:00 ehallnor@zazzer.eecs.umich.edu $" }}; @@ -1854,6 +1854,7 @@ decode OPCODE default Unknown::unknown() { 0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }}); 0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED); 0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED); + {{fault = memAccessObj->copySrcTranslate(EA);}}, //0x20: copy_load({{EA = Ra;}}, // {{memAccessObj->copySrcTranslate(EA);}}, // IsMemRef, IsLoad, IsCopy); @@ -1876,6 +1877,7 @@ decode OPCODE default Unknown::unknown() { 0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }}); 0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }}); + {{fault =memAccessObj->copy(EA);}}, //0x24: copy_store({{EA = Rb;}}, // {{memAccessObj->copy(EA);}}, // IsMemRef, IsStore, IsCopy); diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index a4bbdd484..a72516ac7 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -147,6 +147,18 @@ class ExecContext #endif + /** + * Temporary storage to pass the source address from copy_load to + * copy_store. + * @todo Remove this temporary when we have a better way to do it. + */ + Addr copySrcAddr; + /** + * Temp storage for the physical source address of a copy. + * @todo Remove this temporary when we have a better way to do it. + */ + Addr copySrcPhysAddr; + /* * number of executed instructions, for matching with syscall trace diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index c25a95775..c2796efd0 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -327,6 +327,46 @@ change_thread_state(int thread_number, int activate, int priority) { } +Fault +SimpleCPU::copySrcTranslate(Addr src) +{ + memReq->reset(src, (dcacheInterface) ? + dcacheInterface->getBlockSize() + : 64); + + // translate to physical address + Fault fault = xc->translateDataReadReq(memReq); + + if (fault == No_Fault) { + xc->copySrcAddr = src; + xc->copySrcPhysAddr = memReq->paddr; + } else { + xc->copySrcAddr = 0; + xc->copySrcPhysAddr = 0; + } + return fault; +} + +Fault +SimpleCPU::copy(Addr dest) +{ + int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; + uint8_t data[blk_size]; + assert(xc->copySrcPhysAddr); + memReq->reset(dest, blk_size); + // translate to physical address + Fault fault = xc->translateDataWriteReq(memReq); + if (fault == No_Fault) { + Addr dest_addr = memReq->paddr; + // Need to read straight from memory since we have more than 8 bytes. + memReq->paddr = xc->copySrcPhysAddr; + xc->mem->read(memReq, data); + memReq->paddr = dest_addr; + xc->mem->write(memReq, data); + } + return fault; +} + // precise architected memory state accessor macros template <class T> Fault diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 4bdc69ad1..9edd66ab4 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -247,16 +247,9 @@ class SimpleCPU : public BaseCPU // need to do this... } - void copySrcTranslate(Addr src) - { - panic("Haven't implemented Copy Src translate yet in SimpleCPU\n"); - } - - void copy(Addr dest) - { - panic("Haven't implemented Copy yet in SimpleCPU\n"); - } + Fault copySrcTranslate(Addr src); + Fault copy(Addr dest); }; #endif // __SIMPLE_CPU_HH__ |