diff options
47 files changed, 775 insertions, 1022 deletions
diff --git a/src/SConscript b/src/SConscript index d6b4c6c8d..c93605ff7 100644 --- a/src/SConscript +++ b/src/SConscript @@ -79,6 +79,7 @@ base_sources = Split(''' base/loader/object_file.cc base/loader/symtab.cc base/stats/events.cc + base/stats/output.cc base/stats/statdb.cc base/stats/visit.cc base/stats/text.cc @@ -134,6 +135,7 @@ base_sources = Split(''' python/swig/main_wrap.cc python/swig/event_wrap.cc python/swig/random_wrap.cc + python/swig/stats_wrap.cc python/swig/trace_wrap.cc python/swig/pyevent.cc @@ -148,7 +150,6 @@ base_sources = Split(''' sim/sim_events.cc sim/sim_object.cc sim/startup.cc - sim/stat_context.cc sim/stat_control.cc sim/system.cc ''') diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 2b1b327e5..8168473a1 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2839,6 +2839,7 @@ class Temp */ void check(); +void dump(); void reset(); void registerResetCallback(Callback *cb); diff --git a/src/base/stats/events.cc b/src/base/stats/events.cc index 6ecc5434c..fa746eab8 100644 --- a/src/base/stats/events.cc +++ b/src/base/stats/events.cc @@ -52,8 +52,6 @@ namespace Stats { Tick EventStart = ULL(0x7fffffffffffffff); -ObjectMatch event_ignore; - #if USE_MYSQL class InsertEvent { diff --git a/src/base/stats/events.hh b/src/base/stats/events.hh index b09b91c7c..dc1408f5b 100644 --- a/src/base/stats/events.hh +++ b/src/base/stats/events.hh @@ -45,8 +45,6 @@ void __event(const std::string &stat); bool MySqlConnected(); #endif -bool ignoreEvent(const std::string &name); - inline void recordEvent(const std::string &stat) { diff --git a/src/base/stats/mysql.cc b/src/base/stats/mysql.cc index 0fb31f4ce..01a82c4bf 100644 --- a/src/base/stats/mysql.cc +++ b/src/base/stats/mysql.cc @@ -49,14 +49,6 @@ using namespace std; namespace Stats { -MySqlRun MySqlDB; - -bool -MySqlConnected() -{ - return MySqlDB.connected(); -} - void MySqlRun::connect(const string &host, const string &user, const string &passwd, const string &db, const string &name, const string &sample, @@ -198,7 +190,7 @@ SetupStat::init() unsigned SetupStat::setup() { - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); stringstream insert; ccprintf(insert, @@ -317,7 +309,7 @@ void InsertData::flush() { if (size) { - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); assert(mysql.connected()); mysql.query(query); if (mysql.error) @@ -349,7 +341,7 @@ InsertData::insert() first = false; size += sprintf(query + size, "(%u,%d,%d,%u,%llu,\"%f\")", - stat, x, y, MySqlDB.run(), (unsigned long long)tick, + stat, x, y, run->run(), (unsigned long long)tick, data); } @@ -367,7 +359,7 @@ struct InsertSubData void InsertSubData::setup() { - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); assert(mysql.connected()); stringstream insert; ccprintf(insert, @@ -386,7 +378,7 @@ InsertSubData::setup() void InsertFormula(uint16_t stat, const string &formula) { - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); assert(mysql.connected()); stringstream insert_formula; ccprintf(insert_formula, @@ -400,7 +392,7 @@ InsertFormula(uint16_t stat, const string &formula) stringstream insert_ref; ccprintf(insert_ref, "INSERT INTO formula_ref(fr_stat,fr_run) values(%d, %d)", - stat, MySqlDB.run()); + stat, run->run()); mysql.query(insert_ref); // if (mysql.error) @@ -413,7 +405,7 @@ InsertFormula(uint16_t stat, const string &formula) void UpdatePrereq(uint16_t stat, uint16_t prereq) { - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); assert(mysql.connected()); stringstream update; ccprintf(update, "UPDATE stats SET st_prereq=%d WHERE st_id=%d", @@ -426,6 +418,29 @@ UpdatePrereq(uint16_t stat, uint16_t prereq) panic("could not commit transaction\n%s\n", mysql.error); } +MySql::MySql() + : run(new MySqlRun) +{} + +MySql::~MySql() +{ + delete run; +} + +void +MySql::connect(const string &host, const string &user, const string &passwd, + const string &db, const string &name, const string &sample, + const string &project) +{ + run->connect(host, user, passwd, db, name, sample, project); +} + +bool +MySql::connected() const +{ + run->connected(); +} + void MySql::configure() { @@ -434,7 +449,7 @@ MySql::configure() */ using namespace Database; - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); stat_list_t::const_iterator i, end = stats().end(); for (i = stats().begin(); i != end; ++i) { @@ -605,7 +620,7 @@ MySql::configure(const FormulaData &data) bool MySql::valid() const { - return MySqlDB.connected(); + return run->connected(); } void @@ -620,7 +635,7 @@ MySql::output() // store sample # newdata.tick = curTick; - MySQL::Connection &mysql = MySqlDB.conn(); + MySQL::Connection &mysql = run->conn(); Database::stat_list_t::const_iterator i, end = Database::stats().end(); for (i = Database::stats().begin(); i != end; ++i) { @@ -825,4 +840,21 @@ MySql::visit(const FormulaData &data) output(data); } -/* namespace Stats */ } +bool +initMySQL(string host, string user, string password, string database, + string name, string sample, string project) +{ + extern list<Output *> OutputList; + static MySql mysql; + + if (mysql.connected()) + return false; + + if (user.empty()) + user = username(); + + mysql.connect(host, user, password, database, name, sample, project); + OutputList.push_back(&mysql); + + return true; +} diff --git a/src/base/stats/mysql.hh b/src/base/stats/mysql.hh index 50f7d9e97..a43c74ecc 100644 --- a/src/base/stats/mysql.hh +++ b/src/base/stats/mysql.hh @@ -35,14 +35,13 @@ #include <string> #include "base/stats/output.hh" +#include "config/use_mysql.hh" namespace MySQL { class Connection; } namespace Stats { class DistDataData; class MySqlRun; -bool MySqlConnected(); -extern MySqlRun MySqlDB; struct SetupStat { @@ -95,6 +94,9 @@ class InsertData class MySql : public Output { protected: + MySqlRun *run; /* Hide the implementation so we don't have a + #include mess */ + SetupStat stat; InsertData newdata; std::list<FormulaData *> formulas; @@ -116,6 +118,17 @@ class MySql : public Output assert(i != idmap.end()); return (*i).second; } + + public: + MySql(MySqlRun &_run){} + ~MySql(); + + void connect(const std::string &host, const std::string &user, + const std::string &passwd, const std::string &db, + const std::string &name, const std::string &sample, + const std::string &project); + bool connected() const; + public: // Implement Visit virtual void visit(const ScalarData &data); @@ -149,6 +162,20 @@ class MySql : public Output void configure(const FormulaData &data); }; +bool initMySQL(std::string host, std::string database, std::string user = "", + std::string passwd = "", std::string name = "test", + std::string sample = "0", std::string project = "test"); + +#if !USE_MYSQL +inline bool +initMySQL(std::string host, std::string user, std::string password, + std::string database, std::string name, std::string sample, + std::string project) +{ + return false; +} +#endif + /* namespace Stats */ } #endif // __BASE_STATS_MYSQL_HH__ diff --git a/src/base/stats/output.cc b/src/base/stats/output.cc new file mode 100644 index 000000000..9f2b91c77 --- /dev/null +++ b/src/base/stats/output.cc @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include <list> + +#include "base/stats/output.hh" +#include "sim/eventq.hh" +#include "sim/host.hh" + +using namespace std; + +namespace Stats { + +Tick lastDump(0); +list<Output *> OutputList; + +void +dump() +{ + assert(lastDump <= curTick); + if (lastDump == curTick) + return; + lastDump = curTick; + + list<Output *>::iterator i = OutputList.begin(); + list<Output *>::iterator end = OutputList.end(); + for (; i != end; ++i) { + Output *output = *i; + if (!output->valid()) + continue; + + output->output(); + } +} + +/* namespace Stats */ } + +void +debugDumpStats() +{ + Stats::dump(); +} + diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc index ae0d65537..66c5955d7 100644 --- a/src/base/stats/text.cc +++ b/src/base/stats/text.cc @@ -725,4 +725,25 @@ Text::visit(const FormulaData &data) visit((const VectorData &)data); } +bool +initText(const string &filename, bool desc, bool compat) +{ + static Text text; + static bool connected = false; + + if (connected) + return false; + + extern list<Output *> OutputList; + + text.open(*simout.find(filename)); + text.descriptions = desc; + text.compat = compat; + OutputList.push_back(&text); + connected = true; + + return true; +} + + /* namespace Stats */ } diff --git a/src/base/stats/text.hh b/src/base/stats/text.hh index b3faf5ad5..0516bc60d 100644 --- a/src/base/stats/text.hh +++ b/src/base/stats/text.hh @@ -34,6 +34,7 @@ #include <iosfwd> #include <string> +#include "base/output.hh" #include "base/stats/output.hh" namespace Stats { @@ -73,6 +74,8 @@ class Text : public Output virtual void output(); }; +bool initText(const std::string &filename, bool desc=true, bool compat=true); + /* namespace Stats */ } #endif // __BASE_STATS_TEXT_HH__ diff --git a/src/base/trace.cc b/src/base/trace.cc index 7afb038be..2dde1f688 100644 --- a/src/base/trace.cc +++ b/src/base/trace.cc @@ -47,7 +47,7 @@ using namespace std; namespace Trace { const string DefaultName("global"); FlagVec flags(NumFlags, false); -bool enabled = true; +bool enabled = false; // // This variable holds the output stream for debug information. Other diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 897bf0023..ba6aa6af8 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -253,7 +253,7 @@ def gen_hh(filename): print >>hhfile, ''' // The remaining enum values are *not* valid indices for Trace::flags. // They are "compound" flags, which correspond to sets of base - // flags, and are used only by TraceParamContext::setFlags(). + // flags, and are used by changeFlag. ''', for flag in compoundFlags: diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 8440d2320..d5a023c59 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -63,7 +63,7 @@ int maxThreadsPerCPU = 1; CPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu) - : Event(q, Event::Stat_Event_Pri), interval(ival), + : Event(q, Event::Progress_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu) { if (interval) diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index be10b4a6a..0f642c08e 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -157,6 +157,9 @@ getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, if (!IsOn(ExecEnable)) return NULL; + if (!Trace::enabled) + return NULL; + if (!IsOn(ExecSpeculative) && tc->misspeculating()) return NULL; diff --git a/src/python/SConscript b/src/python/SConscript index 51271650f..4dd614cfb 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -110,6 +110,7 @@ swig_it('main') swig_it('debug') swig_it('event') swig_it('random') +swig_it('stats') swig_it('trace') # Action function to build the zip archive. Uses the PyZipFile module diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 934358298..ba79d3729 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -653,15 +653,13 @@ class SimObject(object): instanceDict[self.path()] = self - if hasattr(self, 'type') and not isinstance(self, ParamContext): + if hasattr(self, 'type'): print 'type=%s' % self.type child_names = self._children.keys() child_names.sort() - np_child_names = [c for c in child_names \ - if not isinstance(self._children[c], ParamContext)] - if len(np_child_names): - print 'children=%s' % ' '.join(np_child_names) + if len(child_names): + print 'children=%s' % ' '.join(child_names) param_names = self._params.keys() param_names.sort() @@ -711,8 +709,7 @@ class SimObject(object): def startDrain(self, drain_event, recursive): count = 0 - # ParamContexts don't serialize - if isinstance(self, SimObject) and not isinstance(self, ParamContext): + if isinstance(self, SimObject): count += self._ccObject.drain(drain_event) if recursive: for child in self._children.itervalues(): @@ -720,7 +717,7 @@ class SimObject(object): return count def resume(self): - if isinstance(self, SimObject) and not isinstance(self, ParamContext): + if isinstance(self, SimObject): self._ccObject.resume() for child in self._children.itervalues(): child.resume() @@ -782,9 +779,6 @@ class SimObject(object): for c in self.children: c.outputDot(dot) -class ParamContext(SimObject): - pass - # Function to provide to C++ so it can look up instances based on paths def resolveSimObject(name): obj = instanceDict[name] @@ -793,7 +787,7 @@ def resolveSimObject(name): # __all__ defines the list of symbols that get exported when # 'from config import *' is invoked. Try to keep this reasonably # short to avoid polluting other namespaces. -__all__ = ['SimObject', 'ParamContext'] +__all__ = ['SimObject'] # see comment on imports at end of __init__.py. import proxy diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 25b52e830..48c75434f 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -264,7 +264,7 @@ def main(): import objects # set stats options - objects.Statistics.text_file = options.stats_file + internal.stats.initText(options.stats_file) # set debugging options for when in options.debug_break: @@ -292,11 +292,12 @@ def main(): for flag in off_flags: internal.trace.clear(flag) - if options.trace_start is not None: - internal.trace.enabled = False + if options.trace_start: def enable_trace(): - internal.event.enabled = True - internal.event.create(enable_trace, options.trace_start) + internal.trace.cvar.enabled = True + internal.event.create(enable_trace, int(options.trace_start)) + else: + internal.trace.enabled = True internal.trace.output(options.trace_file) diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index c78ae6ccb..8db4fa5a2 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -1,8 +1,5 @@ from m5.SimObject import SimObject from m5.params import * -from Serialize import Serialize -from Serialize import Statreset -from Statistics import Statistics class Root(SimObject): type = 'Root' @@ -12,7 +9,3 @@ class Root(SimObject): "print a progress message every n ticks (0 = never)") output_file = Param.String('cout', "file to dump simulator output to") checkpoint = Param.String('', "checkpoint file to load") -# stats = Param.Statistics(Statistics(), "statistics object") -# serialize = Param.Serialize(Serialize(), "checkpoint generation options") - stats = Statistics() - serialize = Serialize() diff --git a/src/python/swig/pyevent.cc b/src/python/swig/pyevent.cc index 6fb7d3f17..7f23b8874 100644 --- a/src/python/swig/pyevent.cc +++ b/src/python/swig/pyevent.cc @@ -31,6 +31,7 @@ #include <Python.h> #include "python/swig/pyevent.hh" +#include "sim/async.hh" PythonEvent::PythonEvent(PyObject *obj, Tick when, Priority priority) : Event(&mainEventQueue, priority), object(obj) @@ -52,9 +53,9 @@ PythonEvent::~PythonEvent() void PythonEvent::process() { - PyObject *result; - - result = PyObject_CallMethod(object, "process", ""); + PyObject *args = PyTuple_New(0); + PyObject *result = PyObject_Call(object, args, NULL); + Py_DECREF(args); if (result) { // Nothing to do just decrement the reference count @@ -62,5 +63,7 @@ PythonEvent::process() } else { // Somethign should be done to signal back to the main interpreter // that there's been an exception. + async_event = true; + async_exception = true; } } diff --git a/src/python/swig/stats.i b/src/python/swig/stats.i new file mode 100644 index 000000000..d6b39c2cb --- /dev/null +++ b/src/python/swig/stats.i @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +%module stats + +%include "std_string.i" + +%{ +#include "base/statistics.hh" +#include "base/stats/mysql.hh" +#include "base/stats/text.hh" +#include "sim/stat_control.hh" +%} + +namespace Stats { +void initSimStats(); +void initText(const std::string &filename, bool desc=true, bool compat=true); +void initMySQL(std::string host, std::string database, std::string user = "", + std::string passwd = "", std::string name = "test", + std::string sample = "0", std::string project = "test"); + +void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0); + +void dump(); +void reset(); + +/* namespace Stat */ } + +%wrapper %{ +// fix up module name to reflect the fact that it's inside the m5 package +#undef SWIG_name +#define SWIG_name "m5.internal._stats" +%} diff --git a/src/sim/async.hh b/src/sim/async.hh index 50ae73040..6ee5eb46a 100644 --- a/src/sim/async.hh +++ b/src/sim/async.hh @@ -47,6 +47,7 @@ extern volatile bool async_dump; ///< Async request to dump stats. extern volatile bool async_exit; ///< Async request to exit simulator. extern volatile bool async_io; ///< Async I/O request (SIGIO). extern volatile bool async_alarm; ///< Async alarm event (SIGALRM). +extern volatile bool async_exception; ///< Python exception. //@} #endif // __ASYNC_HH__ diff --git a/src/sim/builder.cc b/src/sim/builder.cc index 9074cc899..8ef54ce52 100644 --- a/src/sim/builder.cc +++ b/src/sim/builder.cc @@ -40,7 +40,7 @@ using namespace std; SimObjectBuilder::SimObjectBuilder(const std::string &_iniSection) - : ParamContext(_iniSection, NoAutoInit) + : ParamContext(_iniSection) { } diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 1aeb26e25..a57e9077e 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -169,6 +169,9 @@ class Event : public Serializable, public FastAlloc /// everything else, but before exit. Stat_Event_Pri = 90, + /// Progress events come at the end. + Progress_Event_Pri = 95, + /// If we want to exit on this cycle, it's the very last thing /// we do. Sim_Exit_Pri = 100 diff --git a/src/sim/main.cc b/src/sim/main.cc index 9f9a56450..8e47ac6a0 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -53,6 +53,7 @@ #include "base/output.hh" #include "base/pollevent.hh" #include "base/statistics.hh" +#include "base/stats/output.hh" #include "base/str.hh" #include "base/time.hh" #include "config/pythonhome.hh" @@ -82,6 +83,7 @@ volatile bool async_dumpreset = false; volatile bool async_exit = false; volatile bool async_io = false; volatile bool async_alarm = false; +volatile bool async_exception = false; /// Stats signal handler. void @@ -219,7 +221,7 @@ loadIniFile(PyObject *_resolveFunc) inifile.load(simout.resolve("config.ini")); // Initialize statistics database - Stats::InitSimStats(); + Stats::initSimStats(); } @@ -270,13 +272,6 @@ connectPorts(SimObject *o1, const std::string &name1, int i1, void finalInit() { - // Parse and check all non-config-hierarchy parameters. - ParamContext::parseAllContexts(inifile); - ParamContext::checkAllContexts(); - - // Echo all parameter settings to stats file as well. - ParamContext::showAllContexts(*configStream); - // Do a second pass to finish initializing the sim objects SimObject::initAll(); @@ -296,7 +291,6 @@ finalInit() SimStartup(); } - /** Simulate for num_cycles additional cycles. If num_cycles is -1 * (the default), do not limit simulation; some other event must * terminate the loop. Exported to Python via SWIG. @@ -349,16 +343,12 @@ simulate(Tick num_cycles = MaxTick) async_event = false; if (async_dump) { async_dump = false; - - using namespace Stats; - SetupEvent(Dump, curTick); + Stats::StatEvent(true, false); } if (async_dumpreset) { async_dumpreset = false; - - using namespace Stats; - SetupEvent(Dump | Reset, curTick); + Stats::StatEvent(true, true); } if (async_exit) { @@ -371,6 +361,11 @@ simulate(Tick num_cycles = MaxTick) async_alarm = false; pollQueue.service(); } + + if (async_exception) { + async_exception = false; + return NULL; + } } } @@ -460,8 +455,6 @@ doExitCleanup() cout.flush(); - ParamContext::cleanupAllContexts(); - // print simulation stats - Stats::DumpNow(); + Stats::dump(); } diff --git a/src/sim/param.cc b/src/sim/param.cc index 5cc69b161..51d389f5a 100644 --- a/src/sim/param.cc +++ b/src/sim/param.cc @@ -583,30 +583,10 @@ SimObjectBaseParam::parse(const string &s, vector<SimObject *>&value) // //////////////////////////////////////////////////////////////////////// -list<ParamContext *> *ParamContext::ctxList = NULL; - -ParamContext::ParamContext(const string &_iniSection, InitPhase _initPhase) +ParamContext::ParamContext(const string &_iniSection) : iniFilePtr(NULL), // initialized on call to parseParams() - iniSection(_iniSection), paramList(NULL), - initPhase(_initPhase) -{ - // Put this context on global list for initialization - if (initPhase != NoAutoInit) { - if (ctxList == NULL) - ctxList = new list<ParamContext *>(); - - // keep list sorted by ascending initPhase values - list<ParamContext *>::iterator i = ctxList->begin(); - list<ParamContext *>::iterator end = ctxList->end(); - for (; i != end; ++i) { - if (initPhase <= (*i)->initPhase) { - // found where we want to insert - break; - } - } - // (fall through case: insert at end) - ctxList->insert(i, this); - } + iniSection(_iniSection), paramList(NULL) +{ } @@ -695,89 +675,6 @@ ParamContext::printErrorProlog(ostream &os) os << "Parameter error in section [" << iniSection << "]: " << endl; } -// -// static method: call parseParams() on all registered contexts -// -void -ParamContext::parseAllContexts(IniFile &iniFile) -{ - list<ParamContext *>::iterator iter; - - for (iter = ctxList->begin(); iter != ctxList->end(); ++iter) { - ParamContext *pc = *iter; - - pc->parseParams(iniFile); - } -} - - -// -// static method: call checkParams() on all registered contexts -// -void -ParamContext::checkAllContexts() -{ - list<ParamContext *>::iterator iter; - - for (iter = ctxList->begin(); iter != ctxList->end(); ++iter) { - ParamContext *pc = *iter; - - pc->checkParams(); - } -} - - -// -// static method: call showParams() on all registered contexts -// -void -ParamContext::showAllContexts(ostream &os) -{ - list<ParamContext *>::iterator iter; - - for (iter = ctxList->begin(); iter != ctxList->end(); ++iter) { - ParamContext *pc = *iter; - - os << "[" << pc->iniSection << "]" << endl; - pc->showParams(os); - os << endl; - } -} - - -// -// static method: call cleanup() on all registered contexts -// -void -ParamContext::cleanupAllContexts() -{ - list<ParamContext *>::iterator iter; - - for (iter = ctxList->begin(); iter != ctxList->end(); ++iter) { - ParamContext *pc = *iter; - - pc->cleanup(); - } -} - - -// -// static method: call describeParams() on all registered contexts -// -void -ParamContext::describeAllContexts(ostream &os) -{ - list<ParamContext *>::iterator iter; - - for (iter = ctxList->begin(); iter != ctxList->end(); ++iter) { - ParamContext *pc = *iter; - - os << "[" << pc->iniSection << "]\n"; - pc->describeParams(os); - os << endl; - } -} - void parseTime(const std::vector<int> &time, struct tm *tm) { diff --git a/src/sim/param.hh b/src/sim/param.hh index 8a4670e27..dff0fa72d 100644 --- a/src/sim/param.hh +++ b/src/sim/param.hh @@ -50,12 +50,6 @@ class SimObject; // class ParamContext : protected StartupCallback { - private: - - // static list of all ParamContext objects, built as a side effect - // of the ParamContext constructor - static std::list<ParamContext *> *ctxList; - protected: // .ini file (database) for parameter lookup... initialized on call @@ -78,31 +72,10 @@ class ParamContext : protected StartupCallback public: - /// Initialization phases for ParamContext objects. - enum InitPhase { - NoAutoInit = -1, ///< Don't initialize at all... params - /// will be parsed later (used by - /// SimObjectBuilder, which parses - /// params in SimObject::create(). - OutputInitPhase = 0, ///< Output stream initialization - TraceInitPhase = 1, ///< Trace context initialization: - /// depends on output streams, but - /// needs to come before others so we - /// can use tracing in other - /// ParamContext init code - StatsInitPhase = 2, ///< Stats output initialization - DefaultInitPhase = 3 ///< Everything else - }; - - /// Records the initialization phase for this ParamContext. - InitPhase initPhase; - /// Constructor. /// @param _iniSection Name of .ini section corresponding to this context. /// @param _initPhase Initialization phase (see InitPhase). - ParamContext(const std::string &_iniSection, - InitPhase _initPhase = DefaultInitPhase); - + ParamContext(const std::string &_iniSection); virtual ~ParamContext() {} // add a parameter to the context... called from the parameter @@ -135,24 +108,6 @@ class ParamContext : protected StartupCallback // generate the name for this instance of this context (used as a // prefix to create unique names in resolveSimObject() virtual const std::string &getInstanceName() { return iniSection; } - - // Parse all parameters registered with all ParamContext objects. - static void parseAllContexts(IniFile &iniFile); - - // Check all parameters registered with all ParamContext objects. - // (calls checkParams() on each) - static void checkAllContexts(); - - // Print all parameter values on indicated ostream. - static void showAllContexts(std::ostream &os); - - // Clean up all registered ParamContext objects. (calls cleanup() - // on each) - static void cleanupAllContexts(); - - // print descriptions of all parameters registered with all - // ParamContext objects - static void describeAllContexts(std::ostream &os); }; diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 4a8c0eb66..66ebc10e1 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -32,6 +32,7 @@ #include <fcntl.h> #include <unistd.h> +#include <fstream> #include <string> #include "arch/vtophys.hh" @@ -199,8 +200,7 @@ namespace AlphaPseudo Tick when = curTick + delay * Clock::Int::ns; Tick repeat = period * Clock::Int::ns; - using namespace Stats; - SetupEvent(Reset, when, repeat); + Stats::StatEvent(false, true, when, repeat); } void @@ -213,8 +213,7 @@ namespace AlphaPseudo Tick when = curTick + delay * Clock::Int::ns; Tick repeat = period * Clock::Int::ns; - using namespace Stats; - SetupEvent(Dump, when, repeat); + Stats::StatEvent(true, false, when, repeat); } void @@ -254,8 +253,7 @@ namespace AlphaPseudo Tick when = curTick + delay * Clock::Int::ns; Tick repeat = period * Clock::Int::ns; - using namespace Stats; - SetupEvent(Dump|Reset, when, repeat); + Stats::StatEvent(true, true, when, repeat); } void diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index 1ff16976d..d32bb1142 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -407,36 +407,3 @@ Checkpoint::sectionExists(const std::string §ion) { return db->sectionExists(section); } - -/** Hacked stat reset event */ - -class StatresetParamContext : public ParamContext -{ - public: - StatresetParamContext(const string §ion); - ~StatresetParamContext(); - void startup(); -}; - -StatresetParamContext statParams("statsreset"); - -Param<Tick> reset_cycle(&statParams, "reset_cycle", - "Cycle to reset stats on", 0); - -StatresetParamContext::StatresetParamContext(const string §ion) - : ParamContext(section) -{ } - -StatresetParamContext::~StatresetParamContext() -{ -} - -void -StatresetParamContext::startup() -{ - if (reset_cycle > 0) { - Stats::SetupEvent(Stats::Reset, curTick + reset_cycle, 0); - cprintf("Stats reset event scheduled for %lli\n", - curTick + reset_cycle); - } -} diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc index 8fc8fe58f..434fcffe6 100644 --- a/src/sim/sim_object.cc +++ b/src/sim/sim_object.cc @@ -56,10 +56,6 @@ using namespace std; // SimObject::SimObjectList SimObject::simObjectList; -namespace Stats { - extern ObjectMatch event_ignore; -} - // // SimObject constructor: used to maintain static simObjectList // @@ -70,7 +66,6 @@ SimObject::SimObject(Params *p) doDebugBreak = false; #endif - doRecordEvent = !Stats::event_ignore.match(name()); simObjectList.push_back(this); state = Running; } @@ -86,7 +81,6 @@ SimObject::SimObject(const string &_name) doDebugBreak = false; #endif - doRecordEvent = !Stats::event_ignore.match(name()); simObjectList.push_back(this); state = Running; } @@ -245,8 +239,7 @@ debugObjectBreak(const char *objs) void SimObject::recordEvent(const std::string &stat) { - if (doRecordEvent) - Stats::recordEvent(stat); + Stats::recordEvent(stat); } unsigned int diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh index 93802e247..536e761e5 100644 --- a/src/sim/sim_object.hh +++ b/src/sim/sim_object.hh @@ -136,7 +136,6 @@ class SimObject : public Serializable, protected StartupCallback #endif public: - bool doRecordEvent; void recordEvent(const std::string &stat); }; diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 3fad8beb5..228c83898 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -38,14 +38,9 @@ #include "base/callback.hh" #include "base/hostinfo.hh" #include "base/statistics.hh" -#include "base/str.hh" #include "base/time.hh" -#include "base/stats/output.hh" #include "cpu/base.hh" #include "sim/eventq.hh" -#include "sim/sim_object.hh" -#include "sim/stat_control.hh" -#include "sim/root.hh" using namespace std; @@ -63,11 +58,9 @@ namespace Stats { Time statTime(true); Tick startTick; -Tick lastDump(0); -class SimTicksReset : public Callback +struct SimTicksReset : public Callback { - public: void process() { statTime.set(); @@ -92,7 +85,7 @@ statElapsedTicks() SimTicksReset simTicksReset; void -InitSimStats() +initSimStats() { simInsts .functor(BaseCPU::numSimulatedInstructions) @@ -153,81 +146,40 @@ InitSimStats() registerResetCallback(&simTicksReset); } -class StatEvent : public Event +class _StatEvent : public Event { - protected: - int flags; + private: + bool dump; + bool reset; Tick repeat; public: - StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat); - virtual void process(); - virtual const char *description(); -}; - -StatEvent::StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat) - : Event(queue, Stat_Event_Pri), - flags(_flags), repeat(_repeat) -{ - setFlags(AutoDelete); - schedule(_when); -} - -const char * -StatEvent::description() -{ - return "Statistics dump and/or reset"; -} - -void -StatEvent::process() -{ - if (flags & Stats::Dump) - DumpNow(); - - if (flags & Stats::Reset) { - cprintf("Resetting stats at cycle %d!\n", curTick); - reset(); + _StatEvent(bool _dump, bool _reset, Tick _when, Tick _repeat) + : Event(&mainEventQueue, Stat_Event_Pri), dump(_dump), reset(_reset), + repeat(_repeat) + { + setFlags(AutoDelete); + schedule(_when); } - if (repeat) - schedule(curTick + repeat); -} + virtual void + process() + { + if (dump) + Stats::dump(); -list<Output *> OutputList; + if (reset) + Stats::reset(); -void -DumpNow() -{ - assert(lastDump <= curTick); - if (lastDump == curTick) - return; - lastDump = curTick; - - list<Output *>::iterator i = OutputList.begin(); - list<Output *>::iterator end = OutputList.end(); - for (; i != end; ++i) { - Output *output = *i; - if (!output->valid()) - continue; - - output->output(); + if (repeat) + new _StatEvent(dump, reset, curTick + repeat, repeat); } -} +}; void -SetupEvent(int flags, Tick when, Tick repeat, EventQueue *queue) +StatEvent(bool dump, bool reset, Tick when, Tick repeat) { - if (queue == NULL) - queue = &mainEventQueue; - - new StatEvent(queue, flags, when, repeat); + new _StatEvent(dump, reset, when, repeat); } /* namespace Stats */ } - -void debugDumpStats() -{ - Stats::DumpNow(); -} - diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh index 67f7cc491..1efa2554e 100644 --- a/src/sim/stat_control.hh +++ b/src/sim/stat_control.hh @@ -31,25 +31,10 @@ #ifndef __SIM_STAT_CONTROL_HH__ #define __SIM_STAT_CONTROL_HH__ -#include <fstream> -#include <list> - -class EventQueue; - namespace Stats { -enum { - Reset = 0x1, - Dump = 0x2 -}; - -class Output; -extern std::list<Output *> OutputList; - -void DumpNow(); -void SetupEvent(int flags, Tick when, Tick repeat = 0, EventQueue *queue = NULL); - -void InitSimStats(); +void initSimStats(); +void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0); /* namespace Stats */ } diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini index b56d96049..0c49d9f08 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,7 +182,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing egid=100 env= euid=100 @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out index 0af9e3f29..7858bd7a1 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt index 28328cd0e..6f6923231 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 490401 # Simulator instruction rate (inst/s) -host_mem_usage 178744 # Number of bytes of host memory used -host_seconds 812.94 # Real time elapsed on the host -host_tick_rate 734822 # Simulator tick rate (ticks/s) +host_inst_rate 595543 # Simulator instruction rate (inst/s) +host_mem_usage 157792 # Number of bytes of host memory used +host_seconds 669.41 # Real time elapsed on the host +host_tick_rate 892368 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664450 # Number of instructions simulated sim_seconds 0.000597 # Number of seconds simulated @@ -153,8 +153,8 @@ system.cpu.l2cache.ReadReq_misses 7180 # nu system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 625 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 625 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks. diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr index 1d6957eca..8534c55aa 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr @@ -1,3 +1,4 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... getting pixel output filename pixels_out.cook opening control file chair.control.cook diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini index fb3d24c55..ffc447d41 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -388,7 +373,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing egid=100 env= euid=100 @@ -414,14 +399,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out index e4ed95acf..c5de37af9 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing system=system uid=100 euid=100 @@ -366,15 +367,6 @@ clock=1000 width=64 responder_set=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -392,25 +384,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt index dfa1fbe0b..46ffe790c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 11837684 # Number of BTB hits -global.BPredUnit.BTBLookups 15197122 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1217 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1998573 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12917224 # Number of conditional branches predicted -global.BPredUnit.lookups 17533197 # Number of BP lookups -global.BPredUnit.usedRAS 1687018 # Number of times the RAS was used to get a target. -host_inst_rate 57997 # Simulator instruction rate (inst/s) -host_mem_usage 178748 # Number of bytes of host memory used -host_seconds 1423.90 # Real time elapsed on the host -host_tick_rate 73521 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 10104667 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 3292311 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 29530804 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 9370879 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 12030516 # Number of BTB hits +global.BPredUnit.BTBLookups 15440177 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1230 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 2016046 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 13150093 # Number of conditional branches predicted +global.BPredUnit.lookups 17791196 # Number of BP lookups +global.BPredUnit.usedRAS 1688779 # Number of times the RAS was used to get a target. +host_inst_rate 79686 # Simulator instruction rate (inst/s) +host_mem_usage 157864 # Number of bytes of host memory used +host_seconds 1056.39 # Real time elapsed on the host +host_tick_rate 100832 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10465878 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 3573806 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 29942981 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 9492949 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 82582323 # Number of instructions simulated -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104686099 # Number of ticks simulated -system.cpu.commit.COM:branches 10071057 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3175901 # number cycles where commit BW limit reached +sim_insts 84179641 # Number of instructions simulated +sim_seconds 0.000107 # Number of seconds simulated +sim_ticks 106518101 # Number of ticks simulated +system.cpu.commit.COM:branches 10240671 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 3286550 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 65490840 +system.cpu.commit.COM:committed_per_cycle.samples 66541371 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 32034998 4891.52% - 1 13785472 2104.95% - 2 8057025 1230.25% - 3 3669149 560.25% - 4 1988059 303.56% - 5 1377349 210.31% - 6 785420 119.93% - 7 617467 94.28% - 8 3175901 484.94% + 0 32590645 4897.80% + 1 14052557 2111.85% + 2 7925597 1191.08% + 3 3833922 576.17% + 4 2055997 308.98% + 5 1406670 211.40% + 6 778313 116.97% + 7 611120 91.84% + 8 3286550 493.91% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 90187947 # Number of instructions committed -system.cpu.commit.COM:loads 19613586 # Number of loads committed +system.cpu.commit.COM:count 91902973 # Number of instructions committed +system.cpu.commit.COM:loads 20034401 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 25981086 # Number of memory references committed +system.cpu.commit.COM:refs 26537088 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1985168 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 90187947 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 387 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 40679620 # The number of squashed insts skipped by commit -system.cpu.committedInsts 82582323 # Number of Instructions Simulated -system.cpu.committedInsts_total 82582323 # Number of Instructions Simulated -system.cpu.cpi 1.267657 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.267657 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 22673452 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5439.841232 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4838.693712 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 22672608 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4591226 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2385476 # number of ReadReq MSHR miss cycles +system.cpu.commit.branchMispredicts 2003600 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 91902973 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 40960562 # The number of squashed insts skipped by commit +system.cpu.committedInsts 84179641 # Number of Instructions Simulated +system.cpu.committedInsts_total 84179641 # Number of Instructions Simulated +system.cpu.cpi 1.265367 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.265367 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23044516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5485.308046 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4904.691383 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23043646 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4772218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 870 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2447441 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 493 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6365908 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5074.130393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4849.051425 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6360739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 26228180 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000812 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5169 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7826369 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000254 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1614 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2811.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3114.692857 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13779.471761 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 700 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 28116 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2180285 # number of cycles access was blocked +system.cpu.dcache.ReadReq_mshr_misses 499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501095 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4881.036474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.310702 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6495173 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28905498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5922 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 4184 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 7957104 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3119.926690 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13204.657577 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 873 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 2723696 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29039360 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5125.462498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29033347 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 30819406 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000207 # miss rate for demand accesses -system.cpu.dcache.demand_misses 6013 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3906 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10211845 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000073 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2107 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29545611 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4958.438751 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29538819 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 33677716 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses +system.cpu.dcache.demand_misses 6792 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 4555 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10404545 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29039360 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5125.462498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4846.627907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29033347 # number of overall hits -system.cpu.dcache.overall_miss_latency 30819406 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000207 # miss rate for overall accesses -system.cpu.dcache.overall_misses 6013 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3906 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10211845 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000073 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2107 # number of overall MSHR misses +system.cpu.dcache.overall_accesses 29545611 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4958.438751 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 29538819 # number of overall hits +system.cpu.dcache.overall_miss_latency 33677716 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses +system.cpu.dcache.overall_misses 6792 # number of overall misses +system.cpu.dcache.overall_mshr_hits 4555 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10404545 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 104 # number of replacements -system.cpu.dcache.sampled_refs 2107 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 158 # number of replacements +system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1404.053454 # Cycle average of tags in use -system.cpu.dcache.total_refs 29033347 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1401.371234 # Cycle average of tags in use +system.cpu.dcache.total_refs 29538819 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 75 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2221252 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13564 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2815361 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 145659694 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 36080141 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 27108364 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 6243203 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 50032 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 81084 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 17533197 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 17509399 # Number of cache lines fetched -system.cpu.fetch.Cycles 45531133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 484323 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 150299775 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2040341 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.244419 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 17509399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13524702 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.095236 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 105 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2237449 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12651 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2840694 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 147924684 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 36686871 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 27530511 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6274304 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45170 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 86541 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17791196 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 17777552 # Number of cache lines fetched +system.cpu.fetch.Cycles 46222210 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 487538 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 152510640 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2057778 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.244332 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 17777552 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13719295 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.094475 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 71734044 +system.cpu.fetch.rateDist.samples 72815676 system.cpu.fetch.rateDist.min_value 0 - 0 43713095 6093.77% - 1 2792314 389.26% - 2 2129360 296.84% - 3 3194083 445.27% - 4 4028588 561.60% - 5 1363321 190.05% - 6 1870461 260.75% - 7 1629807 227.20% - 8 11013015 1535.26% + 0 44371798 6093.72% + 1 2823722 387.79% + 2 2124290 291.74% + 3 3251818 446.58% + 4 4141832 568.81% + 5 1395626 191.67% + 6 1928347 264.83% + 7 1658600 227.78% + 8 11119643 1527.09% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 17509399 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3388.211547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2494.269154 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 17495889 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 45774738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000772 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 13510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3486 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25002554 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10024 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 17777552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3389.584594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2497.747914 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 17763934 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 46159363 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000766 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 13618 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3550 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 25147326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10068 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3400.454545 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1745.399940 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3002.121212 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1764.395511 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 22 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 74810 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 99070 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 17509399 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3388.211547 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency -system.cpu.icache.demand_hits 17495889 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 45774738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000772 # miss rate for demand accesses -system.cpu.icache.demand_misses 13510 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3486 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25002554 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10024 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 17777552 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3389.584594 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency +system.cpu.icache.demand_hits 17763934 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 46159363 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000766 # miss rate for demand accesses +system.cpu.icache.demand_misses 13618 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3550 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 25147326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000566 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10068 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 17509399 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3388.211547 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2494.269154 # average overall mshr miss latency +system.cpu.icache.overall_accesses 17777552 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3389.584594 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 17495889 # number of overall hits -system.cpu.icache.overall_miss_latency 45774738 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000772 # miss rate for overall accesses -system.cpu.icache.overall_misses 13510 # number of overall misses -system.cpu.icache.overall_mshr_hits 3486 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25002554 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10024 # number of overall MSHR misses +system.cpu.icache.overall_hits 17763934 # number of overall hits +system.cpu.icache.overall_miss_latency 46159363 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000766 # miss rate for overall accesses +system.cpu.icache.overall_misses 13618 # number of overall misses +system.cpu.icache.overall_mshr_hits 3550 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 25147326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000566 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10068 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8115 # number of replacements -system.cpu.icache.sampled_refs 10024 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8155 # number of replacements +system.cpu.icache.sampled_refs 10068 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1481.631027 # Cycle average of tags in use -system.cpu.icache.total_refs 17495889 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1487.917031 # Cycle average of tags in use +system.cpu.icache.total_refs 17763934 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 32952056 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12456785 # Number of branches executed -system.cpu.iew.EXEC:nop 11559797 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.365191 # Inst execution rate -system.cpu.iew.EXEC:refs 30958353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7006627 # Number of stores executed +system.cpu.idleCycles 33702426 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12615755 # Number of branches executed +system.cpu.iew.EXEC:nop 11674396 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.372220 # Inst execution rate +system.cpu.iew.EXEC:refs 31504897 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7134544 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 86914579 # num instructions consuming a value -system.cpu.iew.WB:count 96291361 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.729319 # average fanout of values written-back +system.cpu.iew.WB:consumers 88896181 # num instructions consuming a value +system.cpu.iew.WB:count 98303270 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.728803 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 63388475 # num instructions producing a value -system.cpu.iew.WB:rate 1.342338 # insts written-back per cycle -system.cpu.iew.WB:sent 96947832 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2153450 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 156060 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29530804 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2057217 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9370879 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 130866464 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 23951726 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2095770 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 97930658 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 43929 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 64787760 # num instructions producing a value +system.cpu.iew.WB:rate 1.350029 # insts written-back per cycle +system.cpu.iew.WB:sent 98915294 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2149664 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 135882 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 29942981 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2170747 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 9492949 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 132862510 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24370353 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2140113 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 99919134 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 28304 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 720 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 6243203 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 62133 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 9874 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 40553 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 855538 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3321 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 875 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6274304 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 51812 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 9931 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 36041 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 935951 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2991 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 18493 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9874 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9917218 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3003379 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 18493 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1143572 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1009878 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.788857 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.788857 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 100026428 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19407 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9931 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 9908580 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2990262 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19407 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 196546 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1953118 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.790285 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.790285 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 102059247 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 61666427 61.65% # Type of FU issued - IntMult 468908 0.47% # Type of FU issued + IntAlu 62946758 61.68% # Type of FU issued + IntMult 472934 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2704055 2.70% # Type of FU issued - FloatCmp 112834 0.11% # Type of FU issued - FloatCvt 2307257 2.31% # Type of FU issued - FloatMult 295394 0.30% # Type of FU issued - FloatDiv 735688 0.74% # Type of FU issued - FloatSqrt 122 0.00% # Type of FU issued - MemRead 24586382 24.58% # Type of FU issued - MemWrite 7149354 7.15% # Type of FU issued + FloatAdd 2777268 2.72% # Type of FU issued + FloatCmp 115533 0.11% # Type of FU issued + FloatCvt 2374854 2.33% # Type of FU issued + FloatMult 302376 0.30% # Type of FU issued + FloatDiv 755012 0.74% # Type of FU issued + FloatSqrt 321 0.00% # Type of FU issued + MemRead 24997637 24.49% # Type of FU issued + MemWrite 7316547 7.17% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1620744 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.016203 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1380880 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013530 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 195067 12.04% # attempts to use FU when none available + IntAlu 203697 14.75% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 1678 0.10% # attempts to use FU when none available - FloatCmp 197 0.01% # attempts to use FU when none available - FloatCvt 4552 0.28% # attempts to use FU when none available - FloatMult 2392 0.15% # attempts to use FU when none available - FloatDiv 951463 58.71% # attempts to use FU when none available + FloatAdd 1158 0.08% # attempts to use FU when none available + FloatCmp 74 0.01% # attempts to use FU when none available + FloatCvt 3812 0.28% # attempts to use FU when none available + FloatMult 2483 0.18% # attempts to use FU when none available + FloatDiv 669323 48.47% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 401417 24.77% # attempts to use FU when none available - MemWrite 63978 3.95% # attempts to use FU when none available + MemRead 447537 32.41% # attempts to use FU when none available + MemWrite 52796 3.82% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 71734044 +system.cpu.iq.ISSUE:issued_per_cycle.samples 72815676 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28631398 3991.33% - 1 15448994 2153.65% - 2 12333631 1719.36% - 3 7046540 982.31% - 4 4503539 627.81% - 5 2295007 319.93% - 6 1113179 155.18% - 7 291761 40.67% - 8 69995 9.76% + 0 28801052 3955.34% + 1 15640626 2147.98% + 2 12881779 1769.09% + 3 7065095 970.27% + 4 4538706 623.31% + 5 2449165 336.35% + 6 1089108 149.57% + 7 276679 38.00% + 8 73466 10.09% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.394407 # Inst issue rate -system.cpu.iq.iqInstsAdded 119306230 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 100026428 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 35838359 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 150449 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 30462150 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12131 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3919.717352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2067.943230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7146 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19539791 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.410931 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10308697 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.410931 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4985 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 75 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 75 # number of WriteReqNoAck|Writeback hits +system.cpu.iq.ISSUE:rate 1.401611 # Inst issue rate +system.cpu.iq.iqInstsAdded 121187678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 102059247 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 36185843 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 120363 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 30311914 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3854.841711 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2070.473487 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7231 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 19555612 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.412305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5073 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10503512 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5073 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.448546 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.446087 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12131 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3919.717352 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7146 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19539791 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.410931 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4985 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3854.841711 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7231 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19555612 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.412305 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5073 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10308697 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.410931 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 10503512 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.412305 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5073 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3919.717352 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2067.943230 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12409 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3854.841711 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7221 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19539791 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.408406 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4985 # number of overall misses +system.cpu.l2cache.overall_hits 7336 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19555612 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.408816 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5073 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10308697 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.408406 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 10503512 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.408816 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5073 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4985 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5073 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3244.539242 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7221 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3263.707979 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7336 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 71734044 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 969328 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 67122956 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 411688 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 37058676 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 742595 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 181728449 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 141044897 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 103457127 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 26196123 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 6243203 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1187915 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 36334171 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 78799 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 513 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2731208 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 502 # count of temporary serializing insts renamed -system.cpu.timesIdled 10186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 72815676 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 912182 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 68427307 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 427437 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37674875 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 794086 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 185014418 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 143398786 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 105292951 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 26609827 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6274304 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1283784 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 36865644 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 60704 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3136689 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed +system.cpu.timesIdled 10449 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini index fbf8dd865..789f77815 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,7 +59,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic egid=100 env= euid=100 @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out index 5375d2a8f..b4087eb1c 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt index e5e0a4991..2cd5a06bf 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 827042 # Simulator instruction rate (inst/s) -host_mem_usage 146736 # Number of bytes of host memory used -host_seconds 111.12 # Real time elapsed on the host -host_tick_rate 827039 # Simulator tick rate (ticks/s) +host_inst_rate 1013473 # Simulator instruction rate (inst/s) +host_mem_usage 151596 # Number of bytes of host memory used +host_seconds 90.68 # Real time elapsed on the host +host_tick_rate 1013469 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91900700 # Number of instructions simulated +sim_insts 91903057 # Number of instructions simulated sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91900699 # Number of ticks simulated +sim_ticks 91903056 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 91900700 # number of cpu cycles simulated -system.cpu.num_insts 91900700 # Number of instructions executed -system.cpu.num_refs 26536244 # Number of memory references -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 91903057 # number of cpu cycles simulated +system.cpu.num_insts 91903057 # Number of instructions executed +system.cpu.num_refs 26537109 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini index 9f6151e4d..e2265235e 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,7 +182,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing egid=100 env= euid=100 @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out index c27975bcb..fcf06c7db 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -30,7 +31,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt index 3926b2de9..5cdae9c4a 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 460435 # Simulator instruction rate (inst/s) -host_mem_usage 178124 # Number of bytes of host memory used -host_seconds 199.60 # Real time elapsed on the host -host_tick_rate 765898 # Simulator tick rate (ticks/s) +host_inst_rate 607322 # Simulator instruction rate (inst/s) +host_mem_usage 157212 # Number of bytes of host memory used +host_seconds 151.33 # Real time elapsed on the host +host_tick_rate 1013960 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91900700 # Number of instructions simulated +sim_insts 91903057 # Number of instructions simulated sim_seconds 0.000153 # Number of seconds simulated -sim_ticks 152870012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 19995627 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3765.212314 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2765.212314 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995156 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1773415 # number of ReadReq miss cycles +sim_ticks 153438012 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 471 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1302415 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 471 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6500813 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3867.178372 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2867.178372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6222290 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000248 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1609 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4613290 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1609 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12737.673077 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11923.977948 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 26496440 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3844.088942 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26494360 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7995705 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2080 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5915705 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2080 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 26496440 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3844.088942 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2844.088942 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26494360 # number of overall hits -system.cpu.dcache.overall_miss_latency 7995705 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2080 # number of overall misses +system.cpu.dcache.overall_hits 26495079 # number of overall hits +system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5915705 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2080 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 103 # number of replacements -system.cpu.dcache.sampled_refs 2080 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 157 # number of replacements +system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1399.324024 # Cycle average of tags in use -system.cpu.dcache.total_refs 26494360 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use +system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74 # number of writebacks -system.cpu.icache.ReadReq_accesses 91900701 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3116.205529 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2116.205529 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 91892201 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26487747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8500 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 17987747 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000092 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8500 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks 104 # number of writebacks +system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 10810.847176 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10798.419271 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 91900701 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3116.205529 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency -system.cpu.icache.demand_hits 91892201 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26487747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_misses 8500 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses +system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 17987747 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000092 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8500 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 91900701 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3116.205529 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2116.205529 # average overall mshr miss latency +system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 91892201 # number of overall hits -system.cpu.icache.overall_miss_latency 26487747 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_misses 8500 # number of overall misses +system.cpu.icache.overall_hits 91894548 # number of overall hits +system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses +system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 17987747 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000092 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8500 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6677 # number of replacements -system.cpu.icache.sampled_refs 8500 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6681 # number of replacements +system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1370.015418 # Cycle average of tags in use -system.cpu.icache.total_refs 91892201 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use +system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 10580 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2883.751500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1878.799057 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13461352 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.441210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4668 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8770234 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.441210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4668 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 74 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.282348 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.274559 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10580 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2883.751500 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5912 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13461352 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.441210 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4668 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8770234 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.441210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 10654 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2883.751500 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1878.799057 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5986 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13461352 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.438145 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4668 # number of overall misses +system.cpu.l2cache.overall_hits 6072 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8770234 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.438145 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 4668 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3056.777484 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5986 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 152870012 # number of cpu cycles simulated -system.cpu.num_insts 91900700 # Number of instructions executed -system.cpu.num_refs 26536244 # Number of memory references -system.cpu.workload.PROG:num_syscalls 387 # Number of system calls +system.cpu.numCycles 153438012 # number of cpu cycles simulated +system.cpu.num_insts 91903057 # Number of instructions executed +system.cpu.num_refs 26537109 # Number of memory references +system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... |