diff options
| -rw-r--r-- | src/sim/ClockedObject.py | 6 | ||||
| -rw-r--r-- | src/sim/System.py | 7 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py index 9bb243df8..26b0e2348 100644 --- a/src/sim/ClockedObject.py +++ b/src/sim/ClockedObject.py @@ -37,9 +37,13 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * class ClockedObject(SimObject): type = 'ClockedObject' abstract = True - clock = Param.Clock('1t', "Clock speed") + # Clock period of this object, with the default value being the + # clock period of the parent object, unproxied at instantiation + # time + clock = Param.Clock(Parent.clock, "Clock speed") diff --git a/src/sim/System.py b/src/sim/System.py index f680e64bf..88afea873 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -41,6 +41,13 @@ class System(MemObject): type = 'System' system_port = MasterPort("System port") + # Override the clock from the ClockedObject which looks at the + # parent clock by default + clock = '1t' + # @todo Either make this value 0 and treat it as an error if it is + # not overridden, or choose a more sensible value in the range of + # 1GHz + @classmethod def export_method_cxx_predecls(cls, code): code('#include "sim/system.hh"') |