diff options
| -rw-r--r-- | src/arch/alpha/ev5.cc | 306 | ||||
| -rw-r--r-- | src/arch/alpha/ipr.cc | 148 | ||||
| -rw-r--r-- | src/arch/alpha/ipr.hh | 310 |
3 files changed, 382 insertions, 382 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 56dadd6b1..7595423c3 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId) AlphaFault *reset = new ResetFault; - tc->setPC(tc->readMiscReg(MISCREG_IPR_PAL_BASE) + reset->vect()); + tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); delete reset; @@ -79,9 +79,9 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId) tc->setMiscReg(i, 0); } - tc->setMiscReg(MISCREG_IPR_PAL_BASE, PalBase); - tc->setMiscReg(MISCREG_IPR_MCSR, 0x6); - tc->setMiscReg(MISCREG_IPR_PALtemp16, cpuId); + tc->setMiscReg(IPR_PAL_BASE, PalBase); + tc->setMiscReg(IPR_MCSR, 0x6); + tc->setMiscReg(IPR_PALtemp16, cpuId); } @@ -96,13 +96,13 @@ AlphaISA::processInterrupts(CPU *cpu) cpu->checkInterrupts = false; - if (cpu->readMiscReg(MISCREG_IPR_ASTRR)) + if (cpu->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (cpu->readMiscReg(MISCREG_IPR_SIRR)) { + if (cpu->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (cpu->readMiscReg(MISCREG_IPR_SIRR) & (ULL(1) << i)) { + if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -123,12 +123,12 @@ AlphaISA::processInterrupts(CPU *cpu) } } - if (ipl && ipl > cpu->readMiscReg(MISCREG_IPR_IPLR)) { - cpu->setMiscReg(MISCREG_IPR_ISR, summary); - cpu->setMiscReg(MISCREG_IPR_INTID, ipl); + if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { + cpu->setMiscReg(IPR_ISR, summary); + cpu->setMiscReg(IPR_INTID, ipl); cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - cpu->readMiscReg(MISCREG_IPR_IPLR), ipl, summary); + cpu->readMiscReg(IPR_IPLR), ipl, summary); } } @@ -150,7 +150,7 @@ SimpleThread::hwrei() if (!inPalMode()) return new UnimplementedOpcodeFault; - setNextPC(readMiscReg(AlphaISA::MISCREG_IPR_EXC_ADDR)); + setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); if (!misspeculating()) { if (kernelStats) @@ -166,13 +166,13 @@ SimpleThread::hwrei() int AlphaISA::MiscRegFile::getInstAsid() { - return EV5::ITB_ASN_ASN(ipr[MISCREG_IPR_ITB_ASN]); + return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } int AlphaISA::MiscRegFile::getDataAsid() { - return EV5::DTB_ASN_ASN(ipr[MISCREG_IPR_DTB_ASN]); + return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } AlphaISA::MiscReg @@ -181,71 +181,71 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) uint64_t retval = 0; // return value, default 0 switch (idx) { - case AlphaISA::MISCREG_IPR_PALtemp0: - case AlphaISA::MISCREG_IPR_PALtemp1: - case AlphaISA::MISCREG_IPR_PALtemp2: - case AlphaISA::MISCREG_IPR_PALtemp3: - case AlphaISA::MISCREG_IPR_PALtemp4: - case AlphaISA::MISCREG_IPR_PALtemp5: - case AlphaISA::MISCREG_IPR_PALtemp6: - case AlphaISA::MISCREG_IPR_PALtemp7: - case AlphaISA::MISCREG_IPR_PALtemp8: - case AlphaISA::MISCREG_IPR_PALtemp9: - case AlphaISA::MISCREG_IPR_PALtemp10: - case AlphaISA::MISCREG_IPR_PALtemp11: - case AlphaISA::MISCREG_IPR_PALtemp12: - case AlphaISA::MISCREG_IPR_PALtemp13: - case AlphaISA::MISCREG_IPR_PALtemp14: - case AlphaISA::MISCREG_IPR_PALtemp15: - case AlphaISA::MISCREG_IPR_PALtemp16: - case AlphaISA::MISCREG_IPR_PALtemp17: - case AlphaISA::MISCREG_IPR_PALtemp18: - case AlphaISA::MISCREG_IPR_PALtemp19: - case AlphaISA::MISCREG_IPR_PALtemp20: - case AlphaISA::MISCREG_IPR_PALtemp21: - case AlphaISA::MISCREG_IPR_PALtemp22: - case AlphaISA::MISCREG_IPR_PALtemp23: - case AlphaISA::MISCREG_IPR_PAL_BASE: - - case AlphaISA::MISCREG_IPR_IVPTBR: - case AlphaISA::MISCREG_IPR_DC_MODE: - case AlphaISA::MISCREG_IPR_MAF_MODE: - case AlphaISA::MISCREG_IPR_ISR: - case AlphaISA::MISCREG_IPR_EXC_ADDR: - case AlphaISA::MISCREG_IPR_IC_PERR_STAT: - case AlphaISA::MISCREG_IPR_DC_PERR_STAT: - case AlphaISA::MISCREG_IPR_MCSR: - case AlphaISA::MISCREG_IPR_ASTRR: - case AlphaISA::MISCREG_IPR_ASTER: - case AlphaISA::MISCREG_IPR_SIRR: - case AlphaISA::MISCREG_IPR_ICSR: - case AlphaISA::MISCREG_IPR_ICM: - case AlphaISA::MISCREG_IPR_DTB_CM: - case AlphaISA::MISCREG_IPR_IPLR: - case AlphaISA::MISCREG_IPR_INTID: - case AlphaISA::MISCREG_IPR_PMCTR: + case AlphaISA::IPR_PALtemp0: + case AlphaISA::IPR_PALtemp1: + case AlphaISA::IPR_PALtemp2: + case AlphaISA::IPR_PALtemp3: + case AlphaISA::IPR_PALtemp4: + case AlphaISA::IPR_PALtemp5: + case AlphaISA::IPR_PALtemp6: + case AlphaISA::IPR_PALtemp7: + case AlphaISA::IPR_PALtemp8: + case AlphaISA::IPR_PALtemp9: + case AlphaISA::IPR_PALtemp10: + case AlphaISA::IPR_PALtemp11: + case AlphaISA::IPR_PALtemp12: + case AlphaISA::IPR_PALtemp13: + case AlphaISA::IPR_PALtemp14: + case AlphaISA::IPR_PALtemp15: + case AlphaISA::IPR_PALtemp16: + case AlphaISA::IPR_PALtemp17: + case AlphaISA::IPR_PALtemp18: + case AlphaISA::IPR_PALtemp19: + case AlphaISA::IPR_PALtemp20: + case AlphaISA::IPR_PALtemp21: + case AlphaISA::IPR_PALtemp22: + case AlphaISA::IPR_PALtemp23: + case AlphaISA::IPR_PAL_BASE: + + case AlphaISA::IPR_IVPTBR: + case AlphaISA::IPR_DC_MODE: + case AlphaISA::IPR_MAF_MODE: + case AlphaISA::IPR_ISR: + case AlphaISA::IPR_EXC_ADDR: + case AlphaISA::IPR_IC_PERR_STAT: + case AlphaISA::IPR_DC_PERR_STAT: + case AlphaISA::IPR_MCSR: + case AlphaISA::IPR_ASTRR: + case AlphaISA::IPR_ASTER: + case AlphaISA::IPR_SIRR: + case AlphaISA::IPR_ICSR: + case AlphaISA::IPR_ICM: + case AlphaISA::IPR_DTB_CM: + case AlphaISA::IPR_IPLR: + case AlphaISA::IPR_INTID: + case AlphaISA::IPR_PMCTR: // no side-effect retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_CC: + case AlphaISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); break; - case AlphaISA::MISCREG_IPR_VA: + case AlphaISA::IPR_VA: retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_VA_FORM: - case AlphaISA::MISCREG_IPR_MM_STAT: - case AlphaISA::MISCREG_IPR_IFAULT_VA_FORM: - case AlphaISA::MISCREG_IPR_EXC_MASK: - case AlphaISA::MISCREG_IPR_EXC_SUM: + case AlphaISA::IPR_VA_FORM: + case AlphaISA::IPR_MM_STAT: + case AlphaISA::IPR_IFAULT_VA_FORM: + case AlphaISA::IPR_EXC_MASK: + case AlphaISA::IPR_EXC_SUM: retval = ipr[idx]; break; - case AlphaISA::MISCREG_IPR_DTB_PTE: + case AlphaISA::IPR_DTB_PTE: { AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); @@ -260,15 +260,15 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) break; // write only registers - case AlphaISA::MISCREG_IPR_HWINT_CLR: - case AlphaISA::MISCREG_IPR_SL_XMIT: - case AlphaISA::MISCREG_IPR_DC_FLUSH: - case AlphaISA::MISCREG_IPR_IC_FLUSH: - case AlphaISA::MISCREG_IPR_ALT_MODE: - case AlphaISA::MISCREG_IPR_DTB_IA: - case AlphaISA::MISCREG_IPR_DTB_IAP: - case AlphaISA::MISCREG_IPR_ITB_IA: - case AlphaISA::MISCREG_IPR_ITB_IAP: + case AlphaISA::IPR_HWINT_CLR: + case AlphaISA::IPR_SL_XMIT: + case AlphaISA::IPR_DC_FLUSH: + case AlphaISA::IPR_IC_FLUSH: + case AlphaISA::IPR_ALT_MODE: + case AlphaISA::IPR_DTB_IA: + case AlphaISA::IPR_DTB_IAP: + case AlphaISA::IPR_ITB_IA: + case AlphaISA::IPR_ITB_IAP: fault = new UnimplementedOpcodeFault; break; @@ -295,52 +295,52 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) return NoFault; switch (idx) { - case AlphaISA::MISCREG_IPR_PALtemp0: - case AlphaISA::MISCREG_IPR_PALtemp1: - case AlphaISA::MISCREG_IPR_PALtemp2: - case AlphaISA::MISCREG_IPR_PALtemp3: - case AlphaISA::MISCREG_IPR_PALtemp4: - case AlphaISA::MISCREG_IPR_PALtemp5: - case AlphaISA::MISCREG_IPR_PALtemp6: - case AlphaISA::MISCREG_IPR_PALtemp7: - case AlphaISA::MISCREG_IPR_PALtemp8: - case AlphaISA::MISCREG_IPR_PALtemp9: - case AlphaISA::MISCREG_IPR_PALtemp10: - case AlphaISA::MISCREG_IPR_PALtemp11: - case AlphaISA::MISCREG_IPR_PALtemp12: - case AlphaISA::MISCREG_IPR_PALtemp13: - case AlphaISA::MISCREG_IPR_PALtemp14: - case AlphaISA::MISCREG_IPR_PALtemp15: - case AlphaISA::MISCREG_IPR_PALtemp16: - case AlphaISA::MISCREG_IPR_PALtemp17: - case AlphaISA::MISCREG_IPR_PALtemp18: - case AlphaISA::MISCREG_IPR_PALtemp19: - case AlphaISA::MISCREG_IPR_PALtemp20: - case AlphaISA::MISCREG_IPR_PALtemp21: - case AlphaISA::MISCREG_IPR_PALtemp22: - case AlphaISA::MISCREG_IPR_PAL_BASE: - case AlphaISA::MISCREG_IPR_IC_PERR_STAT: - case AlphaISA::MISCREG_IPR_DC_PERR_STAT: - case AlphaISA::MISCREG_IPR_PMCTR: + case AlphaISA::IPR_PALtemp0: + case AlphaISA::IPR_PALtemp1: + case AlphaISA::IPR_PALtemp2: + case AlphaISA::IPR_PALtemp3: + case AlphaISA::IPR_PALtemp4: + case AlphaISA::IPR_PALtemp5: + case AlphaISA::IPR_PALtemp6: + case AlphaISA::IPR_PALtemp7: + case AlphaISA::IPR_PALtemp8: + case AlphaISA::IPR_PALtemp9: + case AlphaISA::IPR_PALtemp10: + case AlphaISA::IPR_PALtemp11: + case AlphaISA::IPR_PALtemp12: + case AlphaISA::IPR_PALtemp13: + case AlphaISA::IPR_PALtemp14: + case AlphaISA::IPR_PALtemp15: + case AlphaISA::IPR_PALtemp16: + case AlphaISA::IPR_PALtemp17: + case AlphaISA::IPR_PALtemp18: + case AlphaISA::IPR_PALtemp19: + case AlphaISA::IPR_PALtemp20: + case AlphaISA::IPR_PALtemp21: + case AlphaISA::IPR_PALtemp22: + case AlphaISA::IPR_PAL_BASE: + case AlphaISA::IPR_IC_PERR_STAT: + case AlphaISA::IPR_DC_PERR_STAT: + case AlphaISA::IPR_PMCTR: // write entire quad w/ no side-effect ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_CC_CTL: + case AlphaISA::IPR_CC_CTL: // This IPR resets the cycle counter. We assume this only // happens once... let's verify that. assert(ipr[idx] == 0); ipr[idx] = 1; break; - case AlphaISA::MISCREG_IPR_CC: + case AlphaISA::IPR_CC: // This IPR only writes the upper 64 bits. It's ok to write // all 64 here since we mask out the lower 32 in rpcc (see // isa_desc). ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_PALtemp23: + case AlphaISA::IPR_PALtemp23: // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; @@ -348,23 +348,23 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->context(old, val, tc); break; - case AlphaISA::MISCREG_IPR_DTB_PTE: + case AlphaISA::IPR_DTB_PTE: // write entire quad w/ no side-effect, tag is forthcoming ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_EXC_ADDR: + case AlphaISA::IPR_EXC_ADDR: // second least significant bit in PC is always zero ipr[idx] = val & ~2; break; - case AlphaISA::MISCREG_IPR_ASTRR: - case AlphaISA::MISCREG_IPR_ASTER: + case AlphaISA::IPR_ASTRR: + case AlphaISA::IPR_ASTER: // only write least significant four bits - privilege mask ipr[idx] = val & 0xf; break; - case AlphaISA::MISCREG_IPR_IPLR: + case AlphaISA::IPR_IPLR: #ifdef DEBUG if (break_ipl != -1 && break_ipl == (val & 0x1f)) debug_break(); @@ -376,7 +376,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->swpipl(ipr[idx]); break; - case AlphaISA::MISCREG_IPR_DTB_CM: + case AlphaISA::IPR_DTB_CM: if (val & 0x18) { if (tc->getKernelStats()) tc->getKernelStats()->mode(Kernel::user, tc); @@ -385,121 +385,121 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) tc->getKernelStats()->mode(Kernel::kernel, tc); } - case AlphaISA::MISCREG_IPR_ICM: + case AlphaISA::IPR_ICM: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::MISCREG_IPR_ALT_MODE: + case AlphaISA::IPR_ALT_MODE: // only write two mode bits - processor mode ipr[idx] = val & 0x18; break; - case AlphaISA::MISCREG_IPR_MCSR: + case AlphaISA::IPR_MCSR: // more here after optimization... ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_SIRR: + case AlphaISA::IPR_SIRR: // only write software interrupt mask ipr[idx] = val & 0x7fff0; break; - case AlphaISA::MISCREG_IPR_ICSR: + case AlphaISA::IPR_ICSR: ipr[idx] = val & ULL(0xffffff0300); break; - case AlphaISA::MISCREG_IPR_IVPTBR: - case AlphaISA::MISCREG_IPR_MVPTBR: + case AlphaISA::IPR_IVPTBR: + case AlphaISA::IPR_MVPTBR: ipr[idx] = val & ULL(0xffffffffc0000000); break; - case AlphaISA::MISCREG_IPR_DC_TEST_CTL: + case AlphaISA::IPR_DC_TEST_CTL: ipr[idx] = val & 0x1ffb; break; - case AlphaISA::MISCREG_IPR_DC_MODE: - case AlphaISA::MISCREG_IPR_MAF_MODE: + case AlphaISA::IPR_DC_MODE: + case AlphaISA::IPR_MAF_MODE: ipr[idx] = val & 0x3f; break; - case AlphaISA::MISCREG_IPR_ITB_ASN: + case AlphaISA::IPR_ITB_ASN: ipr[idx] = val & 0x7f0; break; - case AlphaISA::MISCREG_IPR_DTB_ASN: + case AlphaISA::IPR_DTB_ASN: ipr[idx] = val & ULL(0xfe00000000000000); break; - case AlphaISA::MISCREG_IPR_EXC_SUM: - case AlphaISA::MISCREG_IPR_EXC_MASK: + case AlphaISA::IPR_EXC_SUM: + case AlphaISA::IPR_EXC_MASK: // any write to this register clears it ipr[idx] = 0; break; - case AlphaISA::MISCREG_IPR_INTID: - case AlphaISA::MISCREG_IPR_SL_RCV: - case AlphaISA::MISCREG_IPR_MM_STAT: - case AlphaISA::MISCREG_IPR_ITB_PTE_TEMP: - case AlphaISA::MISCREG_IPR_DTB_PTE_TEMP: + case AlphaISA::IPR_INTID: + case AlphaISA::IPR_SL_RCV: + case AlphaISA::IPR_MM_STAT: + case AlphaISA::IPR_ITB_PTE_TEMP: + case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers return new UnimplementedOpcodeFault; - case AlphaISA::MISCREG_IPR_HWINT_CLR: - case AlphaISA::MISCREG_IPR_SL_XMIT: - case AlphaISA::MISCREG_IPR_DC_FLUSH: - case AlphaISA::MISCREG_IPR_IC_FLUSH: + case AlphaISA::IPR_HWINT_CLR: + case AlphaISA::IPR_SL_XMIT: + case AlphaISA::IPR_DC_FLUSH: + case AlphaISA::IPR_IC_FLUSH: // the following are write only ipr[idx] = val; break; - case AlphaISA::MISCREG_IPR_DTB_IA: + case AlphaISA::IPR_DTB_IA: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushAll(); break; - case AlphaISA::MISCREG_IPR_DTB_IAP: + case AlphaISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; tc->getDTBPtr()->flushProcesses(); break; - case AlphaISA::MISCREG_IPR_DTB_IS: + case AlphaISA::IPR_DTB_IS: // really a control write ipr[idx] = val; tc->getDTBPtr()->flushAddr(val, - DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN])); + DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); break; - case AlphaISA::MISCREG_IPR_DTB_TAG: { + case AlphaISA::IPR_DTB_TAG: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]) != 0) + if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) panic("PTE GH field != 0"); // write entire quad ipr[idx] = val; // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN]); + pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB tc->getDTBPtr()->insert(val, pte); } break; - case AlphaISA::MISCREG_IPR_ITB_PTE: { + case AlphaISA::IPR_ITB_PTE: { struct AlphaISA::PTE pte; // FIXME: granularity hints NYI... @@ -516,33 +516,33 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) pte.fonr = ITB_PTE_FONR(val); pte.fonw = ITB_PTE_FONW(val); pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN]); + pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - tc->getITBPtr()->insert(ipr[AlphaISA::MISCREG_IPR_ITB_TAG], pte); + tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); } break; - case AlphaISA::MISCREG_IPR_ITB_IA: + case AlphaISA::IPR_ITB_IA: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushAll(); break; - case AlphaISA::MISCREG_IPR_ITB_IAP: + case AlphaISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; tc->getITBPtr()->flushProcesses(); break; - case AlphaISA::MISCREG_IPR_ITB_IS: + case AlphaISA::IPR_ITB_IS: // really a control write ipr[idx] = val; tc->getITBPtr()->flushAddr(val, - ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN])); + ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); break; default: diff --git a/src/arch/alpha/ipr.cc b/src/arch/alpha/ipr.cc index 50086a845..8e83102eb 100644 --- a/src/arch/alpha/ipr.cc +++ b/src/arch/alpha/ipr.cc @@ -38,89 +38,89 @@ namespace AlphaISA md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = { //Write only - IPR_HWINT_CLR, // H/W interrupt clear register - IPR_SL_XMIT, // serial line transmit register - IPR_DC_FLUSH, - IPR_IC_FLUSH, // instruction cache flush control - IPR_ALT_MODE, // alternate mode register - IPR_DTB_IA, // DTLB invalidate all register - IPR_DTB_IAP, // DTLB invalidate all process register - IPR_ITB_IA, // ITLB invalidate all register - IPR_ITB_IAP, // ITLB invalidate all process register + RAW_IPR_HWINT_CLR, // H/W interrupt clear register + RAW_IPR_SL_XMIT, // serial line transmit register + RAW_IPR_DC_FLUSH, + RAW_IPR_IC_FLUSH, // instruction cache flush control + RAW_IPR_ALT_MODE, // alternate mode register + RAW_IPR_DTB_IA, // DTLB invalidate all register + RAW_IPR_DTB_IAP, // DTLB invalidate all process register + RAW_IPR_ITB_IA, // ITLB invalidate all register + RAW_IPR_ITB_IAP, // ITLB invalidate all process register //Read only - IPR_INTID, // interrupt ID register - IPR_SL_RCV, // serial line receive register - IPR_MM_STAT, // data MMU fault status register - IPR_ITB_PTE_TEMP, // ITLB page table entry temp register - IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register + RAW_IPR_INTID, // interrupt ID register + RAW_IPR_SL_RCV, // serial line receive register + RAW_IPR_MM_STAT, // data MMU fault status register + RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register + RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register - IPR_ISR, // interrupt summary register - IPR_ITB_TAG, // ITLB tag register - IPR_ITB_PTE, // ITLB page table entry register - IPR_ITB_ASN, // ITLB address space register - IPR_ITB_IS, // ITLB invalidate select register - IPR_SIRR, // software interrupt request register - IPR_ASTRR, // asynchronous system trap request register - IPR_ASTER, // asynchronous system trap enable register - IPR_EXC_ADDR, // exception address register - IPR_EXC_SUM, // exception summary register - IPR_EXC_MASK, // exception mask register - IPR_PAL_BASE, // PAL base address register - IPR_ICM, // instruction current mode - IPR_IPLR, // interrupt priority level register - IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register - IPR_IVPTBR, // virtual page table base register - IPR_ICSR, // instruction control and status register - IPR_IC_PERR_STAT, // inst cache parity error status register - IPR_PMCTR, // performance counter register + RAW_IPR_ISR, // interrupt summary register + RAW_IPR_ITB_TAG, // ITLB tag register + RAW_IPR_ITB_PTE, // ITLB page table entry register + RAW_IPR_ITB_ASN, // ITLB address space register + RAW_IPR_ITB_IS, // ITLB invalidate select register + RAW_IPR_SIRR, // software interrupt request register + RAW_IPR_ASTRR, // asynchronous system trap request register + RAW_IPR_ASTER, // asynchronous system trap enable register + RAW_IPR_EXC_ADDR, // exception address register + RAW_IPR_EXC_SUM, // exception summary register + RAW_IPR_EXC_MASK, // exception mask register + RAW_IPR_PAL_BASE, // PAL base address register + RAW_IPR_ICM, // instruction current mode + RAW_IPR_IPLR, // interrupt priority level register + RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register + RAW_IPR_IVPTBR, // virtual page table base register + RAW_IPR_ICSR, // instruction control and status register + RAW_IPR_IC_PERR_STAT, // inst cache parity error status register + RAW_IPR_PMCTR, // performance counter register // PAL temporary registers... // register meanings gleaned from osfpal.s source code - IPR_PALtemp0, // local scratch - IPR_PALtemp1, // local scratch - IPR_PALtemp2, // entUna - IPR_PALtemp3, // CPU specific impure area pointer - IPR_PALtemp4, // memory management temp - IPR_PALtemp5, // memory management temp - IPR_PALtemp6, // memory management temp - IPR_PALtemp7, // entIF - IPR_PALtemp8, // intmask - IPR_PALtemp9, // entSys - IPR_PALtemp10, // ?? - IPR_PALtemp11, // entInt - IPR_PALtemp12, // entArith - IPR_PALtemp13, // reserved for platform specific PAL - IPR_PALtemp14, // reserved for platform specific PAL - IPR_PALtemp15, // reserved for platform specific PAL - IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> - IPR_PALtemp17, // sysval - IPR_PALtemp18, // usp - IPR_PALtemp19, // ksp - IPR_PALtemp20, // PTBR - IPR_PALtemp21, // entMM - IPR_PALtemp22, // kgp - IPR_PALtemp23, // PCBB + RAW_IPR_PALtemp0, // local scratch + RAW_IPR_PALtemp1, // local scratch + RAW_IPR_PALtemp2, // entUna + RAW_IPR_PALtemp3, // CPU specific impure area pointer + RAW_IPR_PALtemp4, // memory management temp + RAW_IPR_PALtemp5, // memory management temp + RAW_IPR_PALtemp6, // memory management temp + RAW_IPR_PALtemp7, // entIF + RAW_IPR_PALtemp8, // intmask + RAW_IPR_PALtemp9, // entSys + RAW_IPR_PALtemp10, // ?? + RAW_IPR_PALtemp11, // entInt + RAW_IPR_PALtemp12, // entArith + RAW_IPR_PALtemp13, // reserved for platform specific PAL + RAW_IPR_PALtemp14, // reserved for platform specific PAL + RAW_IPR_PALtemp15, // reserved for platform specific PAL + RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> + RAW_IPR_PALtemp17, // sysval + RAW_IPR_PALtemp18, // usp + RAW_IPR_PALtemp19, // ksp + RAW_IPR_PALtemp20, // PTBR + RAW_IPR_PALtemp21, // entMM + RAW_IPR_PALtemp22, // kgp + RAW_IPR_PALtemp23, // PCBB - IPR_DTB_ASN, // DTLB address space number register - IPR_DTB_CM, // DTLB current mode register - IPR_DTB_TAG, // DTLB tag register - IPR_DTB_PTE, // DTLB page table entry register + RAW_IPR_DTB_ASN, // DTLB address space number register + RAW_IPR_DTB_CM, // DTLB current mode register + RAW_IPR_DTB_TAG, // DTLB tag register + RAW_IPR_DTB_PTE, // DTLB page table entry register - IPR_VA, // fault virtual address register - IPR_VA_FORM, // formatted virtual address register - IPR_MVPTBR, // MTU virtual page table base register - IPR_DTB_IS, // DTLB invalidate single register - IPR_CC, // cycle counter register - IPR_CC_CTL, // cycle counter control register - IPR_MCSR, // MTU control register + RAW_IPR_VA, // fault virtual address register + RAW_IPR_VA_FORM, // formatted virtual address register + RAW_IPR_MVPTBR, // MTU virtual page table base register + RAW_IPR_DTB_IS, // DTLB invalidate single register + RAW_IPR_CC, // cycle counter register + RAW_IPR_CC_CTL, // cycle counter control register + RAW_IPR_MCSR, // MTU control register - IPR_DC_PERR_STAT, // Dcache parity error status register - IPR_DC_TEST_CTL, // Dcache test tag control register - IPR_DC_TEST_TAG, // Dcache test tag register - IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register - IPR_DC_MODE, // Dcache mode register - IPR_MAF_MODE // miss address file mode register + RAW_IPR_DC_PERR_STAT, // Dcache parity error status register + RAW_IPR_DC_TEST_CTL, // Dcache test tag control register + RAW_IPR_DC_TEST_TAG, // Dcache test tag register + RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register + RAW_IPR_DC_MODE, // Dcache mode register + RAW_IPR_MAF_MODE // miss address file mode register }; int IprToMiscRegIndex[MaxInternalProcRegs]; diff --git a/src/arch/alpha/ipr.hh b/src/arch/alpha/ipr.hh index dba0733ba..17518c0fe 100644 --- a/src/arch/alpha/ipr.hh +++ b/src/arch/alpha/ipr.hh @@ -40,86 +40,86 @@ namespace AlphaISA // enum md_ipr_names { - IPR_ISR = 0x100, // interrupt summary register - IPR_ITB_TAG = 0x101, // ITLB tag register - IPR_ITB_PTE = 0x102, // ITLB page table entry register - IPR_ITB_ASN = 0x103, // ITLB address space register - IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register - IPR_ITB_IA = 0x105, // ITLB invalidate all register - IPR_ITB_IAP = 0x106, // ITLB invalidate all process register - IPR_ITB_IS = 0x107, // ITLB invalidate select register - IPR_SIRR = 0x108, // software interrupt request register - IPR_ASTRR = 0x109, // asynchronous system trap request register - IPR_ASTER = 0x10a, // asynchronous system trap enable register - IPR_EXC_ADDR = 0x10b, // exception address register - IPR_EXC_SUM = 0x10c, // exception summary register - IPR_EXC_MASK = 0x10d, // exception mask register - IPR_PAL_BASE = 0x10e, // PAL base address register - IPR_ICM = 0x10f, // instruction current mode - IPR_IPLR = 0x110, // interrupt priority level register - IPR_INTID = 0x111, // interrupt ID register - IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register - IPR_IVPTBR = 0x113, // virtual page table base register - IPR_HWINT_CLR = 0x115, // H/W interrupt clear register - IPR_SL_XMIT = 0x116, // serial line transmit register - IPR_SL_RCV = 0x117, // serial line receive register - IPR_ICSR = 0x118, // instruction control and status register - IPR_IC_FLUSH = 0x119, // instruction cache flush control - IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register - IPR_PMCTR = 0x11c, // performance counter register + RAW_IPR_ISR = 0x100, // interrupt summary register + RAW_IPR_ITB_TAG = 0x101, // ITLB tag register + RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry register + RAW_IPR_ITB_ASN = 0x103, // ITLB address space register + RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register + RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all register + RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process register + RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select register + RAW_IPR_SIRR = 0x108, // software interrupt request register + RAW_IPR_ASTRR = 0x109, // asynchronous system trap request register + RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable register + RAW_IPR_EXC_ADDR = 0x10b, // exception address register + RAW_IPR_EXC_SUM = 0x10c, // exception summary register + RAW_IPR_EXC_MASK = 0x10d, // exception mask register + RAW_IPR_PAL_BASE = 0x10e, // PAL base address register + RAW_IPR_ICM = 0x10f, // instruction current mode + RAW_IPR_IPLR = 0x110, // interrupt priority level register + RAW_IPR_INTID = 0x111, // interrupt ID register + RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register + RAW_IPR_IVPTBR = 0x113, // virtual page table base register + RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear register + RAW_IPR_SL_XMIT = 0x116, // serial line transmit register + RAW_IPR_SL_RCV = 0x117, // serial line receive register + RAW_IPR_ICSR = 0x118, // instruction control and status register + RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control + RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register + RAW_IPR_PMCTR = 0x11c, // performance counter register // PAL temporary registers... // register meanings gleaned from osfpal.s source code - IPR_PALtemp0 = 0x140, // local scratch - IPR_PALtemp1 = 0x141, // local scratch - IPR_PALtemp2 = 0x142, // entUna - IPR_PALtemp3 = 0x143, // CPU specific impure area pointer - IPR_PALtemp4 = 0x144, // memory management temp - IPR_PALtemp5 = 0x145, // memory management temp - IPR_PALtemp6 = 0x146, // memory management temp - IPR_PALtemp7 = 0x147, // entIF - IPR_PALtemp8 = 0x148, // intmask - IPR_PALtemp9 = 0x149, // entSys - IPR_PALtemp10 = 0x14a, // ?? - IPR_PALtemp11 = 0x14b, // entInt - IPR_PALtemp12 = 0x14c, // entArith - IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL - IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL - IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL - IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> - IPR_PALtemp17 = 0x151, // sysval - IPR_PALtemp18 = 0x152, // usp - IPR_PALtemp19 = 0x153, // ksp - IPR_PALtemp20 = 0x154, // PTBR - IPR_PALtemp21 = 0x155, // entMM - IPR_PALtemp22 = 0x156, // kgp - IPR_PALtemp23 = 0x157, // PCBB - - IPR_DTB_ASN = 0x200, // DTLB address space number register - IPR_DTB_CM = 0x201, // DTLB current mode register - IPR_DTB_TAG = 0x202, // DTLB tag register - IPR_DTB_PTE = 0x203, // DTLB page table entry register - IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register - - IPR_MM_STAT = 0x205, // data MMU fault status register - IPR_VA = 0x206, // fault virtual address register - IPR_VA_FORM = 0x207, // formatted virtual address register - IPR_MVPTBR = 0x208, // MTU virtual page table base register - IPR_DTB_IAP = 0x209, // DTLB invalidate all process register - IPR_DTB_IA = 0x20a, // DTLB invalidate all register - IPR_DTB_IS = 0x20b, // DTLB invalidate single register - IPR_ALT_MODE = 0x20c, // alternate mode register - IPR_CC = 0x20d, // cycle counter register - IPR_CC_CTL = 0x20e, // cycle counter control register - IPR_MCSR = 0x20f, // MTU control register - - IPR_DC_FLUSH = 0x210, - IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register - IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register - IPR_DC_TEST_TAG = 0x214, // Dcache test tag register - IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register - IPR_DC_MODE = 0x216, // Dcache mode register - IPR_MAF_MODE = 0x217, // miss address file mode register + RAW_IPR_PALtemp0 = 0x140, // local scratch + RAW_IPR_PALtemp1 = 0x141, // local scratch + RAW_IPR_PALtemp2 = 0x142, // entUna + RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer + RAW_IPR_PALtemp4 = 0x144, // memory management temp + RAW_IPR_PALtemp5 = 0x145, // memory management temp + RAW_IPR_PALtemp6 = 0x146, // memory management temp + RAW_IPR_PALtemp7 = 0x147, // entIF + RAW_IPR_PALtemp8 = 0x148, // intmask + RAW_IPR_PALtemp9 = 0x149, // entSys + RAW_IPR_PALtemp10 = 0x14a, // ?? + RAW_IPR_PALtemp11 = 0x14b, // entInt + RAW_IPR_PALtemp12 = 0x14c, // entArith + RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL + RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL + RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL + RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> + RAW_IPR_PALtemp17 = 0x151, // sysval + RAW_IPR_PALtemp18 = 0x152, // usp + RAW_IPR_PALtemp19 = 0x153, // ksp + RAW_IPR_PALtemp20 = 0x154, // PTBR + RAW_IPR_PALtemp21 = 0x155, // entMM + RAW_IPR_PALtemp22 = 0x156, // kgp + RAW_IPR_PALtemp23 = 0x157, // PCBB + + RAW_IPR_DTB_ASN = 0x200, // DTLB address space number register + RAW_IPR_DTB_CM = 0x201, // DTLB current mode register + RAW_IPR_DTB_TAG = 0x202, // DTLB tag register + RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry register + RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register + + RAW_IPR_MM_STAT = 0x205, // data MMU fault status register + RAW_IPR_VA = 0x206, // fault virtual address register + RAW_IPR_VA_FORM = 0x207, // formatted virtual address register + RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base register + RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process register + RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all register + RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single register + RAW_IPR_ALT_MODE = 0x20c, // alternate mode register + RAW_IPR_CC = 0x20d, // cycle counter register + RAW_IPR_CC_CTL = 0x20e, // cycle counter control register + RAW_IPR_MCSR = 0x20f, // MTU control register + + RAW_IPR_DC_FLUSH = 0x210, + RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register + RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register + RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag register + RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register + RAW_IPR_DC_MODE = 0x216, // Dcache mode register + RAW_IPR_MAF_MODE = 0x217, // miss address file mode register MaxInternalProcRegs // number of IPR registers }; @@ -128,92 +128,92 @@ namespace AlphaISA { //Write only MinWriteOnlyIpr, - MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr, - MISCREG_IPR_SL_XMIT, - MISCREG_IPR_DC_FLUSH, - MISCREG_IPR_IC_FLUSH, - MISCREG_IPR_ALT_MODE, - MISCREG_IPR_DTB_IA, - MISCREG_IPR_DTB_IAP, - MISCREG_IPR_ITB_IA, + IPR_HWINT_CLR = MinWriteOnlyIpr, + IPR_SL_XMIT, + IPR_DC_FLUSH, + IPR_IC_FLUSH, + IPR_ALT_MODE, + IPR_DTB_IA, + IPR_DTB_IAP, + IPR_ITB_IA, MaxWriteOnlyIpr, - MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr, + IPR_ITB_IAP = MaxWriteOnlyIpr, //Read only MinReadOnlyIpr, - MISCREG_IPR_INTID = MinReadOnlyIpr, - MISCREG_IPR_SL_RCV, - MISCREG_IPR_MM_STAT, - MISCREG_IPR_ITB_PTE_TEMP, + IPR_INTID = MinReadOnlyIpr, + IPR_SL_RCV, + IPR_MM_STAT, + IPR_ITB_PTE_TEMP, MaxReadOnlyIpr, - MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, - - MISCREG_IPR_ISR, - MISCREG_IPR_ITB_TAG, - MISCREG_IPR_ITB_PTE, - MISCREG_IPR_ITB_ASN, - MISCREG_IPR_ITB_IS, - MISCREG_IPR_SIRR, - MISCREG_IPR_ASTRR, - MISCREG_IPR_ASTER, - MISCREG_IPR_EXC_ADDR, - MISCREG_IPR_EXC_SUM, - MISCREG_IPR_EXC_MASK, - MISCREG_IPR_PAL_BASE, - MISCREG_IPR_ICM, - MISCREG_IPR_IPLR, - MISCREG_IPR_IFAULT_VA_FORM, - MISCREG_IPR_IVPTBR, - MISCREG_IPR_ICSR, - MISCREG_IPR_IC_PERR_STAT, - MISCREG_IPR_PMCTR, + IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, + + IPR_ISR, + IPR_ITB_TAG, + IPR_ITB_PTE, + IPR_ITB_ASN, + IPR_ITB_IS, + IPR_SIRR, + IPR_ASTRR, + IPR_ASTER, + IPR_EXC_ADDR, + IPR_EXC_SUM, + IPR_EXC_MASK, + IPR_PAL_BASE, + IPR_ICM, + IPR_IPLR, + IPR_IFAULT_VA_FORM, + IPR_IVPTBR, + IPR_ICSR, + IPR_IC_PERR_STAT, + IPR_PMCTR, // PAL temporary registers... // register meanings gleaned from osfpal.s source code - MISCREG_IPR_PALtemp0, - MISCREG_IPR_PALtemp1, - MISCREG_IPR_PALtemp2, - MISCREG_IPR_PALtemp3, - MISCREG_IPR_PALtemp4, - MISCREG_IPR_PALtemp5, - MISCREG_IPR_PALtemp6, - MISCREG_IPR_PALtemp7, - MISCREG_IPR_PALtemp8, - MISCREG_IPR_PALtemp9, - MISCREG_IPR_PALtemp10, - MISCREG_IPR_PALtemp11, - MISCREG_IPR_PALtemp12, - MISCREG_IPR_PALtemp13, - MISCREG_IPR_PALtemp14, - MISCREG_IPR_PALtemp15, - MISCREG_IPR_PALtemp16, - MISCREG_IPR_PALtemp17, - MISCREG_IPR_PALtemp18, - MISCREG_IPR_PALtemp19, - MISCREG_IPR_PALtemp20, - MISCREG_IPR_PALtemp21, - MISCREG_IPR_PALtemp22, - MISCREG_IPR_PALtemp23, - - MISCREG_IPR_DTB_ASN, - MISCREG_IPR_DTB_CM, - MISCREG_IPR_DTB_TAG, - MISCREG_IPR_DTB_PTE, - - MISCREG_IPR_VA, - MISCREG_IPR_VA_FORM, - MISCREG_IPR_MVPTBR, - MISCREG_IPR_DTB_IS, - MISCREG_IPR_CC, - MISCREG_IPR_CC_CTL, - MISCREG_IPR_MCSR, - - MISCREG_IPR_DC_PERR_STAT, - MISCREG_IPR_DC_TEST_CTL, - MISCREG_IPR_DC_TEST_TAG, - MISCREG_IPR_DC_TEST_TAG_TEMP, - MISCREG_IPR_DC_MODE, - MISCREG_IPR_MAF_MODE, + IPR_PALtemp0, + IPR_PALtemp1, + IPR_PALtemp2, + IPR_PALtemp3, + IPR_PALtemp4, + IPR_PALtemp5, + IPR_PALtemp6, + IPR_PALtemp7, + IPR_PALtemp8, + IPR_PALtemp9, + IPR_PALtemp10, + IPR_PALtemp11, + IPR_PALtemp12, + IPR_PALtemp13, + IPR_PALtemp14, + IPR_PALtemp15, + IPR_PALtemp16, + IPR_PALtemp17, + IPR_PALtemp18, + IPR_PALtemp19, + IPR_PALtemp20, + IPR_PALtemp21, + IPR_PALtemp22, + IPR_PALtemp23, + + IPR_DTB_ASN, + IPR_DTB_CM, + IPR_DTB_TAG, + IPR_DTB_PTE, + + IPR_VA, + IPR_VA_FORM, + IPR_MVPTBR, + IPR_DTB_IS, + IPR_CC, + IPR_CC_CTL, + IPR_MCSR, + + IPR_DC_PERR_STAT, + IPR_DC_TEST_CTL, + IPR_DC_TEST_TAG, + IPR_DC_TEST_TAG_TEMP, + IPR_DC_MODE, + IPR_MAF_MODE, NumInternalProcRegs // number of IPR registers }; |