3 files changed, 0 insertions, 64 deletions
diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
index 3deb380f8..5e08b069d 100644
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -38,14 +38,6 @@ Branch::branchTarget(Addr branchPC) const
     return branchPC + 8 + disp;
 }
 
-Addr
-Jump::branchTarget(ThreadContext *tc) const
-{
-    Addr NPC = tc->readPC() + 8;
-    uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
-    return (Rb & ~3) | (NPC & 1);
-}
-
 const std::string &
 PCDependentDisassembly::disassemble(Addr pc,
                                     const SymbolTable *symtab) const
@@ -90,12 +82,4 @@ BranchExchange::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     }
     return ss.str();
 }
-
-std::string
-Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-{
-    std::stringstream ss;
-    printMnemonic(ss);
-    return ss.str();
-}
 }
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index c9a4eaf40..db626f28f 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -107,33 +107,6 @@ class BranchExchange : public PredOp
     generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
-
-/**
- * Base class for jumps (register-indirect control transfers).  In
- * the Arm ISA, these are always unconditional.
- */
-class Jump : public PCDependentDisassembly
-{
-  protected:
-
-    /// Displacement to target address (signed).
-    int32_t disp;
-
-    uint32_t target;
-
-  public:
-    /// Constructor
-    Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-        : PCDependentDisassembly(mnem, _machInst, __opClass),
-          disp(machInst.offset << 2)
-    {
-    }
-
-    Addr branchTarget(ThreadContext *tc) const;
-
-    std::string
-    generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-};
 }
 
 #endif //__ARCH_ARM_INSTS_BRANCH_HH__
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 5f1b541ff..efe91f039 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -108,24 +108,3 @@ def format BranchExchange(code,*opt_flags) {{
     exec_output = BasicExecute.subst(iop)
 }};
 
-def format Jump(code, *opt_flags) {{
-    #Build Instruction Flags
-    #Use Link Flag to Add Link Code
-    inst_flags = ('IsIndirectControl', 'IsUncondControl')
-    for x in opt_flags:
-        if x == 'Link':
-            code = 'LR = NPC;\n' + code
-        elif x == 'ClearHazards':
-            code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
-        else:
-            inst_flags += (x, )
-
-    iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = BasicExecute.subst(iop)
-    #exec_output = PredOpExecute.subst(iop)
-}};
-
-