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-rw-r--r--src/arch/arm/isa/operands.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 62684f5af..64deef044 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -118,7 +118,7 @@ let {{
return ('IntReg', 'uw', idx, None, srtNormal)
def cntrlReg(idx, id = srtNormal, type = 'uw'):
- return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
+ return ('ControlReg', type, idx, None, id)
def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
return ('ControlReg', type, idx, None, id)