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-rw-r--r--src/arch/arm/insts/misc.cc23
-rw-r--r--src/arch/arm/insts/misc.hh36
-rw-r--r--src/arch/arm/isa/templates/misc.isa51
3 files changed, 110 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 3547c6712..0d68b7c2b 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -153,3 +153,26 @@ RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printReg(ss, op1);
return ss.str();
}
+
+std::string
+SatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d, ", satImm);
+ printReg(ss, op1);
+ return ss.str();
+}
+
+std::string
+SatShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ccprintf(ss, ", #%d, ", satImm);
+ printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
+ printReg(ss, op1);
+ return ss.str();
+}
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index ae8d20e79..f4520478e 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -108,4 +108,40 @@ class RevOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class SatOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ uint32_t satImm;
+ IntRegIndex op1;
+
+ SatOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), satImm(_satImm), op1(_op1)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class SatShiftOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ uint32_t satImm;
+ IntRegIndex op1;
+ int32_t shiftAmt;
+ ArmShiftType shiftType;
+
+ SatShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
+ int32_t _shiftAmt, ArmShiftType _shiftType) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), satImm(_satImm), op1(_op1),
+ shiftAmt(_shiftAmt), shiftType(_shiftType)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
#endif
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 566d0a8dd..82e9aeab7 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -119,3 +119,54 @@ def template RevOpConstructor {{
%(constructor)s;
}
}};
+
+def template SatOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template SatOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ uint32_t _satImm,
+ IntRegIndex _op1)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _satImm, _op1)
+ {
+ %(constructor)s;
+ }
+}};
+
+def template SatShiftOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
+ int32_t _shiftAmt, ArmShiftType _shiftType);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template SatShiftOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ uint32_t _satImm,
+ IntRegIndex _op1,
+ int32_t _shiftAmt,
+ ArmShiftType _shiftType)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _satImm, _op1, _shiftAmt, _shiftType)
+ {
+ %(constructor)s;
+ }
+}};