diff options
| -rw-r--r-- | src/arch/mips/MipsTLB.py | 4 | ||||
| -rw-r--r-- | src/arch/x86/X86TLB.py | 2 | ||||
| -rw-r--r-- | src/python/swig/event.i | 4 | ||||
| -rw-r--r-- | src/python/swig/range.i | 2 |
4 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index ce8847365..1d0244e22 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -33,10 +33,8 @@ from m5.SimObject import SimObject from m5.params import * class MipsTLB(SimObject): - abstract = True type = 'MipsTLB' - cxx_namespace = 'MipsISA' - cxx_class = 'TLB' + abstract = True size = Param.Int("TLB size") class MipsDTB(MipsTLB): diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index dc080f37e..8dd53620e 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -69,8 +69,6 @@ if build_env['FULL_SYSTEM']: class X86TLB(SimObject): type = 'X86TLB' - cxx_namespace = 'X86ISA' - cxx_class = 'TLB' abstract = True size = Param.Int("TLB size") if build_env['FULL_SYSTEM']: diff --git a/src/python/swig/event.i b/src/python/swig/event.i index 9a2093c99..ee1f3d00b 100644 --- a/src/python/swig/event.i +++ b/src/python/swig/event.i @@ -44,8 +44,8 @@ void create(PyObject *object, Tick when); -class Event; -class CountedDrainEvent : public Event { +class CountedDrainEvent +{ public: void setCount(int _count); }; diff --git a/src/python/swig/range.i b/src/python/swig/range.i index 40809dae4..309e6a8ba 100644 --- a/src/python/swig/range.i +++ b/src/python/swig/range.i @@ -28,6 +28,8 @@ * Authors: Nathan Binkert */ +%rename(assign) *::operator=; + %include "base/range.hh" %include "sim/host.hh" |