diff options
| -rw-r--r-- | configs/common/FSConfig.py | 83 | ||||
| -rw-r--r-- | configs/example/fs.py | 106 | ||||
| -rw-r--r-- | configs/example/ruby_fs.py | 146 | ||||
| -rw-r--r-- | configs/example/se.py | 4 | ||||
| -rw-r--r-- | configs/ruby/Ruby.py | 3 | ||||
| -rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 4 |
6 files changed, 114 insertions, 232 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index cb1a004da..735e3302c 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -55,8 +55,8 @@ class MemBus(CoherentBus): default = Self.badaddr_responder.pio -def makeLinuxAlphaSystem(mem_mode, mdesc = None): - IO_address_space_base = 0x80000000000 +def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): + class BaseTsunami(Tsunami): ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) ide = IdeController(disks=[Parent.disk0, Parent.disk2], @@ -67,73 +67,44 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentBus() - self.membus = MemBus() - # By default the bridge responds to all addresses above the I/O - # base address (including the PCI config space) - self.bridge = Bridge(delay='50ns', - ranges = [AddrRange(IO_address_space_base, Addr.max)]) - self.mem_ranges = [AddrRange(mdesc.mem())] - self.bridge.master = self.iobus.slave - self.bridge.slave = self.membus.master - self.disk0 = CowIdeDisk(driveID='master') - self.disk2 = CowIdeDisk(driveID='master') - self.disk0.childImage(mdesc.disk()) - self.disk2.childImage(disk('linux-bigswap2.img')) + self.tsunami = BaseTsunami() + + # Create the io bus to connect all device ports + self.iobus = NoncoherentBus() self.tsunami.attachIO(self.iobus) + self.tsunami.ide.pio = self.iobus.master self.tsunami.ide.config = self.iobus.master - self.tsunami.ide.dma = self.iobus.slave + self.tsunami.ethernet.pio = self.iobus.master self.tsunami.ethernet.config = self.iobus.master - self.tsunami.ethernet.dma = self.iobus.slave - self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), - read_only = True)) - self.intrctrl = IntrControl() - self.mem_mode = mem_mode - self.terminal = Terminal() - self.kernel = binary('vmlinux') - self.pal = binary('ts_osfpal') - self.console = binary('console') - self.boot_osflags = 'root=/dev/hda1 console=ttyS0' - self.system_port = self.membus.slave + if ruby: + # Store the dma devices for later connection to dma ruby ports. + # Append an underscore to dma_ports to avoid the SimObjectVector check. + self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] + else: + self.membus = MemBus() - return self + # By default the bridge responds to all addresses above the I/O + # base address (including the PCI config space) + IO_address_space_base = 0x80000000000 + self.bridge = Bridge(delay='50ns', + ranges = [AddrRange(IO_address_space_base, Addr.max)]) + self.bridge.master = self.iobus.slave + self.bridge.slave = self.membus.master -def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): - class BaseTsunami(Tsunami): - ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) - ide = IdeController(disks=[Parent.disk0, Parent.disk2], - pci_func=0, pci_dev=0, pci_bus=0) - self = LinuxAlphaSystem() - self.mem_ranges = [AddrRange(mdesc.mem())] - if not mdesc: - # generic system - mdesc = SysConfig() - self.readfile = mdesc.script() + self.tsunami.ide.dma = self.iobus.slave + self.tsunami.ethernet.dma = self.iobus.slave - # Create pio bus to connect all device pio ports to rubymem's pio port - self.piobus = NoncoherentBus() + self.system_port = self.membus.slave + self.mem_ranges = [AddrRange(mdesc.mem())] self.disk0 = CowIdeDisk(driveID='master') self.disk2 = CowIdeDisk(driveID='master') self.disk0.childImage(mdesc.disk()) self.disk2.childImage(disk('linux-bigswap2.img')) - self.tsunami = BaseTsunami() - self.tsunami.attachIO(self.piobus) - self.tsunami.ide.pio = self.piobus.master - self.tsunami.ide.config = self.piobus.master - self.tsunami.ethernet.pio = self.piobus.master - self.tsunami.ethernet.config = self.piobus.master - - # - # Store the dma devices for later connection to dma ruby ports. - # Append an underscore to dma_devices to avoid the SimObjectVector check. - # - self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] - self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), read_only = True)) self.intrctrl = IntrControl() @@ -392,12 +363,12 @@ def connectX86ClassicSystem(x86_sys, numCPUs): def connectX86RubySystem(x86_sys): # North Bridge - x86_sys.piobus = NoncoherentBus() + x86_sys.iobus = NoncoherentBus() # add the ide to the list of dma devices that later need to attach to # dma controllers x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] - x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) + x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, diff --git a/configs/example/fs.py b/configs/example/fs.py index f53f5f151..7bc044647 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -10,6 +10,8 @@ # unmodified and in its entirety in all distributions of the software, # modified or unmodified, in source code or in binary form. # +# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood +# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -37,6 +39,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi +# Brad Beckmann import optparse import sys @@ -47,6 +50,9 @@ from m5.objects import * from m5.util import addToPath, fatal addToPath('../common') +addToPath('../ruby') + +import Ruby from FSConfig import * from SysPaths import * @@ -61,6 +67,10 @@ parser = optparse.OptionParser() Options.addCommonOptions(parser) Options.addFSOptions(parser) +# Add the ruby specific and protocol specific options +if '--ruby' in sys.argv: + Ruby.define_options(parser) + (options, args) = parser.parse_args() if args: @@ -104,13 +114,14 @@ else: np = options.num_cpus if buildEnv['TARGET_ISA'] == "alpha": - test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "x86": - test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], + options.ruby) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], options.dtb_filename, @@ -120,6 +131,9 @@ elif buildEnv['TARGET_ISA'] == "arm": else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) +# Set the cache line size for the entire system +test_sys.cache_line_size = options.cacheline_size + # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) @@ -156,32 +170,72 @@ test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): test_sys.vm = KvmVM() -if options.caches or options.l2cache: - # By default the IOCache runs at the system clock - test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) - test_sys.iocache.cpu_side = test_sys.iobus.master - test_sys.iocache.mem_side = test_sys.membus.slave +if options.ruby: + # Check for timing mode because ruby does not support atomic accesses + if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): + print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" + sys.exit(1) + + Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) + + # Create a seperate clock domain for Ruby + test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = test_sys.voltage_domain) + + for (i, cpu) in enumerate(test_sys.cpu): + # + # Tie the cpu ports to the correct ruby system ports + # + cpu.clk_domain = test_sys.cpu_clk_domain + cpu.createThreads() + cpu.createInterruptController() + + cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave + + if buildEnv['TARGET_ISA'] == "x86": + cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave + + cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master + cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave + cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master + + test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True + + # Create the appropriate memory controllers and connect them to the + # PIO bus + test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] + for i in xrange(len(test_sys.mem_ctrls)): + test_sys.mem_ctrls[i].port = test_sys.iobus.master + else: - test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) - test_sys.iobridge.slave = test_sys.iobus.master - test_sys.iobridge.master = test_sys.membus.slave - -# Sanity check -if options.fastmem: - if TestCPUClass != AtomicSimpleCPU: - fatal("Fastmem can only be used with atomic CPU!") - if (options.caches or options.l2cache): - fatal("You cannot use fastmem in combination with caches!") - -for i in xrange(np): - if options.fastmem: - test_sys.cpu[i].fastmem = True - if options.checker: - test_sys.cpu[i].addCheckerCpu() - test_sys.cpu[i].createThreads() + if options.caches or options.l2cache: + # By default the IOCache runs at the system clock + test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) + test_sys.iocache.cpu_side = test_sys.iobus.master + test_sys.iocache.mem_side = test_sys.membus.slave + else: + test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) + test_sys.iobridge.slave = test_sys.iobus.master + test_sys.iobridge.master = test_sys.membus.slave -CacheConfig.config_cache(options, test_sys) -MemConfig.config_mem(options, test_sys) + # Sanity check + if options.fastmem: + if TestCPUClass != AtomicSimpleCPU: + fatal("Fastmem can only be used with atomic CPU!") + if (options.caches or options.l2cache): + fatal("You cannot use fastmem in combination with caches!") + + for i in xrange(np): + if options.fastmem: + test_sys.cpu[i].fastmem = True + if options.checker: + test_sys.cpu[i].addCheckerCpu() + test_sys.cpu[i].createThreads() + + CacheConfig.config_cache(options, test_sys) + MemConfig.config_mem(options, test_sys) if len(bm) == 2: if buildEnv['TARGET_ISA'] == 'alpha': diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py deleted file mode 100644 index cd45ee8af..000000000 --- a/configs/example/ruby_fs.py +++ /dev/null @@ -1,146 +0,0 @@ -# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Brad Beckmann - -# -# Full system configuraiton for ruby -# - -import optparse -import sys - -import m5 -from m5.defines import buildEnv -from m5.objects import * -from m5.util import addToPath, fatal - -addToPath('../common') -addToPath('../ruby') -addToPath('../topologies') - -import Ruby - -from FSConfig import * -from SysPaths import * -from Benchmarks import * -import Options -import Simulation - -parser = optparse.OptionParser() -Options.addCommonOptions(parser) -Options.addFSOptions(parser) - -# Add the ruby specific and protocol specific options -Ruby.define_options(parser) - -(options, args) = parser.parse_args() -options.ruby = True - -if args: - print "Error: script doesn't take any positional arguments" - sys.exit(1) - -if options.benchmark: - try: - bm = Benchmarks[options.benchmark] - except KeyError: - print "Error benchmark %s has not been defined." % options.benchmark - print "Valid benchmarks are: %s" % DefinedBenchmarks - sys.exit(1) -else: - bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] - -# Check for timing mode because ruby does not support atomic accesses -if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): - print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" - sys.exit(1) -(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) - -TestMemClass = Simulation.setMemClass(options) - -if buildEnv['TARGET_ISA'] == "alpha": - system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) -elif buildEnv['TARGET_ISA'] == "x86": - system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) - Simulation.setWorkCountOptions(system, options) -else: - fatal("incapable of building non-alpha or non-x86 full system!") -system.cache_line_size = options.cacheline_size - -# Create a top-level voltage domain and clock domain -system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) - -system.clk_domain = SrcClockDomain(clock = options.sys_clock, - voltage_domain = system.voltage_domain) - -if options.kernel is not None: - system.kernel = binary(options.kernel) - -if options.script is not None: - system.readfile = options.script - -system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] - -# Create a source clock for the CPUs and set the clock period -system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, - voltage_domain = system.voltage_domain) - -Ruby.create_system(options, system, system.piobus, system._dma_ports) - -# Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, - voltage_domain = system.voltage_domain) - -for (i, cpu) in enumerate(system.cpu): - # - # Tie the cpu ports to the correct ruby system ports - # - cpu.clk_domain = system.cpu_clk_domain - cpu.createThreads() - cpu.createInterruptController() - - cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave - cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave - - if buildEnv['TARGET_ISA'] == "x86": - cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave - cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave - - cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master - cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave - cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master - - system.ruby._cpu_ruby_ports[i].access_phys_mem = True - -# Create the appropriate memory controllers and connect them to the -# PIO bus -system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges] -for i in xrange(len(system.mem_ctrls)): - system.mem_ctrls[i].port = system.piobus.master - -root = Root(full_system = True, system = system) -Simulation.run(options, root, system, FutureClass) diff --git a/configs/example/se.py b/configs/example/se.py index 97ad2c7de..34a3f045e 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -53,7 +53,6 @@ from m5.util import addToPath, fatal addToPath('../common') addToPath('../ruby') -addToPath('../topologies') import Options import Ruby @@ -145,7 +144,8 @@ if options.bench: app, options.spec_input)) multiprocesses.append(workload.makeLiveProcess()) except: - print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) + print >>sys.stderr, "Unable to find workload for %s: %s" % ( + buildEnv['TARGET_ISA'], app) sys.exit(1) elif options.cmd: multiprocesses, numThreads = get_processes(options) diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index e66a68f1d..75b891b1f 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -43,6 +43,9 @@ import math import m5 from m5.objects import * from m5.defines import buildEnv +from m5.util import addToPath, fatal + +addToPath('../topologies') def define_options(parser): # By default, ruby uses the simple timing cpu diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 81ec2fa9b..3d1b78324 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -68,7 +68,7 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) for i in xrange(options.num_cpus)] -Ruby.create_system(options, system, system.piobus, system._dma_ports) +Ruby.create_system(options, system, system.iobus, system._dma_ports) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, @@ -92,7 +92,7 @@ for (i, cpu) in enumerate(system.cpu): system.physmem = [DDR3_1600_x64(range = r) for r in system.mem_ranges] for i in xrange(len(system.physmem)): - system.physmem[i].port = system.piobus.master + system.physmem[i].port = system.iobus.master root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz') |