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-rw-r--r--src/arch/alpha/AlphaTLB.py8
-rw-r--r--src/arch/alpha/tlb.cc13
-rw-r--r--src/arch/alpha/tlb.hh6
-rw-r--r--src/arch/mips/tlb.cc12
-rw-r--r--src/arch/mips/tlb.hh5
-rw-r--r--src/arch/sparc/tlb.cc12
-rw-r--r--src/arch/sparc/tlb.hh5
-rw-r--r--src/arch/x86/faults.hh9
-rw-r--r--src/arch/x86/pagetable_walker.cc18
-rw-r--r--src/arch/x86/pagetable_walker.hh5
-rw-r--r--src/arch/x86/tlb.cc33
-rw-r--r--src/arch/x86/tlb.hh8
-rw-r--r--src/cpu/BaseCPU.py13
-rw-r--r--src/cpu/base_dyn_inst.hh5
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/simple/atomic.cc7
-rw-r--r--src/cpu/simple/timing.cc28
-rw-r--r--src/cpu/simple/timing.hh45
-rw-r--r--src/sim/tlb.cc7
-rw-r--r--src/sim/tlb.hh18
20 files changed, 130 insertions, 129 deletions
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index cdee54d26..51f636ec2 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -34,4 +34,10 @@ from BaseTLB import BaseTLB
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
- size = Param.Int(64, "TLB size")
+ size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+ size = 64
+
+class AlphaITB(AlphaTLB):
+ size = 48
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index d20a0adc2..d4f31b421 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -607,23 +607,20 @@ TLB::index(bool advance)
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
/* end namespace AlphaISA */ }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 292ba15f4..b84c26451 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -141,11 +141,9 @@ class TLB : public BaseTLB
Fault translateInst(RequestPtr req, ThreadContext *tc);
public:
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write = false, bool execute = false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
};
} // namespace AlphaISA
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 9343e35a3..9fc3e20ee 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -562,22 +562,20 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index fa2ed3f85..68b1c0c75 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -138,10 +138,9 @@ class TLB : public BaseTLB
void regStats();
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write=false, bool execute=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write=false, bool execute=false);
+ Translation *translation, Mode mode);
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index d11a41db5..64d73c3c1 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -843,22 +843,20 @@ handleMmuRegAccess:
};
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
#if FULL_SYSTEM
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index cba60a0ff..76b687042 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -163,10 +163,9 @@ class TLB : public BaseTLB
void dumpAll();
- Fault translateAtomic(RequestPtr req,
- ThreadContext *tc, bool write=false, bool execute=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write=false, bool execute=false);
+ Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index fe5132994..dbfb8d4d0 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -61,6 +61,7 @@
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
+#include "sim/tlb.hh"
#include <string>
@@ -331,16 +332,16 @@ namespace X86ISA
X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
{}
- PageFault(Addr _addr, bool present, bool write,
- bool user, bool reserved, bool fetch) :
+ PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
+ bool user, bool reserved) :
X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
{
PageFaultErrorCode code = 0;
code.present = present;
- code.write = write;
+ code.write = (mode == BaseTLB::Write);
code.user = user;
code.reserved = reserved;
- code.fetch = fetch;
+ code.fetch = (mode == BaseTLB::Execute);
errorCode = code;
}
diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc
index 2471c0663..69ded7cbc 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -98,7 +98,7 @@ Walker::doNext(PacketPtr &write)
bool uncacheable = pte.pcd;
Addr nextRead = 0;
bool doWrite = false;
- bool badNX = pte.nx && execute && enableNX;
+ bool badNX = pte.nx && mode == BaseTLB::Write && enableNX;
switch(state) {
case LongPML4:
DPRINTF(PageTableWalker,
@@ -329,14 +329,13 @@ Walker::doNext(PacketPtr &write)
Fault
Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
- RequestPtr _req, bool _write, bool _execute)
+ RequestPtr _req, BaseTLB::Mode _mode)
{
assert(state == Ready);
tc = _tc;
req = _req;
Addr vaddr = req->getVaddr();
- execute = _execute;
- write = _write;
+ mode = _mode;
translation = _translation;
VAddr addr = vaddr;
@@ -451,14 +450,14 @@ Walker::recvTiming(PacketPtr pkt)
* well.
*/
bool delayedResponse;
- Fault fault = tlb->translate(req, tc, NULL, write, execute,
+ Fault fault = tlb->translate(req, tc, NULL, mode,
delayedResponse, true);
assert(!delayedResponse);
// Let the CPU continue.
- translation->finish(fault, req, tc, write);
+ translation->finish(fault, req, tc, mode);
} else {
// There was a fault during the walk. Let the CPU know.
- translation->finish(timingFault, req, tc, write);
+ translation->finish(timingFault, req, tc, mode);
}
}
} else if (pkt->wasNacked()) {
@@ -563,8 +562,9 @@ Walker::pageFault(bool present)
{
DPRINTF(PageTableWalker, "Raising page fault.\n");
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
- return new PageFault(entry.vaddr, present, write,
- m5reg.cpl == 3, false, execute && enableNX);
+ if (mode == BaseTLB::Execute && !enableNX)
+ mode = BaseTLB::Read;
+ return new PageFault(entry.vaddr, present, mode, m5reg.cpl == 3, false);
}
}
diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index f73774a45..0f9d24923 100644
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -97,7 +97,7 @@ namespace X86ISA
// Kick off the state machine.
Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
- RequestPtr req, bool write, bool execute);
+ RequestPtr req, BaseTLB::Mode mode);
// Clean up after the state machine.
void
stop()
@@ -183,7 +183,8 @@ namespace X86ISA
State nextState;
int size;
bool enableNX;
- bool write, execute, user;
+ BaseTLB::Mode mode;
+ bool user;
TlbEntry entry;
Fault pageFault(bool present);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 2feed6f3e..62d694225 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -186,9 +186,8 @@ TLB::demapPage(Addr va, uint64_t asn)
}
Fault
-TLB::translate(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute,
- bool &delayedResponse, bool timing)
+TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
+ Mode mode, bool &delayedResponse, bool timing)
{
delayedResponse = false;
Addr vaddr = req->getVaddr();
@@ -577,9 +576,9 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
bool expandDown = false;
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
- if (!attr.writable && write)
+ if (!attr.writable && mode == Write)
return new GeneralProtection(0);
- if (!attr.readable && !write && !execute)
+ if (!attr.readable && mode == Read)
return new GeneralProtection(0);
expandDown = attr.expandDown;
@@ -612,8 +611,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
TlbEntry *entry = lookup(vaddr);
if (!entry) {
#if FULL_SYSTEM
- Fault fault = walker->start(tc, translation, req,
- write, execute);
+ Fault fault = walker->start(tc, translation, req, mode);
if (timing || fault != NoFault) {
// This gets ignored in atomic mode.
delayedResponse = true;
@@ -629,7 +627,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
Process *p = tc->getProcessPtr();
TlbEntry newEntry;
bool success = p->pTable->lookup(vaddr, newEntry);
- if(!success && !execute) {
+ if(!success && mode != Execute) {
p->checkAndAllocNextPage(vaddr);
success = p->pTable->lookup(vaddr, newEntry);
}
@@ -648,12 +646,11 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
bool inUser = (csAttr.dpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
if ((inUser && !entry->user) ||
- (write && !entry->writable)) {
+ (mode == Write && !entry->writable)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
- return new PageFault(vaddr, true, write,
- inUser, false, execute);
+ return new PageFault(vaddr, true, mode, inUser, false);
}
@@ -700,24 +697,22 @@ TLB::translate(RequestPtr req, ThreadContext *tc,
};
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
bool delayedResponse;
- return TLB::translate(req, tc, NULL, write,
- execute, delayedResponse, false);
+ return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
bool delayedResponse;
assert(translation);
- Fault fault = TLB::translate(req, tc, translation,
- write, execute, delayedResponse, true);
+ Fault fault =
+ TLB::translate(req, tc, translation, mode, delayedResponse, true);
if (!delayedResponse)
- translation->finish(fault, req, tc, write, execute);
+ translation->finish(fault, req, tc, mode);
}
#if FULL_SYSTEM
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index f67a93d8d..a9d3a4fa6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -127,16 +127,14 @@ namespace X86ISA
EntryList entryList;
Fault translate(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute,
+ Translation *translation, Mode mode,
bool &delayedResponse, bool timing);
public:
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write = false, bool execute = false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ef777ac5b..3aa9b87bb 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -38,7 +38,7 @@ import sys
default_tracer = ExeTracer()
if build_env['TARGET_ISA'] == 'alpha':
- from AlphaTLB import AlphaTLB
+ from AlphaTLB import AlphaDTB, AlphaITB
if build_env['FULL_SYSTEM']:
from AlphaInterrupts import AlphaInterrupts
elif build_env['TARGET_ISA'] == 'sparc':
@@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips':
if build_env['FULL_SYSTEM']:
from MipsInterrupts import MipsInterrupts
elif build_env['TARGET_ISA'] == 'arm':
- from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
+ from ArmTLB import ArmDTB
if build_env['FULL_SYSTEM']:
from ArmInterrupts import ArmInterrupts
@@ -89,8 +89,8 @@ class BaseCPU(MemObject):
interrupts = Param.SparcInterrupts(
SparcInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'alpha':
- dtb = Param.AlphaTLB(AlphaTLB(size=64), "Data TLB")
- itb = Param.AlphaTLB(AlphaTLB(size=48), "Instruction TLB")
+ dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
+ itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.AlphaInterrupts(
AlphaInterrupts(), "Interrupt Controller")
@@ -109,9 +109,8 @@ class BaseCPU(MemObject):
MipsInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'arm':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
- dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
- itb = Param.ArmITB(ArmITB(), "Instruction TLB")
- tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
+ dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
+ itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.ArmInterrupts(
ArmInterrupts(), "Interrupt Controller")
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 41c57cf39..ed0054402 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -46,6 +46,7 @@
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
+#include "sim/tlb.hh"
/**
* @file
@@ -860,7 +861,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->dtb->translateAtomic(req, thread->getTC(), false);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
if (req->isUncacheable())
isUncacheable = true;
@@ -916,7 +917,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->contextId(), threadNumber);
- fault = cpu->dtb->translateAtomic(req, thread->getTC(), true);
+ fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
if (req->isUncacheable())
isUncacheable = true;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f9cc78c18..fcee2daa6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Translate the instruction request.
fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
- false, true);
+ BaseTLB::Execute);
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b5e65265a..601111588 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
- Fault fault = thread->dtb->translateAtomic(req, tc, false);
+ Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
// Now do the access.
if (fault == NoFault) {
@@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(0, addr, dataSize, flags, thread->readPC());
// translate to physical address
- Fault fault = thread->dtb->translateAtomic(req, tc, true);
+ Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
// Now do the access.
if (fault == NoFault) {
@@ -609,7 +609,8 @@ AtomicSimpleCPU::tick()
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom && !curMacroStaticInst) {
setupFetchRequest(&ifetch_req);
- fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true);
+ fault = thread->itb->translateAtomic(&ifetch_req, tc,
+ BaseTLB::Execute);
}
if (fault == NoFault) {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 874eeefb7..1af2ea0ec 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -454,15 +454,15 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
typedef SplitDataTranslation::WholeTranslationState WholeState;
WholeState *state = new WholeState(req1, req2, req,
- (uint8_t *)(new T), true);
+ (uint8_t *)(new T), BaseTLB::Read);
thread->dtb->translateTiming(req1, tc,
- new SplitDataTranslation(this, 0, state), false);
+ new SplitDataTranslation(this, 0, state), BaseTLB::Read);
thread->dtb->translateTiming(req2, tc,
- new SplitDataTranslation(this, 1, state), false);
+ new SplitDataTranslation(this, 1, state), BaseTLB::Read);
} else {
- thread->dtb->translateTiming(req, tc,
- new DataTranslation(this, (uint8_t *)(new T), NULL, true),
- false);
+ DataTranslation *translation =
+ new DataTranslation(this, (uint8_t *)(new T), NULL, BaseTLB::Read);
+ thread->dtb->translateTiming(req, tc, translation, BaseTLB::Read);
}
if (traceData) {
@@ -573,15 +573,15 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
typedef SplitDataTranslation::WholeTranslationState WholeState;
WholeState *state = new WholeState(req1, req2, req,
- (uint8_t *)dataP, false);
+ (uint8_t *)dataP, BaseTLB::Write);
thread->dtb->translateTiming(req1, tc,
- new SplitDataTranslation(this, 0, state), true);
+ new SplitDataTranslation(this, 0, state), BaseTLB::Write);
thread->dtb->translateTiming(req2, tc,
- new SplitDataTranslation(this, 1, state), true);
+ new SplitDataTranslation(this, 1, state), BaseTLB::Write);
} else {
- thread->dtb->translateTiming(req, tc,
- new DataTranslation(this, (uint8_t *)dataP, res, false),
- true);
+ DataTranslation *translation =
+ new DataTranslation(this, (uint8_t *)dataP, res, BaseTLB::Write);
+ thread->dtb->translateTiming(req, tc, translation, BaseTLB::Write);
}
if (traceData) {
@@ -671,8 +671,8 @@ TimingSimpleCPU::fetch()
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
- thread->itb->translateTiming(ifetch_req, tc,
- &fetchTranslation, false, true);
+ thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
+ BaseTLB::Execute);
} else {
_status = IcacheWaitResponse;
completeIfetch(NULL);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 731eeeefc..6f6b02bb7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -102,11 +102,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
TimingSimpleCPU *cpu;
public:
- FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
+ FetchTranslation(TimingSimpleCPU *_cpu)
+ : cpu(_cpu)
{}
- void finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write, bool execute)
+ void
+ finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ BaseTLB::Mode mode)
{
cpu->sendFetch(fault, req, tc);
}
@@ -119,19 +121,22 @@ class TimingSimpleCPU : public BaseSimpleCPU
TimingSimpleCPU *cpu;
uint8_t *data;
uint64_t *res;
- bool read;
+ BaseTLB::Mode mode;
public:
DataTranslation(TimingSimpleCPU *_cpu,
- uint8_t *_data, uint64_t *_res, bool _read) :
- cpu(_cpu), data(_data), res(_res), read(_read)
- {}
+ uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode)
+ : cpu(_cpu), data(_data), res(_res), mode(_mode)
+ {
+ assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
+ }
void
- finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write, bool execute)
+ finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ BaseTLB::Mode mode)
{
- cpu->sendData(fault, req, data, res, read);
+ assert(mode == this->mode);
+ cpu->sendData(fault, req, data, res, mode == BaseTLB::Read);
delete this;
}
};
@@ -147,18 +152,20 @@ class TimingSimpleCPU : public BaseSimpleCPU
RequestPtr mainReq;
Fault faults[2];
uint8_t *data;
- bool read;
+ BaseTLB::Mode mode;
WholeTranslationState(RequestPtr req1, RequestPtr req2,
- RequestPtr main, uint8_t *_data, bool _read)
+ RequestPtr main, uint8_t *data, BaseTLB::Mode mode)
{
+ assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
+
outstanding = 2;
requests[0] = req1;
requests[1] = req2;
mainReq = main;
faults[0] = faults[1] = NoFault;
- data = _data;
- read = _read;
+ this->data = data;
+ this->mode = mode;
}
};
@@ -167,13 +174,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
WholeTranslationState *state;
SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
- WholeTranslationState *_state) :
- cpu(_cpu), index(_index), state(_state)
+ WholeTranslationState *_state)
+ : cpu(_cpu), index(_index), state(_state)
{}
void
- finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write, bool execute)
+ finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ BaseTLB::Mode mode)
{
assert(state);
assert(state->outstanding);
@@ -185,7 +192,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
state->requests[1],
state->mainReq,
state->data,
- state->read);
+ state->mode == BaseTLB::Read);
delete state;
}
delete this;
diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index 60ad8c155..e9a719ffa 100644
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -34,7 +34,7 @@
#include "sim/tlb.hh"
Fault
-GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool, bool)
+GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)
{
#if FULL_SYSTEM
panic("Generic translation shouldn't be used in full system mode.\n");
@@ -51,11 +51,10 @@ GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool, bool)
void
GenericTLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
void
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 6c1bf5350..db62b691d 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -42,10 +42,14 @@ class Packet;
class BaseTLB : public SimObject
{
protected:
- BaseTLB(const Params *p) : SimObject(p)
+ BaseTLB(const Params *p)
+ : SimObject(p)
{}
public:
+ enum Mode { Read, Write, Execute };
+
+ public:
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
class Translation
@@ -59,24 +63,24 @@ class BaseTLB : public SimObject
* be responsible for cleaning itself up which will happen in this
* function. Once it's called, the object is no longer valid.
*/
- virtual void finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write=false, bool execute=false) = 0;
+ virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ Mode mode) = 0;
};
};
class GenericTLB : public BaseTLB
{
protected:
- GenericTLB(const Params *p) : BaseTLB(p)
+ GenericTLB(const Params *p)
+ : BaseTLB(p)
{}
public:
void demapPage(Addr vaddr, uint64_t asn);
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool=false, bool=false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, bool=false, bool=false);
+ Translation *translation, Mode mode);
};
#endif // __ARCH_SPARC_TLB_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 14:35:00 +0000