diff options
| -rw-r--r-- | configs/example/memtest.py | 3 | ||||
| -rw-r--r-- | src/mem/cache/BaseCache.py | 3 |
2 files changed, 3 insertions, 3 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 9fd943aaa..c28ffab10 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -82,8 +82,7 @@ cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads, # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(latency = "50ps"), - membus = Bus(clock="500MHz", width=16)) + physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16)) # l2cache & bus if options.caches: diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 4b98f6b30..32f3f0174 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -27,6 +27,7 @@ # Authors: Nathan Binkert from m5.params import * +from m5.proxy import Self from MemObject import MemObject class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] @@ -77,7 +78,7 @@ class BaseCache(MemObject): "Squash prefetches with a later time on a subsequent miss") prefetch_degree = Param.Int(1, "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, + prefetch_latency = Param.Latency(10 * Self.latency, "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") |