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-rw-r--r--tests/configs/simple-timing-ruby.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 1d67f6f97..d03b86068 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -82,8 +82,7 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
-cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
+cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
# -----------------------
# run simulation