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-rw-r--r--src/arch/arm/ArmISA.py5
-rw-r--r--src/arch/arm/faults.cc20
-rw-r--r--src/arch/arm/isa.cc11
-rw-r--r--src/arch/arm/isa.hh7
-rw-r--r--src/arch/arm/miscregs.cc12
-rw-r--r--src/arch/arm/system.hh7
-rw-r--r--src/arch/arm/table_walker.cc15
-rw-r--r--src/arch/arm/utility.cc44
8 files changed, 54 insertions, 67 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 7ef8afd88..146ca6494 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015 ARM Limited
+# Copyright (c) 2012-2013, 2015-2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -117,8 +117,7 @@ class ArmISA(SimObject):
"AArch64 Memory Model Feature Register 1")
# !GICv3 CP15 | AdvSIMD | FP | !EL3 | !EL2 | EL1 (AArch64) | EL0 (AArch64)
- # (no AArch32/64 interprocessing support for now)
- id_aa64pfr0_el1 = Param.UInt64(0x0000000000000011,
+ id_aa64pfr0_el1 = Param.UInt64(0x0000000000000022,
"AArch64 Processor Feature Register 0")
# Reserved for future expansion
id_aa64pfr1_el1 = Param.UInt64(0x0000000000000000,
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 1b54a3e24..e7a461ef6 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -338,11 +338,10 @@ ArmFault::getVector64(ThreadContext *tc)
assert(ArmSystem::haveSecurity(tc));
vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization(tc));
- // vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
+ break;
case EL1:
vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
break;
@@ -596,12 +595,11 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
elr_idx = MISCREG_ELR_EL1;
spsr_idx = MISCREG_SPSR_EL1;
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // elr_idx = MISCREG_ELR_EL2;
- // spsr_idx = MISCREG_SPSR_EL2;
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ elr_idx = MISCREG_ELR_EL2;
+ spsr_idx = MISCREG_SPSR_EL2;
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
elr_idx = MISCREG_ELR_EL3;
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c90de1337..2cf67fff7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -359,9 +359,8 @@ ISA::clear64(const ArmISAParams *p)
if (haveSecurity) {
miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
- // @todo: uncomment this to enable Virtualization
- // } else if (haveVirtualization) {
- // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
+ } else if (haveVirtualization) {
+ miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
} else {
miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
// Always non-secure
@@ -391,15 +390,13 @@ ISA::clear64(const ArmISAParams *p)
// Enforce consistency with system-level settings...
// EL3
- // (no AArch32/64 interprocessing support for now)
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
- haveSecurity ? 0x1 : 0x0);
+ haveSecurity ? 0x2 : 0x0);
// EL2
- // (no AArch32/64 interprocessing support for now)
miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
- haveVirtualization ? 0x1 : 0x0);
+ haveVirtualization ? 0x2 : 0x0);
// Large ASID support
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index ab5c72e6a..b8eaaec11 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2015 ARM Limited
+ * Copyright (c) 2010, 2012-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -261,9 +261,8 @@ namespace ArmISA
switch (el) {
case EL3:
return INTREG_SP3;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return INTREG_SP2;
+ case EL2:
+ return INTREG_SP2;
case EL1:
return INTREG_SP1;
case EL0:
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 3a40a27b0..9514997e3 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2015 ARM Limited
+ * Copyright (c) 2010-2013, 2015-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -2118,9 +2118,8 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] :
miscRegInfo[reg][MISCREG_PRI_NS_RD];
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return miscRegInfo[reg][MISCREG_HYP_RD];
+ case EL2:
+ return miscRegInfo[reg][MISCREG_HYP_RD];
case EL3:
return secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
miscRegInfo[reg][MISCREG_MON_NS1_RD];
@@ -2163,9 +2162,8 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
case EL1:
return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
miscRegInfo[reg][MISCREG_PRI_NS_WR];
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // return miscRegInfo[reg][MISCREG_HYP_WR];
+ case EL2:
+ return miscRegInfo[reg][MISCREG_HYP_WR];
case EL3:
return secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
miscRegInfo[reg][MISCREG_MON_NS1_WR];
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 511118d4d..ee286d23a 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2015 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -184,9 +184,8 @@ class ArmSystem : public System
{
if (_haveSecurity)
return EL3;
- // @todo: uncomment this to enable Virtualization
- // if (_haveVirtualization)
- // return EL2;
+ if (_haveVirtualization)
+ return EL2;
return EL1;
}
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 91b13e251..1f0bdeb8e 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2015 ARM Limited
+ * Copyright (c) 2010, 2012-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -223,7 +223,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
// ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
// aarch32/translation/translation/AArch32.TranslateAddress dictates
// even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
- currState->aarch64 = opModeIs64(currOpMode(_tc)) ||
+ currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) ||
((currEL(_tc) == EL0) && ELIs64(_tc, EL1));
currState->el = currEL(_tc);
currState->transState = _trans;
@@ -255,12 +255,11 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(haveVirtualization);
- // currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
- // currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
- // break;
+ case EL2:
+ assert(_haveVirtualization);
+ currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
+ currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
+ break;
case EL3:
assert(haveSecurity);
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index df00e8bcc..ea7fa2bde 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2014 ARM Limited
+ * Copyright (c) 2009-2014, 2016 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -235,14 +235,14 @@ ELIs64(ThreadContext *tc, ExceptionLevel el)
return opModeIs64(currOpMode(tc));
case EL1:
{
- // @todo: uncomment this to enable Virtualization
- // if (ArmSystem::haveVirtualization(tc)) {
- // HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
- // return hcr.rw;
- // }
- assert(ArmSystem::haveSecurity(tc));
- SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
- return scr.rw;
+ if (ArmSystem::haveVirtualization(tc)) {
+ HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+ return hcr.rw;
+ } else if (ArmSystem::haveSecurity(tc)) {
+ SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+ return scr.rw;
+ }
+ panic("must haveSecurity(tc)");
}
case EL2:
{
@@ -286,13 +286,12 @@ purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
else if (!bits(addr, 55, 48) && tcr.tbi0)
return bits(addr,55, 0);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
- // if (tcr.tbi)
- // return addr & mask(56);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ tcr = tc->readMiscReg(MISCREG_TCR_EL2);
+ if (tcr.tbi)
+ return addr & mask(56);
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
if (tcr.tbi)
@@ -320,13 +319,12 @@ purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el)
else if (!bits(addr, 55, 48) && tcr.tbi0)
return bits(addr,55, 0);
break;
- // @todo: uncomment this to enable Virtualization
- // case EL2:
- // assert(ArmSystem::haveVirtualization());
- // tcr = tc->readMiscReg(MISCREG_TCR_EL2);
- // if (tcr.tbi)
- // return addr & mask(56);
- // break;
+ case EL2:
+ assert(ArmSystem::haveVirtualization(tc));
+ tcr = tc->readMiscReg(MISCREG_TCR_EL2);
+ if (tcr.tbi)
+ return addr & mask(56);
+ break;
case EL3:
assert(ArmSystem::haveSecurity(tc));
tcr = tc->readMiscReg(MISCREG_TCR_EL3);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 17:18:33 +0000