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-rw-r--r--src/mem/cache/base_cache.hh1
-rw-r--r--src/mem/cache/cache.hh41
-rw-r--r--src/mem/cache/cache_builder.cc4
-rw-r--r--src/mem/cache/cache_impl.hh38
-rw-r--r--src/mem/cache/miss/mshr_queue.cc17
-rw-r--r--src/mem/cache/tags/fa_lru.hh19
-rw-r--r--src/mem/cache/tags/iic.cc94
-rw-r--r--src/mem/cache/tags/iic.hh16
-rw-r--r--src/mem/cache/tags/lru.cc45
-rw-r--r--src/mem/cache/tags/lru.hh16
-rw-r--r--src/mem/cache/tags/split.cc13
-rw-r--r--src/mem/cache/tags/split.hh16
-rw-r--r--src/mem/cache/tags/split_lifo.cc46
-rw-r--r--src/mem/cache/tags/split_lifo.hh16
-rw-r--r--src/mem/cache/tags/split_lru.cc46
-rw-r--r--src/mem/cache/tags/split_lru.hh16
-rw-r--r--src/python/m5/objects/BaseCache.py1
17 files changed, 4 insertions, 441 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 8814abb38..93830b04f 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -58,7 +58,6 @@ enum BlockedCause{
Blocked_NoTargets,
Blocked_NoWBBuffers,
Blocked_Coherence,
- Blocked_Copy,
NUM_BLOCKED_CAUSES
};
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 7024ce58a..07d9d6336 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -75,12 +75,6 @@ class Cache : public BaseCache
/** Prefetcher */
Prefetcher<TagStore, Buffering> *prefetcher;
- /** Do fast copies in this cache. */
- bool doCopy;
-
- /** Block on a delayed copy. */
- bool blockOnCopy;
-
/**
* The clock ratio of the outgoing bus.
* Used for calculating critical word first.
@@ -105,18 +99,6 @@ class Cache : public BaseCache
Packet * invalidatePkt;
Request *invalidateReq;
- /**
- * Temporarily move a block into a MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(Addr addr);
-
- /**
- * Temporarily move a block into an existing MSHR.
- * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
- */
- void pseudoFill(MSHR *mshr);
-
public:
class Params
@@ -125,19 +107,17 @@ class Cache : public BaseCache
TagStore *tags;
Buffering *missQueue;
Coherence *coherence;
- bool doCopy;
- bool blockOnCopy;
BaseCache::Params baseParams;
Prefetcher<TagStore, Buffering> *prefetcher;
bool prefetchAccess;
int hitLatency;
Params(TagStore *_tags, Buffering *mq, Coherence *coh,
- bool do_copy, BaseCache::Params params,
+ BaseCache::Params params,
Prefetcher<TagStore, Buffering> *_prefetcher,
bool prefetch_access, int hit_latency)
- : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
- blockOnCopy(false), baseParams(params),
+ : tags(_tags), missQueue(mq), coherence(coh),
+ baseParams(params),
prefetcher(_prefetcher), prefetchAccess(prefetch_access),
hitLatency(hit_latency)
{
@@ -192,21 +172,6 @@ class Cache : public BaseCache
void handleResponse(Packet * &pkt);
/**
- * Start handling a copy transaction.
- * @param pkt The copy request to perform.
- */
- void startCopy(Packet * &pkt);
-
- /**
- * Handle a delayed copy transaction.
- * @param pkt The delayed copy request to continue.
- * @param addr The address being responded to.
- * @param blk The block of the current response.
- * @param mshr The mshr being handled.
- */
- void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
-
- /**
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 05a149a1c..03646ec2a 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -113,7 +113,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
Param<bool> prioritizeRequests;
// SimObjectParam<Bus *> in_bus;
// SimObjectParam<Bus *> out_bus;
- Param<bool> do_copy;
SimObjectParam<CoherenceProtocol *> protocol;
Param<Addr> trace_addr;
Param<int> hash_delay;
@@ -163,7 +162,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
/* INIT_PARAM_DFLT(in_bus, "incoming bus object", NULL),
INIT_PARAM(out_bus, "outgoing bus object"),
*/
- INIT_PARAM_DFLT(do_copy, "perform fast copies in the cache", false),
INIT_PARAM_DFLT(protocol, "coherence protocol to use in the cache", NULL),
INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
@@ -228,7 +226,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
BUILD_NULL_PREFETCHER(t, comp, b); \
} \
Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
- do_copy, base_params, \
+ base_params, \
/*in_bus, out_bus,*/ pf, \
prefetch_access, hit_latency); \
Cache<CacheTags<t, comp>, b, c> *retval = \
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 44d7b4895..9504d16c6 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -148,7 +148,6 @@ Cache(const std::string &_name,
prefetchAccess(params.prefetchAccess),
tags(params.tags), missQueue(params.missQueue),
coherence(params.coherence), prefetcher(params.prefetcher),
- doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
hitLatency(params.hitLatency)
{
tags->setCache(this);
@@ -350,43 +349,6 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
}
template<class TagStore, class Buffering, class Coherence>
-void
-Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr)
-{
- // Need to temporarily move this blk into MSHRs
- MSHR *mshr = missQueue->allocateTargetList(addr);
- int lat;
- PacketList dummy;
- // Read the data into the mshr
- BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
- assert(dummy.empty());
- assert(mshr->pkt->flags & SATISFIED);
- // can overload order since it isn't used on non pending blocks
- mshr->order = blk->status;
- // temporarily remove the block from the cache.
- tags->invalidateBlk(addr);
-}
-
-template<class TagStore, class Buffering, class Coherence>
-void
-Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
-{
- // Need to temporarily move this blk into MSHRs
- assert(mshr->pkt->cmd == Packet::ReadReq);
- int lat;
- PacketList dummy;
- // Read the data into the mshr
- BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
- assert(dummy.empty());
- assert(mshr->pkt->flags & SATISFIED);
- // can overload order since it isn't used on non pending blocks
- mshr->order = blk->status;
- // temporarily remove the block from the cache.
- tags->invalidateBlk(mshr->pkt->getAddr());
-}
-
-
-template<class TagStore, class Buffering, class Coherence>
Packet *
Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
{
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 9d2a692cf..777443e5f 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -103,23 +103,6 @@ MSHRQueue::findPending(Packet * &pkt) const
return mshr;
}
}
-
- //need to check destination address for copies.
- //TEMP NOT DOING COPIES
-#if 0
- if (mshr->pkt->cmd == Copy) {
- Addr dest = mshr->pkt->dest;
- if (dest < pkt->addr) {
- if (dest + mshr->pkt->size > pkt->addr) {
- return mshr;
- }
- } else {
- if (pkt->addr + pkt->size > dest) {
- return mshr;
- }
- }
- }
-#endif
}
return NULL;
}
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index f9d4d7109..0fc54902b 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -322,25 +322,6 @@ public:
PacketList &writebacks)
{
}
-
- /**
- * Unimplemented. Perform a cache block copy from block aligned addresses.
- * @param source The block aligned source address.
- * @param dest The block aligned destination adddress.
- * @param asid The address space ID.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks)
- {
- }
-
- /**
- * Unimplemented.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks)
- {
- }
-
};
#endif
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 1377c8613..0fdfadd32 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -750,10 +750,6 @@ IIC::writeData(IICTag *blk, uint8_t *write_data, int size,
// can free data blocks
for (int i=num_subs; i < blk->numData; ++i){
// decrement reference count and compare to zero
- /**
- * @todo
- * Make this work with copying.
- */
if (--dataReferenceCount[blk->data_ptr[i]] == 0) {
freeDataBlock(blk->data_ptr[i]);
}
@@ -775,96 +771,6 @@ IIC::writeData(IICTag *blk, uint8_t *write_data, int size,
}
-/**
- * @todo This code can break if the src is evicted to get a tag for the dest.
- */
-void
-IIC::doCopy(Addr source, Addr dest, PacketList &writebacks)
-{
-//Copy unsuported now
-#if 0
- IICTag *dest_tag = findBlock(dest);
-
- if (dest_tag) {
- for (int i = 0; i < dest_tag->numData; ++i) {
- if (--dataReferenceCount[dest_tag->data_ptr[i]] == 0) {
- freeDataBlock(dest_tag->data_ptr[i]);
- }
- }
- // Reset replacement entry
- } else {
- dest_tag = getFreeTag(hash(dest), writebacks);
- dest_tag->re = (void*) repl->add(dest_tag - tagStore);
- dest_tag->set = hash(dest);
- dest_tag->tag = extractTag(dest);
- dest_tag->status = BlkValid | BlkWritable;
- }
- // Find the source tag here since it might move if we need to find a
- // tag for the destination.
- IICTag *src_tag = findBlock(source);
- assert(src_tag);
- assert(!cache->doData() || src_tag->size <= trivialSize
- || src_tag->numData > 0);
- // point dest to source data and inc counter
- for (int i = 0; i < src_tag->numData; ++i) {
- dest_tag->data_ptr[i] = src_tag->data_ptr[i];
- ++dataReferenceCount[dest_tag->data_ptr[i]];
- }
-
- // Maintain fast access data.
- memcpy(dest_tag->data, src_tag->data, blkSize);
-
- dest_tag->xc = src_tag->xc;
- dest_tag->size = src_tag->size;
- dest_tag->numData = src_tag->numData;
- if (src_tag->numData == 0) {
- // Data is stored in the trivial data, just copy it.
- memcpy(dest_tag->trivialData, src_tag->trivialData, src_tag->size);
- }
-
- dest_tag->status |= BlkDirty;
- if (dest_tag->size < blkSize) {
- dest_tag->status |= BlkCompressed;
- } else {
- dest_tag->status &= ~BlkCompressed;
- }
-#endif
-}
-
-void
-IIC::fixCopy(Packet * &pkt, PacketList &writebacks)
-{
-#if 0
- // if reference counter is greater than 1, do copy
- // else do write
- Addr blk_addr = blkAlign(pkt->getAddr);
- IICTag* blk = findBlock(blk_addr);
-
- if (blk->numData > 0 && dataReferenceCount[blk->data_ptr[0]] != 1) {
- // copy the data
- // Mark the block as referenced so it doesn't get replaced.
- blk->status |= BlkReferenced;
- for (int i = 0; i < blk->numData; ++i){
- unsigned long new_data = getFreeDataBlock(writebacks);
- // Need to refresh pointer
- /**
- * @todo Remove this refetch once we change IIC to pointer based
- */
- blk = findBlock(blk_addr);
- assert(blk);
- if (cache->doData()) {
- memcpy(&(dataBlks[new_data][0]),
- &(dataBlks[blk->data_ptr[i]][0]),
- subSize);
- }
- dataReferenceCount[blk->data_ptr[i]]--;
- dataReferenceCount[new_data]++;
- blk->data_ptr[i] = new_data;
- }
- }
-#endif
-}
-
void
IIC::cleanupRefs()
{
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 2357bdce3..905d480c5 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -498,22 +498,6 @@ class IIC : public BaseTags
PacketList & writebacks);
/**
- * Perform a block aligned copy from the source address to the destination.
- * @param source The block-aligned source address.
- * @param dest The block-aligned destination address.
- * @param asid The address space DI.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks);
-
- /**
- * If a block is currently marked copy on write, copy it before writing.
- * @param pkt The write request.
- * @param writebacks List for any generated writeback pktuests.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks);
-
- /**
* Called at end of simulation to complete average block reference stats.
*/
virtual void cleanupRefs();
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 976bbeff2..a9ae049c3 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -251,51 +251,6 @@ LRU::invalidateBlk(Addr addr)
}
void
-LRU::doCopy(Addr source, Addr dest, PacketList &writebacks)
-{
- assert(source == blkAlign(source));
- assert(dest == blkAlign(dest));
- LRUBlk *source_blk = findBlock(source);
- assert(source_blk);
- LRUBlk *dest_blk = findBlock(dest);
- if (dest_blk == NULL) {
- // Need to do a replacement
- Request *search = new Request(dest,1,0);
- Packet * pkt = new Packet(search, Packet::ReadReq, -1);
- BlkList dummy_list;
- dest_blk = findReplacement(pkt, writebacks, dummy_list);
- if (dest_blk->isValid() && dest_blk->isModified()) {
- // Need to writeback data.
-/* pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag,
- dest_blk->set),
- dest_blk->req->asid,
- dest_blk->xc,
- blkSize,
- dest_blk->data,
- dest_blk->size);
-*/
- Request *writebackReq = new Request(regenerateBlkAddr(dest_blk->tag,
- dest_blk->set),
- blkSize, 0);
- Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1);
- writeback->allocate();
- memcpy(writeback->getPtr<uint8_t>(),dest_blk->data, blkSize);
- writebacks.push_back(writeback);
- }
- dest_blk->tag = extractTag(dest);
- delete search;
- delete pkt;
- }
- /**
- * @todo Can't assume the status once we have coherence on copies.
- */
-
- // Set this block as readable, writeable, and dirty.
- dest_blk->status = 7;
- memcpy(dest_blk->data, source_blk->data, blkSize);
-}
-
-void
LRU::cleanupRefs()
{
for (int i = 0; i < numSets*assoc; ++i) {
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index a3a56a0e6..9f0a05ee8 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -303,22 +303,6 @@ public:
}
/**
- * Perform a block aligned copy from the source address to the destination.
- * @param source The block-aligned source address.
- * @param dest The block-aligned destination address.
- * @param asid The address space DI.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks);
-
- /**
- * No impl.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks)
- {
- }
-
- /**
* Called at end of simulation to complete average block reference stats.
*/
virtual void cleanupRefs();
diff --git a/src/mem/cache/tags/split.cc b/src/mem/cache/tags/split.cc
index 690eea22e..cad18e885 100644
--- a/src/mem/cache/tags/split.cc
+++ b/src/mem/cache/tags/split.cc
@@ -422,19 +422,6 @@ Split::invalidateBlk(Addr addr)
}
void
-Split::doCopy(Addr source, Addr dest, PacketList &writebacks)
-{
- if (lru->probe( source))
- lru->doCopy(source, dest, writebacks);
- else {
- if (lifo && lifo_net)
- lifo_net->doCopy(source, dest, writebacks);
- else if (lru_net)
- lru_net->doCopy(source, dest, writebacks);
- }
-}
-
-void
Split::cleanupRefs()
{
lru->cleanupRefs();
diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh
index f0091e971..708058e96 100644
--- a/src/mem/cache/tags/split.hh
+++ b/src/mem/cache/tags/split.hh
@@ -311,22 +311,6 @@ class Split : public BaseTags
}
/**
- * Perform a block aligned copy from the source address to the destination.
- * @param source The block-aligned source address.
- * @param dest The block-aligned destination address.
- * @param asid The address space DI.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks);
-
- /**
- * No impl.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks)
- {
- }
-
- /**
* Called at end of simulation to complete average block reference stats.
*/
virtual void cleanupRefs();
diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc
index 6fcbf3597..4e9375070 100644
--- a/src/mem/cache/tags/split_lifo.cc
+++ b/src/mem/cache/tags/split_lifo.cc
@@ -347,52 +347,6 @@ SplitLIFO::invalidateBlk(Addr addr)
}
void
-SplitLIFO::doCopy(Addr source, Addr dest, PacketList &writebacks)
-{
-//Copy Unsuported for now
-#if 0
- assert(source == blkAlign(source));
- assert(dest == blkAlign(dest));
- SplitBlk *source_blk = findBlock(source);
- assert(source_blk);
- SplitBlk *dest_blk = findBlock(dest);
- if (dest_blk == NULL) {
- // Need to do a replacement
- Packet * pkt = new Packet();
- pkt->paddr = dest;
- BlkList dummy_list;
- dest_blk = findReplacement(pkt, writebacks, dummy_list);
- if (dest_blk->isValid() && dest_blk->isModified()) {
- // Need to writeback data.
- pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag,
- dest_blk->set),
- dest_blk->xc,
- blkSize,
- (cache->doData())?dest_blk->data:0,
- dest_blk->size);
- writebacks.push_back(pkt);
- }
- dest_blk->tag = extractTag(dest);
- /**
- * @todo Do we need to pass in the execution context, or can we
- * assume its the same?
- */
- assert(source_blk->xc);
- dest_blk->xc = source_blk->xc;
- }
- /**
- * @todo Can't assume the status once we have coherence on copies.
- */
-
- // Set this block as readable, writeable, and dirty.
- dest_blk->status = 7;
- if (cache->doData()) {
- memcpy(dest_blk->data, source_blk->data, blkSize);
- }
-#endif
-}
-
-void
SplitLIFO::cleanupRefs()
{
for (int i = 0; i < numBlks; ++i) {
diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh
index 355a66162..ddc7fdeec 100644
--- a/src/mem/cache/tags/split_lifo.hh
+++ b/src/mem/cache/tags/split_lifo.hh
@@ -326,22 +326,6 @@ public:
}
/**
- * Perform a block aligned copy from the source address to the destination.
- * @param source The block-aligned source address.
- * @param dest The block-aligned destination address.
- * @param asid The address space DI.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks);
-
- /**
- * No impl.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks)
- {
- }
-
- /**
* Called at end of simulation to complete average block reference stats.
*/
virtual void cleanupRefs();
diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc
index 4381923bd..4aba1c37f 100644
--- a/src/mem/cache/tags/split_lru.cc
+++ b/src/mem/cache/tags/split_lru.cc
@@ -272,52 +272,6 @@ SplitLRU::invalidateBlk(Addr addr)
}
void
-SplitLRU::doCopy(Addr source, Addr dest, PacketList &writebacks)
-{
-//Copy not supported for now
-#if 0
- assert(source == blkAlign(source));
- assert(dest == blkAlign(dest));
- SplitBlk *source_blk = findBlock(source);
- assert(source_blk);
- SplitBlk *dest_blk = findBlock(dest);
- if (dest_blk == NULL) {
- // Need to do a replacement
- Packet * pkt = new Packet();
- pkt->paddr = dest;
- BlkList dummy_list;
- dest_blk = findReplacement(pkt, writebacks, dummy_list);
- if (dest_blk->isValid() && dest_blk->isModified()) {
- // Need to writeback data.
- pkt = buildWritebackReq(regenerateBlkAddr(dest_blk->tag,
- dest_blk->set),
- dest_blk->xc,
- blkSize,
- (cache->doData())?dest_blk->data:0,
- dest_blk->size);
- writebacks.push_back(pkt);
- }
- dest_blk->tag = extractTag(dest);
- /**
- * @todo Do we need to pass in the execution context, or can we
- * assume its the same?
- */
- assert(source_blk->xc);
- dest_blk->xc = source_blk->xc;
- }
- /**
- * @todo Can't assume the status once we have coherence on copies.
- */
-
- // Set this block as readable, writeable, and dirty.
- dest_blk->status = 7;
- if (cache->doData()) {
- memcpy(dest_blk->data, source_blk->data, blkSize);
- }
-#endif
-}
-
-void
SplitLRU::cleanupRefs()
{
for (int i = 0; i < numSets*assoc; ++i) {
diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh
index 72aebac9c..71f921177 100644
--- a/src/mem/cache/tags/split_lru.hh
+++ b/src/mem/cache/tags/split_lru.hh
@@ -309,22 +309,6 @@ public:
}
/**
- * Perform a block aligned copy from the source address to the destination.
- * @param source The block-aligned source address.
- * @param dest The block-aligned destination address.
- * @param asid The address space DI.
- * @param writebacks List for any generated writeback pktuests.
- */
- void doCopy(Addr source, Addr dest, PacketList &writebacks);
-
- /**
- * No impl.
- */
- void fixCopy(Packet * &pkt, PacketList &writebacks)
- {
- }
-
- /**
* Called at end of simulation to complete average block reference stats.
*/
virtual void cleanupRefs();
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index db58a177f..773a11bea 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -14,7 +14,6 @@ class BaseCache(MemObject):
"This cache connects to a compressed memory")
compression_latency = Param.Latency('0ns',
"Latency in cycles of compression algorithm")
- do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
lifo = Param.Bool(False,
"whether this NIC partition should use LIFO repl. policy")
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 05:18:55 +0000