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-rw-r--r--configs/common/MemConfig.py2
-rw-r--r--configs/dram/sweep.py4
-rw-r--r--src/mem/DRAMCtrl.py (renamed from src/mem/SimpleDRAM.py)24
-rw-r--r--src/mem/SConscript4
-rw-r--r--src/mem/dram_ctrl.cc (renamed from src/mem/simple_dram.cc)90
-rw-r--r--src/mem/dram_ctrl.hh (renamed from src/mem/simple_dram.hh)32
6 files changed, 78 insertions, 78 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index e5e701716..e954407bc 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -160,7 +160,7 @@ def config_mem(options, system):
ctrl = cls()
# Only do this for DRAMs
- if issubclass(cls, m5.objects.SimpleDRAM):
+ if issubclass(cls, m5.objects.DRAMCtrl):
# Inform each controller how many channels to account
# for
ctrl.channels = nbr_mem_ctrls
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 41b92d938..5981d59dd 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -86,8 +86,8 @@ MemConfig.config_mem(options, system)
# the following assumes that we are using the native DRAM
# controller, check to be sure
-if not isinstance(system.mem_ctrls[0], m5.objects.SimpleDRAM):
- fatal("This script assumes the memory is a SimpleDRAM subclass")
+if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
+ fatal("This script assumes the memory is a DRAMCtrl subclass")
# for now the generator assumes a single rank
system.mem_ctrls[0].ranks_per_channel = 1
diff --git a/src/mem/SimpleDRAM.py b/src/mem/DRAMCtrl.py
index 5c705f14e..3237e602d 100644
--- a/src/mem/SimpleDRAM.py
+++ b/src/mem/DRAMCtrl.py
@@ -59,13 +59,13 @@ class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
'close_adaptive']
-# SimpleDRAM is a single-channel single-ported DRAM controller model
+# DRAMCtrl is a single-channel single-ported DRAM controller model
# that aims to model the most important system-level performance
# effects of a DRAM without getting into too much detail of the DRAM
# itself.
-class SimpleDRAM(AbstractMemory):
- type = 'SimpleDRAM'
- cxx_header = "mem/simple_dram.hh"
+class DRAMCtrl(AbstractMemory):
+ type = 'DRAMCtrl'
+ cxx_header = "mem/dram_ctrl.hh"
# single-ported on the system interface side, instantiate with a
# bus in front of the controller for multiple ports
@@ -137,7 +137,7 @@ class SimpleDRAM(AbstractMemory):
# it is easier to also evaluate SDR memories like WideIO.
# This parameter has to account for burst length.
# Read/Write requests with data size larger than one full burst are broken
- # down into multiple requests in the SimpleDRAM controller
+ # down into multiple requests in the controller
tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
# time taken to complete one refresh cycle (N rows in all banks)
@@ -166,7 +166,7 @@ class SimpleDRAM(AbstractMemory):
# A single DDR3 x64 interface (one command and address bus), with
# default timings based on DDR3-1600 4 Gbit parts in an 8x8
# configuration, which would amount to 4 Gbyte of memory.
-class DDR3_1600_x64(SimpleDRAM):
+class DDR3_1600_x64(DRAMCtrl):
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
@@ -222,7 +222,7 @@ class DDR3_1600_x64(SimpleDRAM):
# to be manually set, depending on size of the memory to be
# simulated. By default DRAMSim2 has 2048MB of memory with a single
# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
-class DDR3_1333_x64_DRAMSim2(SimpleDRAM):
+class DDR3_1333_x64_DRAMSim2(DRAMCtrl):
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
@@ -268,7 +268,7 @@ class DDR3_1333_x64_DRAMSim2(SimpleDRAM):
# A single LPDDR2-S4 x32 interface (one command/address bus), with
# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
# configuration.
-class LPDDR2_S4_1066_x32(SimpleDRAM):
+class LPDDR2_S4_1066_x32(DRAMCtrl):
# 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32
@@ -302,7 +302,7 @@ class LPDDR2_S4_1066_x32(SimpleDRAM):
# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
# Note this is a BL8 DDR device.
# Requests larger than 32 bytes are broken down into multiple requests
- # in the SimpleDRAM controller
+ # in the controller
tBURST = '7.5ns'
# LPDDR2-S4, 4 Gbit
@@ -321,7 +321,7 @@ class LPDDR2_S4_1066_x32(SimpleDRAM):
# A single WideIO x128 interface (one command and address bus), with
# default timings based on an estimated WIO-200 8 Gbit part.
-class WideIO_200_x128(SimpleDRAM):
+class WideIO_200_x128(DRAMCtrl):
# 1x128 configuration, 1 device with a 128-bit interface
device_bus_width = 128
@@ -370,7 +370,7 @@ class WideIO_200_x128(SimpleDRAM):
# A single LPDDR3 x32 interface (one command/address bus), with
# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
# configuration
-class LPDDR3_1600_x32(SimpleDRAM):
+class LPDDR3_1600_x32(DRAMCtrl):
# 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32
@@ -403,7 +403,7 @@ class LPDDR3_1600_x32(SimpleDRAM):
# 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
# Note this is a BL8 DDR device.
# Requests larger than 32 bytes are broken down into multiple requests
- # in the SimpleDRAM controller
+ # in the controller
tBURST = '5ns'
# LPDDR3, 4 Gb
diff --git a/src/mem/SConscript b/src/mem/SConscript
index ddd57d11b..c513004d2 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -40,15 +40,16 @@ SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
+SimObject('DRAMCtrl.py')
SimObject('MemObject.py')
SimObject('SimpleMemory.py')
-SimObject('SimpleDRAM.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('coherent_bus.cc')
+Source('dram_ctrl.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_bus.cc')
@@ -59,7 +60,6 @@ Source('tport.cc')
Source('port_proxy.cc')
Source('simple_mem.cc')
Source('physical.cc')
-Source('simple_dram.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')
diff --git a/src/mem/simple_dram.cc b/src/mem/dram_ctrl.cc
index cb640dcb2..971c7227d 100644
--- a/src/mem/simple_dram.cc
+++ b/src/mem/dram_ctrl.cc
@@ -42,16 +42,16 @@
* Neha Agarwal
*/
-#include "base/trace.hh"
#include "base/bitfield.hh"
-#include "debug/Drain.hh"
+#include "base/trace.hh"
#include "debug/DRAM.hh"
-#include "mem/simple_dram.hh"
+#include "debug/Drain.hh"
+#include "mem/dram_ctrl.hh"
#include "sim/system.hh"
using namespace std;
-SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) :
+DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
AbstractMemory(p),
port(name() + ".port", *this),
retryRdReq(false), retryWrReq(false),
@@ -133,17 +133,17 @@ SimpleDRAM::SimpleDRAM(const SimpleDRAMParams* p) :
}
void
-SimpleDRAM::init()
+DRAMCtrl::init()
{
if (!port.isConnected()) {
- fatal("SimpleDRAM %s is unconnected!\n", name());
+ fatal("DRAMCtrl %s is unconnected!\n", name());
} else {
port.sendRangeChange();
}
}
void
-SimpleDRAM::startup()
+DRAMCtrl::startup()
{
// update the start tick for the precharge accounting to the
// current tick
@@ -157,7 +157,7 @@ SimpleDRAM::startup()
}
Tick
-SimpleDRAM::recvAtomic(PacketPtr pkt)
+DRAMCtrl::recvAtomic(PacketPtr pkt)
{
DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
@@ -174,7 +174,7 @@ SimpleDRAM::recvAtomic(PacketPtr pkt)
}
bool
-SimpleDRAM::readQueueFull(unsigned int neededEntries) const
+DRAMCtrl::readQueueFull(unsigned int neededEntries) const
{
DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n",
readBufferSize, readQueue.size() + respQueue.size(),
@@ -185,15 +185,15 @@ SimpleDRAM::readQueueFull(unsigned int neededEntries) const
}
bool
-SimpleDRAM::writeQueueFull(unsigned int neededEntries) const
+DRAMCtrl::writeQueueFull(unsigned int neededEntries) const
{
DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n",
writeBufferSize, writeQueue.size(), neededEntries);
return (writeQueue.size() + neededEntries) > writeBufferSize;
}
-SimpleDRAM::DRAMPacket*
-SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
+DRAMCtrl::DRAMPacket*
+DRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
bool isRead)
{
// decode the address based on the address mapping scheme, with
@@ -293,7 +293,7 @@ SimpleDRAM::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size,
}
void
-SimpleDRAM::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
+DRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
{
// only add to the read queue here. whenever the request is
// eventually done, set the readyTime, and call schedule()
@@ -382,7 +382,7 @@ SimpleDRAM::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
}
void
-SimpleDRAM::processWriteEvent()
+DRAMCtrl::processWriteEvent()
{
assert(!writeQueue.empty());
@@ -439,7 +439,7 @@ SimpleDRAM::processWriteEvent()
void
-SimpleDRAM::triggerWrites()
+DRAMCtrl::triggerWrites()
{
DPRINTF(DRAM, "Writes triggered at %lld\n", curTick());
// Flag variable to stop any more read scheduling
@@ -455,7 +455,7 @@ SimpleDRAM::triggerWrites()
}
void
-SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
+DRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
{
// only add to the write queue here. whenever the request is
// eventually done, set the readyTime, and call schedule()
@@ -567,7 +567,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
}
void
-SimpleDRAM::printParams() const
+DRAMCtrl::printParams() const
{
// Sanity check print of important parameters
DPRINTF(DRAM,
@@ -618,7 +618,7 @@ SimpleDRAM::printParams() const
}
void
-SimpleDRAM::printQs() const {
+DRAMCtrl::printQs() const {
DPRINTF(DRAM, "===READ QUEUE===\n\n");
for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) {
DPRINTF(DRAM, "Read %lu\n", (*i)->addr);
@@ -634,7 +634,7 @@ SimpleDRAM::printQs() const {
}
bool
-SimpleDRAM::recvTimingReq(PacketPtr pkt)
+DRAMCtrl::recvTimingReq(PacketPtr pkt)
{
/// @todo temporary hack to deal with memory corruption issues until
/// 4-phase transactions are complete
@@ -705,7 +705,7 @@ SimpleDRAM::recvTimingReq(PacketPtr pkt)
}
void
-SimpleDRAM::processRespondEvent()
+DRAMCtrl::processRespondEvent()
{
DPRINTF(DRAM,
"processRespondEvent(): Some req has reached its readyTime\n");
@@ -755,7 +755,7 @@ SimpleDRAM::processRespondEvent()
}
void
-SimpleDRAM::chooseNextWrite()
+DRAMCtrl::chooseNextWrite()
{
// This method does the arbitration between write requests. The
// chosen packet is simply moved to the head of the write
@@ -779,7 +779,7 @@ SimpleDRAM::chooseNextWrite()
}
bool
-SimpleDRAM::chooseNextRead()
+DRAMCtrl::chooseNextRead()
{
// This method does the arbitration between read requests. The
// chosen packet is simply moved to the head of the queue. The
@@ -807,7 +807,7 @@ SimpleDRAM::chooseNextRead()
}
void
-SimpleDRAM::reorderQueue(std::deque<DRAMPacket*>& queue)
+DRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue)
{
// Only determine this when needed
uint64_t earliest_banks = 0;
@@ -847,7 +847,7 @@ SimpleDRAM::reorderQueue(std::deque<DRAMPacket*>& queue)
}
void
-SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency)
+DRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
{
DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr());
@@ -879,7 +879,7 @@ SimpleDRAM::accessAndRespond(PacketPtr pkt, Tick static_latency)
}
pair<Tick, Tick>
-SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
+DRAMCtrl::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
{
// If a request reaches a bank at tick 'inTime', how much time
// *after* that does it take to finish the request, depending
@@ -963,13 +963,13 @@ SimpleDRAM::estimateLatency(DRAMPacket* dram_pkt, Tick inTime)
}
void
-SimpleDRAM::processNextReqEvent()
+DRAMCtrl::processNextReqEvent()
{
scheduleNextReq();
}
void
-SimpleDRAM::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank)
+DRAMCtrl::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank)
{
assert(0 <= rank && rank < ranksPerChannel);
assert(actTicks[rank].size() == activationLimit);
@@ -1035,7 +1035,7 @@ SimpleDRAM::recordActivate(Tick act_tick, uint8_t rank, uint8_t bank)
}
void
-SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
+DRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt)
{
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
@@ -1237,7 +1237,7 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
}
void
-SimpleDRAM::moveToRespQ()
+DRAMCtrl::moveToRespQ()
{
// Remove from read queue
DRAMPacket* dram_pkt = readQueue.front();
@@ -1278,7 +1278,7 @@ SimpleDRAM::moveToRespQ()
}
void
-SimpleDRAM::scheduleNextReq()
+DRAMCtrl::scheduleNextReq()
{
DPRINTF(DRAM, "Reached scheduleNextReq()\n");
@@ -1297,7 +1297,7 @@ SimpleDRAM::scheduleNextReq()
}
Tick
-SimpleDRAM::maxBankFreeAt() const
+DRAMCtrl::maxBankFreeAt() const
{
Tick banksFree = 0;
@@ -1309,7 +1309,7 @@ SimpleDRAM::maxBankFreeAt() const
}
uint64_t
-SimpleDRAM::minBankFreeAt(const deque<DRAMPacket*>& queue) const
+DRAMCtrl::minBankFreeAt(const deque<DRAMPacket*>& queue) const
{
uint64_t bank_mask = 0;
Tick freeAt = MaxTick;
@@ -1341,7 +1341,7 @@ SimpleDRAM::minBankFreeAt(const deque<DRAMPacket*>& queue) const
}
void
-SimpleDRAM::processRefreshEvent()
+DRAMCtrl::processRefreshEvent()
{
DPRINTF(DRAM, "Refreshing at tick %ld\n", curTick());
@@ -1361,7 +1361,7 @@ SimpleDRAM::processRefreshEvent()
}
void
-SimpleDRAM::regStats()
+DRAMCtrl::regStats()
{
using namespace Stats;
@@ -1624,14 +1624,14 @@ SimpleDRAM::regStats()
}
void
-SimpleDRAM::recvFunctional(PacketPtr pkt)
+DRAMCtrl::recvFunctional(PacketPtr pkt)
{
// rely on the abstract memory
functionalAccess(pkt);
}
BaseSlavePort&
-SimpleDRAM::getSlavePort(const string &if_name, PortID idx)
+DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
{
if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx);
@@ -1641,7 +1641,7 @@ SimpleDRAM::getSlavePort(const string &if_name, PortID idx)
}
unsigned int
-SimpleDRAM::drain(DrainManager *dm)
+DRAMCtrl::drain(DrainManager *dm)
{
unsigned int count = port.drain(dm);
@@ -1670,13 +1670,13 @@ SimpleDRAM::drain(DrainManager *dm)
return count;
}
-SimpleDRAM::MemoryPort::MemoryPort(const std::string& name, SimpleDRAM& _memory)
+DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
: QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
memory(_memory)
{ }
AddrRangeList
-SimpleDRAM::MemoryPort::getAddrRanges() const
+DRAMCtrl::MemoryPort::getAddrRanges() const
{
AddrRangeList ranges;
ranges.push_back(memory.getAddrRange());
@@ -1684,7 +1684,7 @@ SimpleDRAM::MemoryPort::getAddrRanges() const
}
void
-SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt)
+DRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
{
pkt->pushLabel(memory.name());
@@ -1699,20 +1699,20 @@ SimpleDRAM::MemoryPort::recvFunctional(PacketPtr pkt)
}
Tick
-SimpleDRAM::MemoryPort::recvAtomic(PacketPtr pkt)
+DRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
{
return memory.recvAtomic(pkt);
}
bool
-SimpleDRAM::MemoryPort::recvTimingReq(PacketPtr pkt)
+DRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
{
// pass it to the memory controller
return memory.recvTimingReq(pkt);
}
-SimpleDRAM*
-SimpleDRAMParams::create()
+DRAMCtrl*
+DRAMCtrlParams::create()
{
- return new SimpleDRAM(this);
+ return new DRAMCtrl(this);
}
diff --git a/src/mem/simple_dram.hh b/src/mem/dram_ctrl.hh
index e3755fec0..e327f0796 100644
--- a/src/mem/simple_dram.hh
+++ b/src/mem/dram_ctrl.hh
@@ -44,11 +44,11 @@
/**
* @file
- * SimpleDRAM declaration
+ * DRAMCtrl declaration
*/
-#ifndef __MEM_SIMPLE_DRAM_HH__
-#define __MEM_SIMPLE_DRAM_HH__
+#ifndef __MEM_DRAM_CTRL_HH__
+#define __MEM_DRAM_CTRL_HH__
#include <deque>
@@ -58,13 +58,13 @@
#include "enums/PageManage.hh"
#include "mem/abstract_mem.hh"
#include "mem/qport.hh"
-#include "params/SimpleDRAM.hh"
+#include "params/DRAMCtrl.hh"
#include "sim/eventq.hh"
/**
- * The simple DRAM is a basic single-channel memory controller aiming
- * to mimic a high-level DRAM controller and the most important timing
- * constraints associated with the DRAM. The focus is really on
+ * The DRAM controller is a basic single-channel memory controller
+ * aiming to mimic a high-level DRAM controller and the most important
+ * timing constraints associated with the DRAM. The focus is really on
* modelling the impact on the system rather than the DRAM itself,
* hence the focus is on the controller model and not on the
* memory. By adhering to the correct timing constraints, ultimately
@@ -80,7 +80,7 @@
* wide range of memory technologies, and also collect statistics
* about the use of the memory.
*/
-class SimpleDRAM : public AbstractMemory
+class DRAMCtrl : public AbstractMemory
{
private:
@@ -91,11 +91,11 @@ class SimpleDRAM : public AbstractMemory
{
SlavePacketQueue queue;
- SimpleDRAM& memory;
+ DRAMCtrl& memory;
public:
- MemoryPort(const std::string& name, SimpleDRAM& _memory);
+ MemoryPort(const std::string& name, DRAMCtrl& _memory);
protected:
@@ -255,16 +255,16 @@ class SimpleDRAM : public AbstractMemory
* in these methods
*/
void processWriteEvent();
- EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
+ EventWrapper<DRAMCtrl, &DRAMCtrl::processWriteEvent> writeEvent;
void processRespondEvent();
- EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
+ EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
void processRefreshEvent();
- EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
+ EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
void processNextReqEvent();
- EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
+ EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
/**
@@ -623,7 +623,7 @@ class SimpleDRAM : public AbstractMemory
void regStats();
- SimpleDRAM(const SimpleDRAMParams* p);
+ DRAMCtrl(const DRAMCtrlParams* p);
unsigned int drain(DrainManager* dm);
@@ -641,4 +641,4 @@ class SimpleDRAM : public AbstractMemory
};
-#endif //__MEM_SIMPLE_DRAM_HH__
+#endif //__MEM_DRAM_CTRL_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 14:59:06 +0000