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-rw-r--r--configs/example/fs.py16
-rw-r--r--configs/example/ruby_direct_test.py4
-rw-r--r--configs/example/ruby_mem_test.py8
-rw-r--r--configs/example/ruby_network_test.py2
-rw-r--r--configs/example/ruby_random_test.py6
-rw-r--r--configs/example/se.py4
-rw-r--r--configs/ruby/Ruby.py2
-rw-r--r--tests/configs/memtest-ruby.py4
-rw-r--r--tests/configs/pc-simple-timing-ruby.py16
-rw-r--r--tests/configs/rubytest-ruby.py4
-rw-r--r--tests/configs/simple-timing-mp-ruby.py4
-rw-r--r--tests/configs/simple-timing-ruby.py4
12 files changed, 37 insertions, 37 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 6c71ef432..584748299 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -149,18 +149,18 @@ def build_test_system(np):
cpu.createThreads()
cpu.createInterruptController()
- cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
+ cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
+ cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
- cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
+ cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
+ cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
- test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
+ test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index f511b0139..36314fbfb 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -115,9 +115,9 @@ Ruby.create_system(options, system)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 064140064..99f6f4a09 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -144,26 +144,26 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
#
system.ruby.randomization = True
-assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby._cpu_ruby_ports[i].slave
+ cpu.test = system.ruby._cpu_ports[i].slave
cpu.functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
- system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
+ system.ruby._cpu_ports[i].deadlock_threshold = 5000000
#
# Ruby doesn't need the backing image of memory when running with
# the tester.
#
- system.ruby._cpu_ruby_ports[i].access_phys_mem = False
+ system.ruby._cpu_ports[i].access_phys_mem = False
for (i, dma) in enumerate(dmas):
#
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index e1ec325bb..b9ca6ddf0 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -120,7 +120,7 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
i = 0
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 24c172b28..32d5cf34d 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -112,9 +112,9 @@ Ruby.create_system(options, system)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
-tester.num_cpus = len(system.ruby._cpu_ruby_ports)
+tester.num_cpus = len(system.ruby._cpu_ports)
#
# The tester is most effective when randomization is turned on and
@@ -122,7 +122,7 @@ tester.num_cpus = len(system.ruby._cpu_ruby_ports)
#
system.ruby.randomization = True
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
diff --git a/configs/example/se.py b/configs/example/se.py
index 34a3f045e..92a950319 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -233,10 +233,10 @@ if options.ruby:
null = True)
options.use_map = True
Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+ assert(options.num_cpus == len(system.ruby._cpu_ports))
for i in xrange(np):
- ruby_port = system.ruby._cpu_ruby_ports[i]
+ ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 75b891b1f..5e987f0ac 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -200,6 +200,6 @@ def create_system(options, system, piobus = None, dma_ports = []):
if buildEnv['TARGET_ISA'] == "x86":
cpu_seq.pio_slave_port = piobus.master
- ruby._cpu_ruby_ports = cpu_sequencers
+ ruby._cpu_ports = cpu_sequencers
ruby.num_of_sequencers = len(cpu_sequencers)
ruby.random_seed = options.random_seed
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 8535a19a4..071f3a7b5 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -104,9 +104,9 @@ Ruby.create_system(options, system)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ports))
-for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
+for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
#
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 3d1b78324..2ac571c83 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -78,16 +78,16 @@ for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
- cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
+ cpu.icache_port = system.ruby._cpu_ports[i].slave
+ cpu.dcache_port = system.ruby._cpu_ports[i].slave
+ cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.interrupts.pio = system.ruby._cpu_ports[i].master
+ cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave
+ cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master
# Set access_phys_mem to True for ruby port
- system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+ system.ruby._cpu_ports[i].access_phys_mem = True
system.physmem = [DDR3_1600_x64(range = r)
for r in system.mem_ranges]
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 9fe85d14f..f2c88c92b 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -92,7 +92,7 @@ Ruby.create_system(options, system)
system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
#
# The tester is most effective when randomization is turned on and
@@ -100,7 +100,7 @@ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
system.ruby.randomization = True
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 835428c3b..f7dfb5c5c 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -83,7 +83,7 @@ Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
@@ -92,7 +92,7 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
+ cpu.connectAllPorts(system.ruby._cpu_ports[i])
# -----------------------
# run simulation
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 94cb15ed4..90af9c920 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -85,7 +85,7 @@ Ruby.create_system(options, system)
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(len(system.ruby._cpu_ruby_ports) == 1)
+assert(len(system.ruby._cpu_ports) == 1)
# create the interrupt controller
cpu.createInterruptController()
@@ -94,7 +94,7 @@ cpu.createInterruptController()
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
+cpu.connectAllPorts(system.ruby._cpu_ports[0])
# -----------------------
# run simulation
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 21:13:31 +0000