summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/dev/x86/Cmos.py38
-rw-r--r--src/dev/x86/PC.py3
-rw-r--r--src/dev/x86/SConscript5
-rw-r--r--src/dev/x86/cmos.cc (renamed from src/dev/x86/south_bridge/cmos.cc)31
-rw-r--r--src/dev/x86/cmos.hh (renamed from src/dev/x86/south_bridge/cmos.hh)30
-rw-r--r--src/dev/x86/south_bridge/SConscript1
-rw-r--r--src/dev/x86/south_bridge/SouthBridge.py2
-rw-r--r--src/dev/x86/south_bridge/south_bridge.cc2
-rw-r--r--src/dev/x86/south_bridge/south_bridge.hh4
9 files changed, 79 insertions, 37 deletions
diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py
new file mode 100644
index 000000000..c786eda36
--- /dev/null
+++ b/src/dev/x86/Cmos.py
@@ -0,0 +1,38 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice
+
+class Cmos(BasicPioDevice):
+ type = 'Cmos'
+ cxx_class='X86ISA::Cmos'
+ time = Param.Time('01/01/2009',
+ "System time to use ('Now' for actual time)")
+ pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 5165308ed..6460e7402 100644
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -29,6 +29,7 @@
from m5.params import *
from m5.proxy import *
+from Cmos import Cmos
from Device import IsaFake
from Pci import PciConfigAll
from Platform import Platform
@@ -47,6 +48,7 @@ class PC(Platform):
pciconfig = PciConfigAll()
south_bridge = SouthBridge()
+ cmos = Cmos(pio_addr=x86IOAddress(0x70))
# "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
@@ -63,6 +65,7 @@ class PC(Platform):
def attachIO(self, bus):
self.south_bridge.pio = bus.port
+ self.cmos.pio = bus.port
self.i_dont_exist.pio = bus.port
self.behind_pci.pio = bus.port
self.com_1.pio = bus.port
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 463344001..c9ac19a91 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -32,5 +32,8 @@ Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
SimObject('PC.py')
-
Source('pc.cc')
+
+ SimObject('Cmos.py')
+ Source('cmos.cc')
+ TraceFlag('CMOS', 'Accesses to CMOS devices')
diff --git a/src/dev/x86/south_bridge/cmos.cc b/src/dev/x86/cmos.cc
index 164b23d84..5bbded260 100644
--- a/src/dev/x86/south_bridge/cmos.cc
+++ b/src/dev/x86/cmos.cc
@@ -28,14 +28,14 @@
* Authors: Gabe Black
*/
-#include "dev/x86/south_bridge/cmos.hh"
+#include "dev/x86/cmos.hh"
#include "mem/packet_access.hh"
Tick
X86ISA::Cmos::read(PacketPtr pkt)
{
assert(pkt->getSize() == 1);
- switch(pkt->getAddr() - addrRange.start)
+ switch(pkt->getAddr() - pioAddr)
{
case 0x0:
pkt->set(address);
@@ -53,7 +53,7 @@ Tick
X86ISA::Cmos::write(PacketPtr pkt)
{
assert(pkt->getSize() == 1);
- switch(pkt->getAddr() - addrRange.start)
+ switch(pkt->getAddr() - pioAddr)
{
case 0x0:
address = pkt->get<uint8_t>();
@@ -71,12 +71,17 @@ uint8_t
X86ISA::Cmos::readRegister(uint8_t reg)
{
assert(reg < numRegs);
+ uint8_t val;
if (reg <= 0xD) {
- return rtc.readData(reg);
+ val = rtc.readData(reg);
+ DPRINTF(CMOS,
+ "Reading CMOS RTC reg %x as %x.\n", reg, val);
} else {
- warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]);
+ val = regs[reg];
+ DPRINTF(CMOS,
+ "Reading non-volitile CMOS address %x as %x.\n", reg, val);
}
- return regs[reg];
+ return val;
}
void
@@ -84,10 +89,18 @@ X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
{
assert(reg < numRegs);
if (reg <= 0xD) {
+ DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n",
+ reg, val);
rtc.writeData(reg, val);
- return;
} else {
- warn("Writing non-volitile CMOS address %x with %x.\n", reg, val);
+ DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n",
+ reg, val);
+ regs[reg] = val;
}
- regs[reg] = val;
+}
+
+X86ISA::Cmos *
+CmosParams::create()
+{
+ return new X86ISA::Cmos(this);
}
diff --git a/src/dev/x86/south_bridge/cmos.hh b/src/dev/x86/cmos.hh
index 585d9351e..04df9dd04 100644
--- a/src/dev/x86/south_bridge/cmos.hh
+++ b/src/dev/x86/cmos.hh
@@ -28,20 +28,21 @@
* Authors: Gabe Black
*/
-#ifndef __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
-#define __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+#ifndef __DEV_X86_CMOS_HH__
+#define __DEV_X86_CMOS_HH__
-#include "arch/x86/x86_traits.hh"
-#include "base/range.hh"
+#include "dev/io_device.hh"
#include "dev/mc146818.hh"
-#include "dev/x86/south_bridge/sub_device.hh"
+#include "params/Cmos.hh"
namespace X86ISA
{
-class Cmos : public SubDevice
+class Cmos : public BasicPioDevice
{
protected:
+ Tick latency;
+
uint8_t address;
static const int numRegs = 128;
@@ -67,19 +68,12 @@ class Cmos : public SubDevice
} rtc;
public:
+ typedef CmosParams Params;
- Cmos(EventManager *em, Tick _latency, struct tm time) :
- SubDevice(_latency), rtc(em, "rtc", time, true, ULL(5000000000))
- {
- memset(regs, 0, numRegs * sizeof(uint8_t));
- address = 0;
- }
-
- Cmos(EventManager *em, Addr start, Addr size,
- Tick _latency, struct tm time) :
- SubDevice(start, size, _latency),
- rtc(em, "rtc", time, true, ULL(5000000000))
+ Cmos(const Params *p) : BasicPioDevice(p), latency(p->pio_latency),
+ rtc(this, "rtc", p->time, true, ULL(5000000000))
{
+ pioSize = 2;
memset(regs, 0, numRegs * sizeof(uint8_t));
address = 0;
}
@@ -91,4 +85,4 @@ class Cmos : public SubDevice
}; // namespace X86ISA
-#endif //__DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+#endif //__DEV_X86_CMOS_HH__
diff --git a/src/dev/x86/south_bridge/SConscript b/src/dev/x86/south_bridge/SConscript
index d01106c5c..edc091e12 100644
--- a/src/dev/x86/south_bridge/SConscript
+++ b/src/dev/x86/south_bridge/SConscript
@@ -36,7 +36,6 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
Source('south_bridge.cc')
# Sub devices
- Source('cmos.cc')
Source('i8254.cc')
Source('i8259.cc')
Source('speaker.cc')
diff --git a/src/dev/x86/south_bridge/SouthBridge.py b/src/dev/x86/south_bridge/SouthBridge.py
index 9e1b66896..bec3c4223 100644
--- a/src/dev/x86/south_bridge/SouthBridge.py
+++ b/src/dev/x86/south_bridge/SouthBridge.py
@@ -32,6 +32,4 @@ from Device import PioDevice
class SouthBridge(PioDevice):
type = 'SouthBridge'
- time = Param.Time('01/01/2009',
- "System time to use ('Now' for actual time)")
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/south_bridge/south_bridge.cc b/src/dev/x86/south_bridge/south_bridge.cc
index fda5acbda..6edb3364c 100644
--- a/src/dev/x86/south_bridge/south_bridge.cc
+++ b/src/dev/x86/south_bridge/south_bridge.cc
@@ -70,13 +70,11 @@ SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
pic1(0x20, 2, p->pio_latency),
pic2(0xA0, 2, p->pio_latency),
pit(this, p->name + ".pit", 0x40, 4, p->pio_latency),
- cmos(this, 0x70, 2, p->pio_latency, p->time),
speaker(&pit, 0x61, 1, p->pio_latency)
{
addDevice(pic1);
addDevice(pic2);
addDevice(pit);
- addDevice(cmos);
addDevice(speaker);
// Let the platform know where we are
diff --git a/src/dev/x86/south_bridge/south_bridge.hh b/src/dev/x86/south_bridge/south_bridge.hh
index 203cb6ee2..6510ab348 100644
--- a/src/dev/x86/south_bridge/south_bridge.hh
+++ b/src/dev/x86/south_bridge/south_bridge.hh
@@ -33,7 +33,6 @@
#include "base/range_map.hh"
#include "dev/io_device.hh"
-#include "dev/x86/south_bridge/cmos.hh"
#include "dev/x86/south_bridge/i8254.hh"
#include "dev/x86/south_bridge/i8259.hh"
#include "dev/x86/south_bridge/speaker.hh"
@@ -60,9 +59,6 @@ class SouthBridge : public PioDevice
// I8254 Programmable Interval Timer
X86ISA::I8254 pit;
- // CMOS apperature
- X86ISA::Cmos cmos;
-
// PC speaker
X86ISA::Speaker speaker;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 00:04:44 +0000