diff options
| -rw-r--r-- | src/arch/arm/miscregs.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index a9031fe0e..c0b6aa5d5 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -922,8 +922,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) if (el == EL0 && !sctlr.dze) return false; } - if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt || - reg == MISCREG_DC_IVAC_Xt) { + if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) { SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1); if (el == EL0 && !sctlr.uci) return false; @@ -3557,7 +3556,7 @@ ISA::initializeMiscRegMetadata() .writes(1).exceptUserMode(); InitReg(MISCREG_DC_IVAC_Xt) .warnNotFail() - .writes(1); + .writes(1).exceptUserMode(); InitReg(MISCREG_DC_ISW_Xt) .warnNotFail() .writes(1).exceptUserMode(); |