6 files changed, 0 insertions, 40 deletions

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 151ea7d7c..53ade4719 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -66,13 +66,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-union AnyReg
-{
-    IntReg  intreg;
-    FloatReg   fpreg;
-    MiscReg ctrlreg;
-};
-
 enum MiscRegIndex
 {
     MISCREG_FPCR = NumInternalProcRegs,
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 0a617e4dc..e7defd182 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -119,13 +119,6 @@ const int SyscallNumReg = ReturnValueReg;
 const int SyscallPseudoReturnReg = ReturnValueReg;
 const int SyscallSuccessReg = ReturnValueReg;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    CCReg    ccreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace ArmISA
 
 #endif
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index b44283d35..55c2dee03 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -299,12 +299,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace MipsISA
 
 #endif
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 4e8c9e9f4..adbaae539 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -95,12 +95,6 @@ const int SyscallNumReg = 0;
 const int SyscallPseudoReturnReg = 3;
 const int SyscallSuccessReg = 3;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 enum MiscIntRegNums {
     INTREG_CR = NumIntArchRegs,
     INTREG_XER,
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 596fdf4d0..a7f4d2a15 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -62,13 +62,6 @@ using VecRegContainer = VecReg::Container;
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpreg;
-    MiscReg ctrlreg;
-} AnyReg;
-
 // semantically meaningful register indices
 const int ZeroReg = 0;      // architecturally meaningful
 // the rest of these depend on the ABI
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 9db3349f0..c2977f8a2 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -107,13 +107,6 @@ constexpr unsigned NumVecRegs = 1;
 //technically for x87 (80 bits) or at all for xmm (128 bits)
 typedef double FloatReg;
 typedef uint64_t FloatRegBits;
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpReg;
-    CCReg ccReg;
-    MiscReg ctrlReg;
-} AnyReg;
 
 } // namespace X86ISA