diff options
| -rw-r--r-- | arch/SConscript | 10 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 150 | ||||
| -rw-r--r-- | base/loader/ecoff_object.cc | 1 | ||||
| -rw-r--r-- | base/loader/elf_object.cc | 1 | ||||
| -rw-r--r-- | cpu/pc_event.hh | 2 | ||||
| -rw-r--r-- | cpu/simple/cpu.cc | 1 | ||||
| -rw-r--r-- | cpu/static_inst.hh | 1 | ||||
| -rw-r--r-- | mem/port.hh | 1 | ||||
| -rw-r--r-- | sim/faults.cc | 1 | ||||
| -rw-r--r-- | sim/system.hh | 3 |
10 files changed, 18 insertions, 153 deletions
diff --git a/arch/SConscript b/arch/SConscript index 0533261a2..4b1a7d406 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -45,13 +45,17 @@ sources = [] # List of headers to generate isa_switch_hdrs = Split(''' + arguments.hh + constants.hh + faults.hh isa_traits.hh - tlb.hh process.hh - arguments.hh + registerfile.hh stacktrace.hh + tlb.hh + types.hh + utility.hh vtophys.hh - faults.hh ''') # Generate the header. target[0] is the full path of the output diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index ea5558364..49127a0bd 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -34,17 +34,10 @@ using namespace LittleEndianGuest; #include "arch/alpha/types.hh" #include "arch/alpha/constants.hh" -#include "base/misc.hh" +#include "arch/alpha/registerfile.hh" #include "config/full_system.hh" #include "sim/host.hh" -#include "sim/faults.hh" -class ExecContext; -class FastCPU; -class FullCPU; -class Checkpoint; - -class StaticInst; class StaticInstPtr; #if !FULL_SYSTEM @@ -86,13 +79,6 @@ class SyscallReturn { namespace AlphaISA { - typedef IntReg IntRegFile[NumIntRegs]; - - typedef union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - } FloatRegFile; - // redirected register map, really only used for the full system case. extern const int reg_redir[NumIntRegs]; @@ -101,130 +87,9 @@ extern const int reg_redir[NumIntRegs]; #include "arch/alpha/isa_fullsys_traits.hh" #endif - class MiscRegFile { - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - - public: - MiscReg readReg(int misc_reg); - - //These functions should be removed once the simplescalar cpu model - //has been replaced. - int getInstAsid(); - int getDataAsid(); - - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); - - Fault setReg(int misc_reg, const MiscReg &val); - - Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); - - void copyMiscRegs(ExecContext *xc); - -#if FULL_SYSTEM - protected: - typedef uint64_t InternalProcReg; - - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - private: - InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); - - Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); - - void copyIprs(ExecContext *xc); -#endif - friend class RegFile; - }; - - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; - -#if FULL_SYSTEM - int intrflag; // interrupt flag - inline int instAsid() - { return miscRegs.getInstAsid(); } - inline int dataAsid() - { return miscRegs.getDataAsid(); } -#endif // FULL_SYSTEM - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - - static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); StaticInstPtr decodeInst(ExtMachInst); - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); - } - - static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 9 && reg <= 15); - } - - static inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - static inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - static inline Addr alignAddress(const Addr &addr, - unsigned int nbytes) { - return (addr & ~(nbytes - 1)); - } - - // Instruction address compression hooks - static inline Addr realPCToFetchPC(const Addr &addr) { - return addr; - } - - static inline Addr fetchPCToRealPC(const Addr &addr) { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - static inline size_t fetchInstSize() { - return sizeof(MachInst); - } - - static inline MachInst makeRegisterCopy(int dest, int src) { - panic("makeRegisterCopy not implemented"); - return 0; - } - - // Machine operations - - void saveMachineReg(AnyReg &savereg, const RegFile ®_file, - int regnum); - - void restoreMachineReg(RegFile ®s, const AnyReg ®, - int regnum); - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template <class XC> - void zeroRegisters(XC *xc); - #if !FULL_SYSTEM static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) { @@ -244,17 +109,4 @@ extern const int reg_redir[NumIntRegs]; #endif }; -static inline AlphaISA::ExtMachInst -AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) { -#if FULL_SYSTEM - AlphaISA::ExtMachInst ext_inst = inst; - if (pc && 0x1) - return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32); - else - return ext_inst; -#else - return AlphaISA::ExtMachInst(inst); -#endif -} - #endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff --git a/base/loader/ecoff_object.cc b/base/loader/ecoff_object.cc index cd37abaa7..80917ee9c 100644 --- a/base/loader/ecoff_object.cc +++ b/base/loader/ecoff_object.cc @@ -29,6 +29,7 @@ #include <string> #include "base/loader/ecoff_object.hh" +#include "base/misc.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" // for DPRINTF diff --git a/base/loader/elf_object.cc b/base/loader/elf_object.cc index 9a67f1887..2925817cd 100644 --- a/base/loader/elf_object.cc +++ b/base/loader/elf_object.cc @@ -42,6 +42,7 @@ #include "libelf/gelf.h" #include "base/loader/elf_object.hh" +#include "base/misc.hh" #include "base/loader/symtab.hh" diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh index 585aba0f1..32b7f3ef5 100644 --- a/cpu/pc_event.hh +++ b/cpu/pc_event.hh @@ -31,6 +31,8 @@ #include <vector> +#include "base/misc.hh" + class ExecContext; class PCEventQueue; diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 3fa84d499..35f9ab6c0 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -35,6 +35,7 @@ #include <sstream> #include <string> +#include "arch/utility.hh" #include "base/cprintf.hh" #include "base/inifile.hh" #include "base/loader/symtab.hh" diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 2ed2fe61c..764020577 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -33,6 +33,7 @@ #include <string> #include "base/hashmap.hh" +#include "base/misc.hh" #include "base/refcnt.hh" #include "cpu/op_class.hh" #include "sim/host.hh" diff --git a/mem/port.hh b/mem/port.hh index 9d0bd7968..a86c9d727 100644 --- a/mem/port.hh +++ b/mem/port.hh @@ -42,6 +42,7 @@ #include <list> #include <inttypes.h> +#include "base/misc.hh" #include "base/range.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/sim/faults.cc b/sim/faults.cc index 701384989..f7e9a0691 100644 --- a/sim/faults.cc +++ b/sim/faults.cc @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "base/misc.hh" #include "sim/faults.hh" #include "cpu/exec_context.hh" #include "cpu/base.hh" diff --git a/sim/system.hh b/sim/system.hh index 0d5b40e3d..a0ba4f141 100644 --- a/sim/system.hh +++ b/sim/system.hh @@ -32,8 +32,9 @@ #include <string> #include <vector> -#include "base/statistics.hh" #include "base/loader/symtab.hh" +#include "base/misc.hh" +#include "base/statistics.hh" #include "cpu/pc_event.hh" #include "sim/sim_object.hh" #if FULL_SYSTEM |