diff options
| -rw-r--r-- | src/base/remote_gdb.hh | 1 | ||||
| -rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 14 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 10 | ||||
| -rw-r--r-- | src/sim/system.hh | 1 |
5 files changed, 16 insertions, 12 deletions
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh index 90b53e53f..8c3ce7572 100644 --- a/src/base/remote_gdb.hh +++ b/src/base/remote_gdb.hh @@ -33,6 +33,7 @@ #include <map> +#include "arch/types.hh" #include "base/kgdb.h" #include "cpu/pc_event.hh" #include "base/pollevent.hh" diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index c07595024..b7362fad9 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -31,6 +31,7 @@ #include "config/use_checker.hh" #include "arch/alpha/faults.hh" +#include "arch/alpha/isa_traits.hh" #include "base/cprintf.hh" #include "base/statistics.hh" #include "base/timebuf.hh" @@ -189,14 +190,14 @@ AlphaO3CPU<Impl>::regStats() template <class Impl> -MiscReg +TheISA::MiscReg AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) { return this->regFile.readMiscReg(misc_reg, tid); } template <class Impl> -MiscReg +TheISA::MiscReg AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid) { @@ -298,6 +299,7 @@ template <class Impl> void AlphaO3CPU<Impl>::processInterrupts() { + using namespace TheISA; // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 // is the one that handles the interrupts. @@ -409,12 +411,12 @@ AlphaO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) // return value itself in the standard return value reg (v0). if (return_value.successful()) { // no error - this->setArchIntReg(SyscallSuccessReg, 0, tid); - this->setArchIntReg(ReturnValueReg, return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid); + this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid); } else { // got an error, return details - this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid); - this->setArchIntReg(ReturnValueReg, -return_value.value(), tid); + this->setArchIntReg(TheISA::SyscallSuccessReg, (IntReg) -1, tid); + this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid); } } #endif diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 20b89e2a4..990db88ac 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1106,7 +1106,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) assert(offset <= cacheBlkSize - instSize); // Get the instruction from the array of the cache line. - inst = gtoh(*reinterpret_cast<MachInst *> + inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> (&cacheData[tid][offset])); ext_inst = TheISA::makeExtMI(inst, fetch_PC); diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index ae085d200..a4546e669 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -283,7 +283,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) } // Copy the misc regs. - copyMiscRegs(tc, this); + TheISA::copyMiscRegs(tc, this); // Then finally set the PC and the next PC. cpu->setPC(tc->readPC(), tid); @@ -306,7 +306,7 @@ O3ThreadContext<Impl>::readIntReg(int reg_idx) } template <class Impl> -FloatReg +TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) { switch(width) { @@ -321,14 +321,14 @@ O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) } template <class Impl> -FloatReg +TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } template <class Impl> -FloatRegBits +TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); @@ -336,7 +336,7 @@ O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) } template <class Impl> -FloatRegBits +TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); diff --git a/src/sim/system.hh b/src/sim/system.hh index a1b53c2eb..c138d2ee4 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -39,6 +39,7 @@ #include "base/loader/symtab.hh" #include "base/misc.hh" #include "base/statistics.hh" +#include "config/full_system.hh" #include "cpu/pc_event.hh" #include "mem/port.hh" #include "sim/sim_object.hh" |