diff options
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 6 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 11 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 11 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 11 |
4 files changed, 36 insertions, 3 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 1ca0657ad..3582e55ca 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -787,6 +787,12 @@ InOrderCPU::init() { BaseCPU::init(); + if (!params()->defer_registration && + system->getMemoryMode() != Enums::timing) { + fatal("The in-order CPU requires the memory system to be in " + "'timing' mode.\n"); + } + for (ThreadID tid = 0; tid < numThreads; ++tid) { // Set noSquashFromTC so that the CPU doesn't squash when initially // setting up registers. diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 9de1bf6b4..2e972b765 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -647,6 +647,12 @@ FullO3CPU<Impl>::init() { BaseCPU::init(); + if (!params()->defer_registration && + system->getMemoryMode() != Enums::timing) { + fatal("The O3 CPU requires the memory system to be in " + "'timing' mode.\n"); + } + for (ThreadID tid = 0; tid < numThreads; ++tid) { // Set noSquashFromTC so that the CPU doesn't squash when initially // setting up registers. @@ -1174,7 +1180,10 @@ FullO3CPU<Impl>::drainResume() if (_status == SwitchedOut) return; - assert(system->getMemoryMode() == Enums::timing); + if (system->getMemoryMode() != Enums::timing) { + fatal("The O3 CPU requires the memory system to be in " + "'timing' mode.\n"); + } if (!tickEvent.scheduled()) schedule(tickEvent, nextCycle()); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index e63d998a7..fffbb55d6 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -83,6 +83,12 @@ AtomicSimpleCPU::init() { BaseCPU::init(); + if (!params()->defer_registration && + system->getMemoryMode() != Enums::atomic) { + fatal("The atomic CPU requires the memory system to be in " + "'atomic' mode.\n"); + } + // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); @@ -155,7 +161,10 @@ AtomicSimpleCPU::drainResume() return; DPRINTF(SimpleCPU, "Resume\n"); - assert(system->getMemoryMode() == Enums::atomic); + if (system->getMemoryMode() != Enums::atomic) { + fatal("The atomic CPU requires the memory system to be in " + "'atomic' mode.\n"); + } setDrainState(Drainable::Running); if (thread->status() == ThreadContext::Active) { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 41764302d..d3959c895 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -66,6 +66,12 @@ TimingSimpleCPU::init() { BaseCPU::init(); + if (!params()->defer_registration && + system->getMemoryMode() != Enums::timing) { + fatal("The timing CPU requires the memory system to be in " + "'timing' mode.\n"); + } + // Initialise the ThreadContext's memory proxies tcBase()->initMemProxies(tcBase()); @@ -140,7 +146,10 @@ TimingSimpleCPU::drainResume() { DPRINTF(SimpleCPU, "Resume\n"); if (_status != SwitchedOut && _status != Idle) { - assert(system->getMemoryMode() == Enums::timing); + if (system->getMemoryMode() != Enums::timing) { + fatal("The timing CPU requires the memory system to be in " + "'timing' mode.\n"); + } if (fetchEvent.scheduled()) deschedule(fetchEvent); |