summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/minor/MinorCPU.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index 87a30497c..9e285a4d1 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2014 ARM Limited
+# Copyright (c) 2012-2014,2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -150,7 +150,9 @@ class MinorDefaultFloatSimdFU(MinorFU):
'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
- 'SimdFloatMultAcc', 'SimdFloatSqrt'])
+ 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix',
+ 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash',
+ 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3'])
timings = [MinorFUTiming(description='FloatSimd',
srcRegsRelativeLats=[2])]
opLat = 6