diff options
102 files changed, 2703 insertions, 1745 deletions
diff --git a/SConscript b/SConscript index d81baedad..54d02ea4c 100644 --- a/SConscript +++ b/SConscript @@ -307,23 +307,23 @@ syscall_emulation_sources = Split(''' # time. These will have to go away if we want to build a binary that # supports multiple ISAs. -targetarch_files = Split(''' - alpha_linux_process.hh - alpha_memory.hh - alpha_tru64_process.hh - aout_machdep.h - arguments.hh - ecoff_machdep.h - ev5.hh - faults.hh - stacktrace.hh - vtophys.hh - ''') +#targetarch_files = Split(''' +# alpha_linux_process.hh +# alpha_memory.hh +# alpha_tru64_process.hh +# aout_machdep.h +# arguments.hh +# ecoff_machdep.h +# ev5.hh +# faults.hh +# stacktrace.hh +# vtophys.hh +# ''') # Set up bridging headers to the architecture specific versions -for f in targetarch_files: - env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), - '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) +#for f in targetarch_files: +# env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), +# '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) # Add a flag defining what THE_ISA should be for all compilation env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())]) diff --git a/arch/SConscript b/arch/SConscript index d237b0b1f..5783b39dd 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -46,6 +46,16 @@ sources = [] # List of headers to generate isa_switch_hdrs = Split(''' isa_traits.hh + linux_process.hh + tru64_process.hh + tlb.hh + aout_machdep.h + ecoff_machdep.h + arguments.hh + stacktrace.hh + vtophys.hh + faults.hh + ev5.hh ''') # Generate the header. target[0] is the full path of the output @@ -70,7 +80,7 @@ def gen_switch_hdr_string(target, source, env): return "Generating ISA switch header " + str(target[0]) # Build SCons Action object. 'varlist' specifies env vars that this -# action depdnds on; when env['ALL_ISA_LIST'] changes these actions +# action depends on; when env['ALL_ISA_LIST'] changes these actions # should get re-executed. switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string, varlist=['ALL_ISA_LIST']) diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript index 050dfb9cf..3b0e69b7a 100644 --- a/arch/alpha/SConscript +++ b/arch/alpha/SConscript @@ -50,7 +50,7 @@ base_sources = Split(''' # Full-system sources full_system_sources = Split(''' - alpha_memory.cc + tlb.cc arguments.cc ev5.cc osfpal.cc @@ -61,9 +61,9 @@ full_system_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - alpha_common_syscall_emul.cc - alpha_linux_process.cc - alpha_tru64_process.cc + common_syscall_emul.cc + linux_process.cc + tru64_process.cc ''') # Set up complete list of sources based on configuration. diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 14b87b16f..2bb005eb4 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "arch/alpha/isa_traits.hh" #include "arch/alpha/osfpal.hh" #include "base/kgdb.h" @@ -72,32 +72,17 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) void AlphaISA::initCPU(RegFile *regs, int cpuId) { - initIPRs(regs, cpuId); + initIPRs(®s->miscRegs, cpuId); // CPU comes up with PAL regs enabled swap_palshadow(regs, true); regs->intRegFile[16] = cpuId; regs->intRegFile[0] = cpuId; - regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault); + regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect(); regs->npc = regs->pc + sizeof(MachInst); } -//////////////////////////////////////////////////////////////////////// -// -// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE -// -const Addr -AlphaISA::fault_addr(Fault fault) -{ - //Check for the system wide faults - if(fault == NoFault) return 0x0000; - else if(fault == MachineCheckFault) return 0x0401; - else if(fault == AlignmentFault) return 0x0301; - //Deal with the alpha specific faults - return ((AlphaFault*)fault)->vect; -}; - const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, @@ -109,14 +94,13 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { // // void -AlphaISA::initIPRs(RegFile *regs, int cpuId) +AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId) { - uint64_t *ipr = regs->ipr; + miscRegs->clearIprs(); - bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); - ipr[IPR_PAL_BASE] = PalBase; - ipr[IPR_MCSR] = 0x6; - ipr[IPR_PALtemp16] = cpuId; + miscRegs->setReg(IPR_PAL_BASE, PalBase); + miscRegs->setReg(IPR_MCSR, 0x6); + miscRegs->setReg(IPR_PALtemp16, cpuId); } @@ -128,17 +112,16 @@ AlphaISA::processInterrupts(CPU *cpu) //Handle the interrupts int ipl = 0; int summary = 0; - IntReg *ipr = cpu->getIprPtr(); cpu->checkInterrupts = false; - if (ipr[IPR_ASTRR]) + if (cpu->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (ipr[IPR_SIRR]) { + if (cpu->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (ipr[IPR_SIRR] & (ULL(1) << i)) { + if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of the 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -159,12 +142,12 @@ AlphaISA::processInterrupts(CPU *cpu) } } - if (ipl && ipl > ipr[IPR_IPLR]) { - ipr[IPR_ISR] = summary; - ipr[IPR_INTID] = ipl; - cpu->trap(InterruptFault); + if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { + cpu->setMiscReg(IPR_ISR, summary); + cpu->setMiscReg(IPR_INTID, ipl); + cpu->trap(new InterruptFault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - ipr[IPR_IPLR], ipl, summary); + cpu->readMiscReg(IPR_IPLR), ipl, summary); } } @@ -181,33 +164,33 @@ AlphaISA::zeroRegisters(CPU *cpu) } void -ExecContext::ev5_trap(Fault fault) +ExecContext::ev5_temp_trap(Fault fault) { - DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc); - cpu->recordEvent(csprintf("Fault %s", fault->name)); + DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name(), regs.pc); + cpu->recordEvent(csprintf("Fault %s", fault->name())); assert(!misspeculating()); kernelStats->fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); - AlphaISA::InternalProcReg *ipr = regs.ipr; - // exception restart address - if (fault != InterruptFault || !inPalMode()) - ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc; + if (!fault->isA<InterruptFault>() || !inPalMode()) + setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc); - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !inPalMode() */) { - // traps... skip faulting instruction - ipr[AlphaISA::IPR_EXC_ADDR] += 4; + // traps... skip faulting instruction. + setMiscReg(AlphaISA::IPR_EXC_ADDR, + readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } if (!inPalMode()) AlphaISA::swap_palshadow(®s, true); - regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault); + regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + + (dynamic_cast<AlphaFault *>(fault.get()))->vect(); regs.npc = regs.pc + sizeof(MachInst); } @@ -215,26 +198,26 @@ ExecContext::ev5_trap(Fault fault) void AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) { - InternalProcReg *ipr = regs->ipr; bool use_pc = (fault == NoFault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("arithmetic faults NYI..."); // compute exception restart address - if (use_pc || fault == PalFault || fault == ArithmeticFault) { + if (use_pc || fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) { // traps... skip faulting instruction - ipr[IPR_EXC_ADDR] = regs->pc + 4; + regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4); } else { // fault, post fault at excepting instruction - ipr[IPR_EXC_ADDR] = regs->pc; + regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc); } // jump to expection address (PAL PC bit set here as well...) if (!use_pc) - regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault); + regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + + (dynamic_cast<AlphaFault *>(fault.get()))->vect(); else - regs->npc = ipr[IPR_PAL_BASE] + pc; + regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc; // that's it! (orders of magnitude less painful than x86) } @@ -242,17 +225,15 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) Fault ExecContext::hwrei() { - uint64_t *ipr = regs.ipr; - if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; - setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); if (!misspeculating()) { kernelStats->hwrei(); - if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) + if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) AlphaISA::swap_palshadow(®s, false); cpu->checkInterrupts = true; @@ -262,10 +243,15 @@ ExecContext::hwrei() return NoFault; } -uint64_t -ExecContext::readIpr(int idx, Fault &fault) +void +AlphaISA::MiscRegFile::clearIprs() +{ + bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); +} + +AlphaISA::MiscReg +AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) { - uint64_t *ipr = regs.ipr; uint64_t retval = 0; // return value, default 0 switch (idx) { @@ -318,7 +304,7 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= cpu->curCycle() & ULL(0x00000000ffffffff); + retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff); break; case AlphaISA::IPR_VA: @@ -335,7 +321,7 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = dtb->index(!misspeculating()); + AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; @@ -357,12 +343,12 @@ ExecContext::readIpr(int idx, Fault &fault) case AlphaISA::IPR_DTB_IAP: case AlphaISA::IPR_ITB_IA: case AlphaISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; default: // invalid IPR - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; break; } @@ -375,12 +361,11 @@ int break_ipl = -1; #endif Fault -ExecContext::setIpr(int idx, uint64_t val) +AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) { - uint64_t *ipr = regs.ipr; uint64_t old; - if (misspeculating()) + if (xc->misspeculating()) return NoFault; switch (idx) { @@ -433,7 +418,7 @@ ExecContext::setIpr(int idx, uint64_t val) // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; - kernelStats->context(old, val); + xc->kernelStats->context(old, val); break; case AlphaISA::IPR_DTB_PTE: @@ -460,14 +445,14 @@ ExecContext::setIpr(int idx, uint64_t val) // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; - kernelStats->swpipl(ipr[idx]); + xc->kernelStats->swpipl(ipr[idx]); break; case AlphaISA::IPR_DTB_CM: if (val & 0x18) - kernelStats->mode(Kernel::user); + xc->kernelStats->mode(Kernel::user); else - kernelStats->mode(Kernel::kernel); + xc->kernelStats->mode(Kernel::kernel); case AlphaISA::IPR_ICM: // only write two mode bits - processor mode @@ -527,7 +512,7 @@ ExecContext::setIpr(int idx, uint64_t val) case AlphaISA::IPR_ITB_PTE_TEMP: case AlphaISA::IPR_DTB_PTE_TEMP: // read-only registers - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; case AlphaISA::IPR_HWINT_CLR: case AlphaISA::IPR_SL_XMIT: @@ -541,21 +526,21 @@ ExecContext::setIpr(int idx, uint64_t val) // really a control write ipr[idx] = 0; - dtb->flushAll(); + xc->dtb->flushAll(); break; case AlphaISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; - dtb->flushProcesses(); + xc->dtb->flushProcesses(); break; case AlphaISA::IPR_DTB_IS: // really a control write ipr[idx] = val; - dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); break; case AlphaISA::IPR_DTB_TAG: { @@ -578,7 +563,7 @@ ExecContext::setIpr(int idx, uint64_t val) pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB - dtb->insert(val, pte); + xc->dtb->insert(val, pte); } break; @@ -602,7 +587,7 @@ ExecContext::setIpr(int idx, uint64_t val) pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); + xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); } break; @@ -610,26 +595,26 @@ ExecContext::setIpr(int idx, uint64_t val) // really a control write ipr[idx] = 0; - itb->flushAll(); + xc->itb->flushAll(); break; case AlphaISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; - itb->flushProcesses(); + xc->itb->flushProcesses(); break; case AlphaISA::IPR_ITB_IS: // really a control write ipr[idx] = val; - itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); + xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); break; default: // invalid IPR - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } // no error... diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc index fa4950198..78613761d 100644 --- a/arch/alpha/faults.cc +++ b/arch/alpha/faults.cc @@ -27,37 +27,95 @@ */ #include "arch/alpha/faults.hh" +#include "cpu/exec_context.hh" -ResetFaultType * const ResetFault = - new ResetFaultType("reset", 1, 0x0001); -ArithmeticFaultType * const ArithmeticFault = - new ArithmeticFaultType("arith", 3, 0x0501); -InterruptFaultType * const InterruptFault = - new InterruptFaultType("interrupt", 4, 0x0101); -NDtbMissFaultType * const NDtbMissFault = - new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); -PDtbMissFaultType * const PDtbMissFault = - new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); -DtbPageFaultType * const DtbPageFault = - new DtbPageFaultType("dfault", 8, 0x0381); -DtbAcvFaultType * const DtbAcvFault = - new DtbAcvFaultType("dfault", 9, 0x0381); -ItbMissFaultType * const ItbMissFault = - new ItbMissFaultType("itbmiss", 10, 0x0181); -ItbPageFaultType * const ItbPageFault = - new ItbPageFaultType("itbmiss", 11, 0x0181); -ItbAcvFaultType * const ItbAcvFault = - new ItbAcvFaultType("iaccvio", 12, 0x0081); -UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = - new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); -FloatEnableFaultType * const FloatEnableFault = - new FloatEnableFaultType("fen", 14, 0x0581); -PalFaultType * const PalFault = - new PalFaultType("pal", 15, 0x2001); -IntegerOverflowFaultType * const IntegerOverflowFault = - new IntegerOverflowFaultType("intover", 16, 0x0501); - -Fault * ListOfFaults[] = { +namespace AlphaISA +{ + +FaultVect AlphaMachineCheckFault::_vect = 0x0401; +FaultStat AlphaMachineCheckFault::_stat; + +FaultVect AlphaAlignmentFault::_vect = 0x0301; +FaultStat AlphaAlignmentFault::_stat; + +FaultName ResetFault::_name = "reset"; +FaultVect ResetFault::_vect = 0x0001; +FaultStat ResetFault::_stat; + +FaultName ArithmeticFault::_name = "arith"; +FaultVect ArithmeticFault::_vect = 0x0501; +FaultStat ArithmeticFault::_stat; + +FaultName InterruptFault::_name = "interrupt"; +FaultVect InterruptFault::_vect = 0x0101; +FaultStat InterruptFault::_stat; + +FaultName NDtbMissFault::_name = "dtb_miss_single"; +FaultVect NDtbMissFault::_vect = 0x0201; +FaultStat NDtbMissFault::_stat; + +FaultName PDtbMissFault::_name = "dtb_miss_double"; +FaultVect PDtbMissFault::_vect = 0x0281; +FaultStat PDtbMissFault::_stat; + +FaultName DtbPageFault::_name = "dfault"; +FaultVect DtbPageFault::_vect = 0x0381; +FaultStat DtbPageFault::_stat; + +FaultName DtbAcvFault::_name = "dfault"; +FaultVect DtbAcvFault::_vect = 0x0381; +FaultStat DtbAcvFault::_stat; + +FaultName ItbMissFault::_name = "itbmiss"; +FaultVect ItbMissFault::_vect = 0x0181; +FaultStat ItbMissFault::_stat; + +FaultName ItbPageFault::_name = "itbmiss"; +FaultVect ItbPageFault::_vect = 0x0181; +FaultStat ItbPageFault::_stat; + +FaultName ItbAcvFault::_name = "iaccvio"; +FaultVect ItbAcvFault::_vect = 0x0081; +FaultStat ItbAcvFault::_stat; + +FaultName UnimplementedOpcodeFault::_name = "opdec"; +FaultVect UnimplementedOpcodeFault::_vect = 0x0481; +FaultStat UnimplementedOpcodeFault::_stat; + +FaultName FloatEnableFault::_name = "fen"; +FaultVect FloatEnableFault::_vect = 0x0581; +FaultStat FloatEnableFault::_stat; + +FaultName PalFault::_name = "pal"; +FaultVect PalFault::_vect = 0x2001; +FaultStat PalFault::_stat; + +FaultName IntegerOverflowFault::_name = "intover"; +FaultVect IntegerOverflowFault::_vect = 0x0501; +FaultStat IntegerOverflowFault::_stat; + +#if FULL_SYSTEM + +void AlphaFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +void AlphaMachineCheckFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +void AlphaAlignmentFault::ev5_trap(ExecContext * xc) +{ + xc->ev5_temp_trap(this); +} + +#endif + +} // namespace AlphaISA + +/*Fault * ListOfFaults[] = { (Fault *)&NoFault, (Fault *)&ResetFault, (Fault *)&MachineCheckFault, @@ -77,4 +135,4 @@ Fault * ListOfFaults[] = { (Fault *)&IntegerOverflowFault, }; -int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *); +int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/ diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh index 3e25adc4e..156faa8fb 100644 --- a/arch/alpha/faults.hh +++ b/arch/alpha/faults.hh @@ -30,131 +30,231 @@ #define __ALPHA_FAULTS_HH__ #include "sim/faults.hh" -#include "arch/isa_traits.hh" //For the Addr type -class AlphaFault : public FaultBase +// The design of the "name" and "vect" functions is in sim/faults.hh + +namespace AlphaISA +{ + +typedef const Addr FaultVect; + +class AlphaFault : public virtual FaultBase { public: - AlphaFault(char * newName, int newId, Addr newVect) - : FaultBase(newName, newId), vect(newVect) - {;} +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + virtual FaultVect vect() = 0; +}; - Addr vect; +class AlphaMachineCheckFault : + public MachineCheckFault, + public AlphaFault +{ + private: + static FaultVect _vect; + static FaultStat _stat; + public: +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} }; -extern class ResetFaultType : public AlphaFault +class AlphaAlignmentFault : + public AlignmentFault, + public AlphaFault { + private: + static FaultVect _vect; + static FaultStat _stat; public: - ResetFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ResetFault; +#if FULL_SYSTEM + void ev5_trap(ExecContext * xc); +#endif + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ArithmeticFaultType : public AlphaFault +static inline Fault genMachineCheckFault() { + return new AlphaMachineCheckFault; +} + +static inline Fault genAlignmentFault() +{ + return new AlphaAlignmentFault; +} + +class ResetFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ArithmeticFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ArithmeticFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class InterruptFaultType : public AlphaFault +class ArithmeticFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - InterruptFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const InterruptFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class NDtbMissFaultType : public AlphaFault +class InterruptFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - NDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const NDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PDtbMissFaultType : public AlphaFault +class NDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PDtbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PDtbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbPageFaultType : public AlphaFault +class PDtbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class DtbAcvFaultType : public AlphaFault +class DtbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - DtbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const DtbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; + +class DtbAcvFault : public AlphaFault +{ + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; + public: + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbMissFaultType : public AlphaFault +class ItbMissFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbMissFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbMissFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbPageFaultType : public AlphaFault +class ItbPageFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbPageFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbPageFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class ItbAcvFaultType : public AlphaFault +class ItbAcvFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - ItbAcvFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const ItbAcvFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class UnimplementedOpcodeFaultType : public AlphaFault +class UnimplementedOpcodeFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const UnimplementedOpcodeFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class FloatEnableFaultType : public AlphaFault +class FloatEnableFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - FloatEnableFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const FloatEnableFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class PalFaultType : public AlphaFault +class PalFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - PalFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const PalFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern class IntegerOverflowFaultType : public AlphaFault +class IntegerOverflowFault : public AlphaFault { + private: + static FaultName _name; + static FaultVect _vect; + static FaultStat _stat; public: - IntegerOverflowFaultType(char * newName, int newId, Addr newVect) - : AlphaFault(newName, newId, newVect) - {;} -} * const IntegerOverflowFault; + FaultName name() {return _name;} + FaultVect vect() {return _vect;} + FaultStat & stat() {return _stat;} +}; -extern Fault * ListOfFaults[]; -extern int NumFaults; +} // AlphaISA namespace #endif // __FAULTS_HH__ diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index 37b15416b..2fb3fbd2a 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2003-2005 The Regents of The University of Michigan +// Copyright (c) 2003-2006 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); @@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() { // signed overflow occurs when operands have same sign // and sign of result does not match. if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); @@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp; }}); 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); @@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() { // sign bit of the subtrahend (Rb), i.e., if the initial // signs are the *same* then no overflow can occur if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = tmp; }}); 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); @@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = tmp<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc.sl = tmp<31:0>; }}, IntMultOp); 0x60: mulqv({{ @@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() { // the lower 64 if (!((hi == 0 && lo<63:> == 0) || (hi == mask(64) && lo<63:> == 1))) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Rc = lo; }}, IntMultOp); } @@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() { #if SS_COMPATIBLE_FP 0x0b: sqrts({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); #else 0x0b: sqrts({{ if (Fb.sf < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc.sf = sqrt(Fb.sf); }}, FloatSqrtOp); #endif 0x2b: sqrtt({{ if (Fb < 0.0) - fault = ArithmeticFault; + fault = new ArithmeticFault; Fc = sqrt(Fb); }}, FloatSqrtOp); } @@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() { // checking the upper 33 bits for all 0s or all 1s. uint64_t sign_bits = Fb.uq<63:31>; if (sign_bits != 0 && sign_bits != mask(33)) - fault = IntegerOverflowFault; + fault = new IntegerOverflowFault; Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); }}); @@ -618,7 +618,7 @@ decode OPCODE default Unknown::unknown() { /* Rb is a fake dependency so here is a fun way to get * the parser to understand that. */ - Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0); + Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); #else Ra = curTick; @@ -670,10 +670,10 @@ decode OPCODE default Unknown::unknown() { 0x00: CallPal::call_pal({{ if (!palValid || (palPriv - && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { + && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { // check to see if simulator wants to do something special @@ -682,8 +682,8 @@ decode OPCODE default Unknown::unknown() { if (dopal) { AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); - xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); - NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset; + xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); + NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; } } }}, IsNonSpeculative); @@ -729,19 +729,19 @@ decode OPCODE default Unknown::unknown() { 0x19: hw_mfpr({{ // this instruction is only valid in PAL mode if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { - Ra = xc->readIpr(ipr_index, fault); + Ra = xc->readMiscRegWithEffect(ipr_index, fault); } }}); 0x1d: hw_mtpr({{ // this instruction is only valid in PAL mode if (!xc->inPalMode()) { - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; } else { - xc->setIpr(ipr_index, Ra); + xc->setMiscRegWithEffect(ipr_index, Ra); if (traceData) { traceData->setData(Ra); } } }}); @@ -758,6 +758,15 @@ decode OPCODE default Unknown::unknown() { 0x01: quiesce({{ AlphaPseudo::quiesce(xc->xcBase()); }}, IsNonSpeculative); + 0x02: quiesceNs({{ + AlphaPseudo::quiesceNs(xc->xcBase(), R16); + }}, IsNonSpeculative); + 0x03: quiesceCycles({{ + AlphaPseudo::quiesceCycles(xc->xcBase(), R16); + }}, IsNonSpeculative); + 0x04: quiesceTime({{ + R0 = AlphaPseudo::quiesceTime(xc->xcBase()); + }}, IsNonSpeculative); 0x10: ivlb({{ AlphaPseudo::ivlb(xc->xcBase()); }}, No_OpClass, IsNonSpeculative); @@ -795,6 +804,9 @@ decode OPCODE default Unknown::unknown() { 0x53: m5addsymbol({{ AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); }}, IsNonSpeculative); + 0x54: m5panic({{ + panic("M5 panic instruction called."); + }}, IsNonSpeculative); } } diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa index 7e81fb830..13656359f 100644 --- a/arch/alpha/isa/fp.isa +++ b/arch/alpha/isa/fp.isa @@ -35,8 +35,8 @@ output exec {{ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) { Fault fault = NoFault; // dummy... this ipr access should not fault - if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) { - fault = FloatEnableFault; + if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) { + fault = new FloatEnableFault; } return fault; } @@ -217,7 +217,8 @@ def template FloatingPointExecute {{ if (roundingMode == Normal) { %(code)s; } else { - fesetround(getC99RoundingMode(xc->readFpcr())); + fesetround(getC99RoundingMode( + xc->readMiscReg(AlphaISA::Fpcr_DepTag))); %(code)s; fesetround(FE_TONEAREST); } diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa index b8d03c0be..ad9c2a55e 100644 --- a/arch/alpha/isa/main.isa +++ b/arch/alpha/isa/main.isa @@ -161,8 +161,8 @@ def operands {{ 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), - 'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), - 'FPCR': (' ControlReg', 'uq', 'Fpcr', None, 1), + 'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1), + 'FPCR': (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1), # The next two are hacks for non-full-system call-pal emulation 'R0': ('IntReg', 'uq', '0', None, 1), 'R16': ('IntReg', 'uq', '16', None, 1), @@ -194,6 +194,8 @@ output header {{ FP_Base_DepTag = AlphaISA::FP_Base_DepTag, Fpcr_DepTag = AlphaISA::Fpcr_DepTag, Uniq_DepTag = AlphaISA::Uniq_DepTag, + Lock_Flag_DepTag = AlphaISA::Lock_Flag_DepTag, + Lock_Addr_DepTag = AlphaISA::Lock_Addr_DepTag, IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag }; diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa index de4ac3eaf..09df39706 100644 --- a/arch/alpha/isa/unimp.isa +++ b/arch/alpha/isa/unimp.isa @@ -111,7 +111,7 @@ output exec {{ { panic("attempt to execute unimplemented instruction '%s' " "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } Fault diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa index 4601b3684..47d166255 100644 --- a/arch/alpha/isa/unknown.isa +++ b/arch/alpha/isa/unknown.isa @@ -42,7 +42,7 @@ output exec {{ { panic("attempt to execute unknown instruction " "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; } }}; diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index f47e90f86..938ba696e 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -38,6 +38,7 @@ using namespace LittleEndianGuest; #include "sim/host.hh" #include "sim/faults.hh" +class ExecContext; class FastCPU; class FullCPU; class Checkpoint; @@ -64,6 +65,7 @@ namespace AlphaISA NumIntRegs = 32, NumFloatRegs = 32, + // @todo: Figure out what this number really should be. NumMiscRegs = 32, MaxRegsOfAnyType = 32, @@ -106,7 +108,9 @@ namespace AlphaISA Ctrl_Base_DepTag = 64, Fpcr_DepTag = 64, // floating point control register Uniq_DepTag = 65, - IPR_Base_DepTag = 66 + Lock_Flag_DepTag = 66, + Lock_Addr_DepTag = 67, + IPR_Base_DepTag = 68 }; typedef uint64_t IntReg; @@ -123,15 +127,6 @@ namespace AlphaISA double d[NumFloatRegs]; // double-precision floating point view } FloatRegFile; - // control register file contents - typedef uint64_t MiscReg; - typedef struct { - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - } MiscRegFile; - extern const Addr PageShift; extern const Addr PageBytes; extern const Addr PageMask; @@ -149,6 +144,39 @@ extern const Addr PageOffset; }; #endif + // control register file contents + typedef uint64_t MiscReg; + class MiscRegFile { + protected: + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + + public: + MiscReg readReg(int misc_reg); + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); + + Fault setReg(int misc_reg, const MiscReg &val); + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc); + +#if FULL_SYSTEM + void clearIprs(); + + protected: + InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs + + private: + MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); + + Fault setIpr(int idx, uint64_t val, ExecContext *xc); +#endif + friend class RegFile; + }; + enum { TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs @@ -172,11 +200,12 @@ extern const Addr PageOffset; Addr npc; // next-cycle program counter #if FULL_SYSTEM IntReg palregs[NumIntRegs]; // PAL shadow registers - InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers - inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } - inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } + inline int instAsid() + { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); } + inline int dataAsid() + { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); } #endif // FULL_SYSTEM void serialize(std::ostream &os); diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc index 16ebcca7b..0b193fb55 100644 --- a/arch/alpha/alpha_linux_process.cc +++ b/arch/alpha/linux_process.cc @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_linux_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/linux_process.hh" #include "arch/alpha/isa_traits.hh" #include "base/trace.hh" diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh index 7de1b1ac1..7de1b1ac1 100644 --- a/arch/alpha/alpha_linux_process.hh +++ b/arch/alpha/linux_process.hh diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc index 30ed07d9d..89b6b73a9 100644 --- a/arch/alpha/stacktrace.cc +++ b/arch/alpha/stacktrace.cc @@ -124,7 +124,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call) { xc = _xc; - bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0; + bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; Addr pc = xc->regs.npc; bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd; @@ -196,22 +196,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call) bool StackTrace::isEntry(Addr addr) { - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp12]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12)) return true; - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp7]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7)) return true; - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp11]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11)) return true; - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp21]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21)) return true; - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp9]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9)) return true; - if (addr == xc->regs.ipr[AlphaISA::IPR_PALtemp2]) + if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2)) return true; return false; diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/tlb.cc index d00186d95..0f2cedc83 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/tlb.cc @@ -30,7 +30,7 @@ #include <string> #include <vector> -#include "arch/alpha/alpha_memory.hh" +#include "arch/alpha/tlb.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -293,12 +293,11 @@ AlphaITB::regStats() void AlphaITB::fault(Addr pc, ExecContext *xc) const { - uint64_t *ipr = xc->regs.ipr; - if (!xc->misspeculating()) { - ipr[AlphaISA::IPR_ITB_TAG] = pc; - ipr[AlphaISA::IPR_IFAULT_VA_FORM] = - ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3); + xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); + xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, + xc->readMiscReg(AlphaISA::IPR_IVPTBR) | + (AlphaISA::VAddr(pc).vpn() << 3)); } } @@ -306,7 +305,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const Fault AlphaITB::translate(MemReqPtr &req) const { - InternalProcReg *ipr = req->xc->regs.ipr; + ExecContext *xc = req->xc; if (AlphaISA::PcPAL(req->vaddr)) { // strip off PAL PC marker (lsb is 1) @@ -322,24 +321,24 @@ AlphaITB::translate(MemReqPtr &req) const if (!validVirtualAddress(req->vaddr)) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && + if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->vaddr) == 2) { #else if (VAddrSpaceEV6(req->vaddr) == 0x7e) { #endif // only valid in kernel mode - if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != + if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) != AlphaISA::mode_kernel) { fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -354,24 +353,26 @@ AlphaITB::translate(MemReqPtr &req) const } else { // not a physical address: need to look up pte + int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + asn); if (!pte) { fault(req->vaddr, req->xc); misses++; - return ItbPageFault; + return new ItbPageFault; } req->paddr = (pte->ppn << AlphaISA::PageShift) + (AlphaISA::VAddr(req->vaddr).offset() & ~3); // check permissions for this access - if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { + if (!(pte->xre & + (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) { // instruction access fault fault(req->vaddr, req->xc); acv++; - return ItbAcvFault; + return new ItbAcvFault; } hits++; @@ -380,7 +381,7 @@ AlphaITB::translate(MemReqPtr &req) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); @@ -469,7 +470,6 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const { ExecContext *xc = req->xc; AlphaISA::VAddr vaddr = req->vaddr; - uint64_t *ipr = xc->regs.ipr; // Set fault address and flags. Even though we're modeling an // EV5, we use the EV6 technique of not latching fault registers @@ -479,17 +479,17 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const if (!xc->misspeculating() && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { // set VA register with faulting address - ipr[AlphaISA::IPR_VA] = req->vaddr; + xc->setMiscReg(AlphaISA::IPR_VA, req->vaddr); // set MM_STAT register flags - ipr[AlphaISA::IPR_MM_STAT] = + xc->setMiscReg(AlphaISA::IPR_MM_STAT, (((Opcode(xc->getInst()) & 0x3f) << 11) | ((Ra(xc->getInst()) & 0x1f) << 6) - | (flags & 0x3f)); + | (flags & 0x3f))); // set VA_FORM register with faulting formatted address - ipr[AlphaISA::IPR_VA_FORM] = - ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3); + xc->setMiscReg(AlphaISA::IPR_VA_FORM, + xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); } } @@ -497,11 +497,11 @@ Fault AlphaDTB::translate(MemReqPtr &req, bool write) const { RegFile *regs = &req->xc->regs; + ExecContext *xc = req->xc; Addr pc = regs->pc; - InternalProcReg *ipr = regs->ipr; AlphaISA::mode_type mode = - (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); + (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)); /** @@ -511,12 +511,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const fault(req, write ? MM_STAT_WR_MASK : 0); DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, req->size); - return AlignmentFault; + return genAlignmentFault(); } if (pc & 0x1) { mode = (req->flags & ALTMODE) ? - (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) + (AlphaISA::mode_type)ALT_MODE_AM( + xc->readMiscReg(AlphaISA::IPR_ALT_MODE)) : AlphaISA::mode_kernel; } @@ -530,24 +531,24 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK); if (write) { write_acv++; } else { read_acv++; } - return DtbPageFault; + return new DtbPageFault; } // Check for "superpage" mapping #if ALPHA_TLASER - if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && + if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->vaddr) == 2) { #else if (VAddrSpaceEV6(req->vaddr) == 0x7e) { #endif // only valid in kernel mode - if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != + if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) != AlphaISA::mode_kernel) { fault(req, ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK)); if (write) { write_acv++; } else { read_acv++; } - return DtbAcvFault; + return new DtbAcvFault; } req->paddr = req->vaddr & PAddrImplMask; @@ -566,16 +567,20 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const else read_accesses++; + int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); + // not a physical address: need to look up pte AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), - DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); + asn); if (!pte) { // page fault fault(req, (write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK); if (write) { write_misses++; } else { read_misses++; } - return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault; + return (req->flags & VPTE) ? + (Fault)(new PDtbMissFault) : + (Fault)(new NDtbMissFault); } req->paddr = (pte->ppn << AlphaISA::PageShift) + @@ -588,25 +593,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const MM_STAT_ACV_MASK | (pte->fonw ? MM_STAT_FONW_MASK : 0)); write_acv++; - return DtbPageFault; + return new DtbPageFault; } if (pte->fonw) { fault(req, MM_STAT_WR_MASK | MM_STAT_FONW_MASK); write_acv++; - return DtbPageFault; + return new DtbPageFault; } } else { if (!(pte->xre & MODE2MASK(mode))) { fault(req, MM_STAT_ACV_MASK | (pte->fonr ? MM_STAT_FONR_MASK : 0)); read_acv++; - return DtbAcvFault; + return new DtbAcvFault; } if (pte->fonr) { fault(req, MM_STAT_FONR_MASK); read_acv++; - return DtbPageFault; + return new DtbPageFault; } } } @@ -619,7 +624,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const // check that the physical address is ok (catch bad physical addresses) if (req->paddr & ~PAddrImplMask) - return MachineCheckFault; + return genMachineCheckFault(); checkCacheability(req); diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/tlb.hh index de955fa46..de955fa46 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/tlb.hh diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc index 8121d3452..90e8b1139 100644 --- a/arch/alpha/alpha_tru64_process.cc +++ b/arch/alpha/tru64_process.cc @@ -27,8 +27,8 @@ */ #include "arch/alpha/isa_traits.hh" -#include "arch/alpha/alpha_common_syscall_emul.hh" -#include "arch/alpha/alpha_tru64_process.hh" +#include "arch/alpha/common_syscall_emul.hh" +#include "arch/alpha/tru64_process.hh" #include "cpu/exec_context.hh" #include "kern/tru64/tru64.hh" #include "mem/functional/functional.hh" diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh index 051760702..051760702 100644 --- a/arch/alpha/alpha_tru64_process.hh +++ b/arch/alpha/tru64_process.hh diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc index 3ffa4bd14..1d70196c5 100644 --- a/arch/alpha/vtophys.cc +++ b/arch/alpha/vtophys.cc @@ -82,7 +82,7 @@ Addr vtophys(ExecContext *xc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20]; + Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 6508ca02a..5185ed573 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -1263,10 +1263,10 @@ class ControlRegOperand(Operand): def makeConstructor(self): c = '' if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s_DepTag;' % \ + c += '\n\t_srcRegIdx[%d] = %s;' % \ (self.src_reg_idx, self.reg_spec) if self.is_dest: - c += '\n\t_destRegIdx[%d] = %s_DepTag;' % \ + c += '\n\t_destRegIdx[%d] = %s;' % \ (self.dest_reg_idx, self.reg_spec) return c @@ -1274,7 +1274,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->read%s()' % self.reg_spec + base = 'xc->readMiscReg(%s)' % self.reg_spec if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: @@ -1284,7 +1284,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->set%s(%s);\n' % (self.reg_spec, self.base_name) + wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name return wb diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc new file mode 100644 index 000000000..e05b3fe59 --- /dev/null +++ b/arch/mips/faults.cc @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/alpha/faults.hh" + +ResetFaultType * const ResetFault = + new ResetFaultType("reset", 1, 0x0001); +ArithmeticFaultType * const ArithmeticFault = + new ArithmeticFaultType("arith", 3, 0x0501); +InterruptFaultType * const InterruptFault = + new InterruptFaultType("interrupt", 4, 0x0101); +NDtbMissFaultType * const NDtbMissFault = + new NDtbMissFaultType("dtb_miss_single", 5, 0x0201); +PDtbMissFaultType * const PDtbMissFault = + new PDtbMissFaultType("dtb_miss_double", 6, 0x0281); +DtbPageFaultType * const DtbPageFault = + new DtbPageFaultType("dfault", 8, 0x0381); +DtbAcvFaultType * const DtbAcvFault = + new DtbAcvFaultType("dfault", 9, 0x0381); +ItbMissFaultType * const ItbMissFault = + new ItbMissFaultType("itbmiss", 10, 0x0181); +ItbPageFaultType * const ItbPageFault = + new ItbPageFaultType("itbmiss", 11, 0x0181); +ItbAcvFaultType * const ItbAcvFault = + new ItbAcvFaultType("iaccvio", 12, 0x0081); +UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault = + new UnimplementedOpcodeFaultType("opdec", 13, 0x0481); +FloatEnableFaultType * const FloatEnableFault = + new FloatEnableFaultType("fen", 14, 0x0581); +PalFaultType * const PalFault = + new PalFaultType("pal", 15, 0x2001); +IntegerOverflowFaultType * const IntegerOverflowFault = + new IntegerOverflowFaultType("intover", 16, 0x0501); + +Fault ** ListOfFaults[] = { + (Fault **)&NoFault, + (Fault **)&ResetFault, + (Fault **)&MachineCheckFault, + (Fault **)&ArithmeticFault, + (Fault **)&InterruptFault, + (Fault **)&NDtbMissFault, + (Fault **)&PDtbMissFault, + (Fault **)&AlignmentFault, + (Fault **)&DtbPageFault, + (Fault **)&DtbAcvFault, + (Fault **)&ItbMissFault, + (Fault **)&ItbPageFault, + (Fault **)&ItbAcvFault, + (Fault **)&UnimplementedOpcodeFault, + (Fault **)&FloatEnableFault, + (Fault **)&PalFault, + (Fault **)&IntegerOverflowFault, + }; + +int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **); diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh new file mode 100644 index 000000000..60c9e735c --- /dev/null +++ b/arch/mips/faults.hh @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ALPHA_FAULTS_HH__ +#define __ALPHA_FAULTS_HH__ + +#include "sim/faults.hh" +#include "arch/isa_traits.hh" //For the Addr type + +class AlphaFault : public Fault +{ + public: + AlphaFault(char * newName, int newId, Addr newVect) + : Fault(newName, newId), vect(newVect) + {;} + + Addr vect; +}; + +extern class ResetFaultType : public AlphaFault +{ + public: + ResetFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ResetFault; + +extern class ArithmeticFaultType : public AlphaFault +{ + public: + ArithmeticFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ArithmeticFault; + +extern class InterruptFaultType : public AlphaFault +{ + public: + InterruptFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const InterruptFault; + +extern class NDtbMissFaultType : public AlphaFault +{ + public: + NDtbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const NDtbMissFault; + +extern class PDtbMissFaultType : public AlphaFault +{ + public: + PDtbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const PDtbMissFault; + +extern class DtbPageFaultType : public AlphaFault +{ + public: + DtbPageFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const DtbPageFault; + +extern class DtbAcvFaultType : public AlphaFault +{ + public: + DtbAcvFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const DtbAcvFault; + +extern class ItbMissFaultType : public AlphaFault +{ + public: + ItbMissFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbMissFault; + +extern class ItbPageFaultType : public AlphaFault +{ + public: + ItbPageFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbPageFault; + +extern class ItbAcvFaultType : public AlphaFault +{ + public: + ItbAcvFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const ItbAcvFault; + +extern class UnimplementedOpcodeFaultType : public AlphaFault +{ + public: + UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const UnimplementedOpcodeFault; + +extern class FloatEnableFaultType : public AlphaFault +{ + public: + FloatEnableFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const FloatEnableFault; + +extern class PalFaultType : public AlphaFault +{ + public: + PalFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const PalFault; + +extern class IntegerOverflowFaultType : public AlphaFault +{ + public: + IntegerOverflowFaultType(char * newName, int newId, Addr newVect) + : AlphaFault(newName, newId, newVect) + {;} +} * const IntegerOverflowFault; + +extern Fault ** ListOfFaults[]; +extern int NumFaults; + +#endif // __FAULTS_HH__ diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa index 846d161b9..7600632d3 100644 --- a/arch/mips/isa/base.isa +++ b/arch/mips/isa/base.isa @@ -7,57 +7,83 @@ //Outputs to decoder.hh output header {{ - /** - * Base class for all MIPS static instructions. - */ - class MipsStaticInst : public StaticInst<MIPSISA> - { - protected: +#define R31 31 - // Constructor. - MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) - : StaticInst<MIPSISA>(mnem, _machInst, __opClass) - { - } + /** + * Base class for all MIPS static instructions. + */ + class MipsStaticInst : public StaticInst + { + protected: - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + /// Make MipsISA register dependence tags directly visible in + /// this class and derived classes. Maybe these should really + /// live here and not in the MipsISA namespace. + enum DependenceTags { + FP_Base_DepTag = MipsISA::FP_Base_DepTag, + Fpcr_DepTag = MipsISA::Fpcr_DepTag, + Uniq_DepTag = MipsISA::Uniq_DepTag, + IPR_Base_DepTag = MipsISA::IPR_Base_DepTag }; + // Constructor + MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) + : StaticInst(mnem, _machInst, __opClass) + { + } + + /// Print a register name for disassembly given the unique + /// dependence tag number (FP or int). + void printReg(std::ostream &os, int reg) const; + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + }}; //Ouputs to decoder.cc output decoder {{ - std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + void MipsStaticInst::printReg(std::ostream &os, int reg) const + { + if (reg < FP_Base_DepTag) { + ccprintf(os, "r%d", reg); + } + else { + ccprintf(os, "f%d", reg - FP_Base_DepTag); + } + } + + std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // just print the first two source regs... if there's + // a third one, it's a read-modify-write dest (Rc), + // e.g. for CMOVxx + if(_numSrcRegs > 0) + { + printReg(ss, _srcRegIdx[0]); + } + if(_numSrcRegs > 1) { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if(_numSrcRegs > 0) - { - printReg(ss, _srcRegIdx[0]); - } - if(_numSrcRegs > 1) - { - ss << ","; - printReg(ss, _srcRegIdx[1]); - } - - // just print the first dest... if there's a second one, - // it's generally implicit - if(_numDestRegs > 0) - { - if(_numSrcRegs > 0) - ss << ","; - printReg(ss, _destRegIdx[0]); - } - - return ss.str(); + ss << ","; + printReg(ss, _srcRegIdx[1]); } + // just print the first dest... if there's a second one, + // it's generally implicit + if(_numDestRegs > 0) + { + if(_numSrcRegs > 0) + ss << ","; + printReg(ss, _destRegIdx[0]); + } + + return ss.str(); + } + }}; diff --git a/arch/mips/isa/bitfields.isa b/arch/mips/isa/bitfields.isa index 532b3793a..3a01b64ee 100644 --- a/arch/mips/isa/bitfields.isa +++ b/arch/mips/isa/bitfields.isa @@ -5,9 +5,15 @@ // Bitfield definitions. // +def bitfield OPCODE <31:26>; def bitfield OPCODE_HI <31:29>; def bitfield OPCODE_LO <28:26>; +def bitfield REGIMM <20:16>; +def bitfield REGIMM_HI <20:19>; +def bitfield REGIMM_LO <18:16>; + +def bitfield FUNCTION < 5: 0>; def bitfield FUNCTION_HI < 5: 3>; def bitfield FUNCTION_LO < 2: 0>; @@ -31,6 +37,8 @@ def bitfield FT <20:16>; def bitfield FS <15:11>; def bitfield FD <10:6>; +def bitfield ND <17:17>; +def bitfield TF <16:16>; def bitfield MOVCI <16:16>; def bitfield MOVCF <16:16>; def bitfield SRL <21:21>; @@ -45,7 +53,7 @@ def bitfield OFFSET <15: 0>; // displacement // Jmp format def bitfield JMPTARG <25: 0>; -def bitfield JMPHINT <10: 6>; +def bitfield HINT <10: 6>; def bitfield SYSCALLCODE <25: 6>; def bitfield TRAPCODE <15:13>; diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa index 7dd08ac49..f16da7f87 100644 --- a/arch/mips/isa/decoder.isa +++ b/arch/mips/isa/decoder.isa @@ -96,13 +96,13 @@ decode OPCODE_HI default Unknown::unknown() { 0x3: decode FUNCTION_LO { format IntOp { 0x0: mult({{ - INT64 temp1 = Rs.sw * Rt.sw; + int64_t temp1 = Rs.sw * Rt.sw; xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0>; }}); 0x1: multu({{ - INT64 temp1 = Rs.uw * Rt.uw; + int64_t temp1 = Rs.uw * Rt.uw; xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> Rd.sw = Rs.uw * Rt.uw; @@ -141,7 +141,7 @@ decode OPCODE_HI default Unknown::unknown() { } 0x6: decode FUNCTION_LO { - format Trap { + format BasicOp { 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); @@ -167,7 +167,7 @@ decode OPCODE_HI default Unknown::unknown() { } 0x1: decode REGIMM_LO { - format Trap { + format BasicOp { 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); @@ -179,14 +179,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: decode REGIMM_LO { format Branch { - 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); - 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); + 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); + 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); } format BranchLikely { //Will be removed in future MIPS releases - 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); - 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); + 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); + 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); } } @@ -336,7 +336,7 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 0x1: decode FUNCTION { - format Trap { + format BasicOp { 0x01: tlbr({{ }}); 0x02: tlbwi({{ }}); 0x06: tlbwr({{ }}); @@ -433,8 +433,8 @@ decode OPCODE_HI default Unknown::unknown() { } format Float64Op { - 0x2: recips({{ Fd = 1 / Fs; }}); - 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); + 0x5: recips({{ Fd = 1 / Fs; }}); + 0x6: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); } } @@ -502,8 +502,8 @@ decode OPCODE_HI default Unknown::unknown() { } format BasicOp { - 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); - 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); + 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); + 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); } format Float64Op { @@ -538,12 +538,12 @@ decode OPCODE_HI default Unknown::unknown() { //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 0x4: decode FUNCTION { format FloatOp { - 0x10: cvt_s({{ + 0x20: cvt_s({{ int rnd_mode = xc->miscRegs.fcsr; Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); }}); - 0x10: cvt_d({{ + 0x21: cvt_d({{ int rnd_mode = xc->miscRegs.fcsr; Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); }}); @@ -613,6 +613,11 @@ decode OPCODE_HI default Unknown::unknown() { } } + format BasicOp { + 0x2: movzps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }}); + 0x3: movnps({{ if ( FPConditionCode(CC) == 0) Fd = Fs; }}); + } + } 0x4: decode RS_LO { @@ -763,14 +768,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: decode FUNCTION_LO { format IntOp { 0x0: madd({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 + (Rs.sw * Rt.sw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> }}); 0x1: maddu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 + (Rs.uw * Rt.uw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> @@ -779,14 +784,14 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 0x4: msub({{ - INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; + int64_t temp1 = Hi.sw << 32 | Lo.sw >> 32; temp1 = temp1 - (Rs.sw * Rt.sw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> }}); 0x5: msubu({{ - INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; + int64_t temp1 = Hi.uw << 32 | Lo.uw >> 32; temp1 = temp1 - (Rs.uw * Rt.uw); xc->miscRegs.hi->temp1<63:32>; xc->miscRegs.lo->temp1<31:0> diff --git a/arch/mips/isa/formats.isa b/arch/mips/isa/formats.isa index c244013df..a6aec9437 100644 --- a/arch/mips/isa/formats.isa +++ b/arch/mips/isa/formats.isa @@ -10,7 +10,7 @@ //Include utility formats/functions ##include "m5/arch/mips/isa/formats/util.isa" -//Include the integerOp and integerOpCc format +//Include the integer formats ##include "m5/arch/mips/isa/formats/int.isa" //Include the floatOp format @@ -30,4 +30,3 @@ //Include the noop format ##include "m5/arch/mips/isa/formats/unknown.isa" - diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index fc207fd3f..c896e9b2d 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -70,7 +70,7 @@ output header {{ int32_t disp; /// Constructor. - Branch(const char *mnem, MachInst _machInst, OpClass __opClass) + BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass) : PCDependentDisassembly(mnem, _machInst, __opClass), disp(OFFSET << 2) { @@ -243,7 +243,7 @@ output decoder {{ ss << ","; } - ccprintf(ss, "(r%d)", RB); + ccprintf(ss, "(r%d)", RT); return ss.str(); } diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa index 23fcbaa67..7dd1e8442 100644 --- a/arch/mips/isa/formats/fp.isa +++ b/arch/mips/isa/formats/fp.isa @@ -1,3 +1,5 @@ +// -*- mode:c++ -*- + //////////////////////////////////////////////////////////////////// // // Floating Point operate instructions @@ -5,7 +7,7 @@ output header {{ /** - * Base class for integer operations. + * Base class for FP operations. */ class FPOp : public MipsStaticInst { @@ -70,62 +72,19 @@ def template FloatingPointExecute {{ }}; // Primary format for integer operate instructions: -def format FloatOp(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) +def format FloatOp(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = FloatingPointExecute.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; // Primary format for integer operate instructions: -def format Float64Op(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', '0'), ('icValue', '0'), - ('xvValue', '0'), ('xcValue', '0')): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = FloatingPointExecute.subst(iop) -}}; - -// Primary format for integer operate instructions: -def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ - orig_code = code - - cblk = CodeBlock(code) - checkPriv = (code.find('checkPriv') != -1) - code.replace('checkPriv', '') - if checkPriv: - code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') - else: - code.replace('checkPriv;', '') - for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), - ('xvValue', xvValue), ('xcValue', xcValue)): - code.replace(marker, value) - iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) +def format Float64Op(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecodeWithMnemonic.subst(iop) - exec_output = IntegerExecute.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) }}; diff --git a/arch/mips/isa/formats/mem.isa b/arch/mips/isa/formats/mem.isa index 134548746..fcdb577c6 100644 --- a/arch/mips/isa/formats/mem.isa +++ b/arch/mips/isa/formats/mem.isa @@ -70,7 +70,7 @@ output decoder {{ Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const { return csprintf("%-10s %c%d,%d(r%d)", mnemonic, - flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); + flags[IsFloating] ? 'f' : 'r', RS, JMPTARG, RT); } }}; diff --git a/arch/mips/isa/formats/noop.isa b/arch/mips/isa/formats/noop.isa index d366461e2..05c5ac10f 100644 --- a/arch/mips/isa/formats/noop.isa +++ b/arch/mips/isa/formats/noop.isa @@ -63,12 +63,12 @@ output exec {{ } }}; -// integer & FP operate instructions use Rc as dest, so check for -// Rc == 31 to detect nops +// integer & FP operate instructions use RT as dest, so check for +// RT == 0 to detect nops def template OperateNopCheckDecode {{ { MipsStaticInst *i = new %(class_name)s(machInst); - if (RC == 31) { + if (RD == 0) { i = makeNop(i); } return i; diff --git a/arch/mips/isa/formats/util.isa b/arch/mips/isa/formats/util.isa index f0671726c..c06877b35 100644 --- a/arch/mips/isa/formats/util.isa +++ b/arch/mips/isa/formats/util.isa @@ -122,4 +122,4 @@ output exec {{ { //CODE HERE } -} +}}; diff --git a/arch/mips/isa/includes.isa b/arch/mips/isa/includes.isa index ff7cb7d1d..da919be00 100644 --- a/arch/mips/isa/includes.isa +++ b/arch/mips/isa/includes.isa @@ -9,7 +9,6 @@ output header {{ #include <iomanip> #include "cpu/static_inst.hh" -#include "traps.hh" #include "mem/mem_req.hh" // some constructors use MemReq flags }}; diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc index 90a85feb6..02a857af7 100644 --- a/arch/mips/isa_traits.cc +++ b/arch/mips/isa_traits.cc @@ -27,32 +27,121 @@ */ #include "arch/mips/isa_traits.hh" +#include "config/full_system.hh" #include "cpu/static_inst.hh" #include "sim/serialize.hh" -// Alpha UNOP (ldq_u r31,0(r0)) -// @todo: fix to MIPS specific +using namespace MipsISA; + +const Addr MipsISA::PageShift = 13; +const Addr MipsISA::PageBytes = ULL(1) << PageShift; +const Addr MipsISA::PageMask = ~(PageBytes - 1); +const Addr MipsISA::PageOffset = PageBytes - 1; + +#if FULL_SYSTEM + +//////////////////////////////////////////////////////////////////////// +// +// Translation stuff +// + +const Addr MipsISA::PteShift = 3; +const Addr MipsISA::NPtePageShift = PageShift - PteShift; +const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift; +const Addr MipsISA::PteMask = NPtePage - 1; + +// User Virtual +const Addr MipsISA::USegBase = ULL(0x0); +const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff); + +// Kernel Direct Mapped +const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000); +const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff); + +// Kernel Virtual +const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000); +const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff); + +#endif + +// Mips UNOP (ldq_u r31,0(r0)) const MachInst MipsISA::NoopMachInst = 0x2ffe0000; +static inline Addr +TruncPage(Addr addr) +{ return addr & ~(MipsISA::PageBytes - 1); } + +static inline Addr +RoundPage(Addr addr) +{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); } void -MipsISA::RegFile::serialize(std::ostream &os) +RegFile::serialize(std::ostream &os) { - intRegFile.serialize(os); - floatRegFile.serialize(os); - miscRegs.serialize(os); + SERIALIZE_ARRAY(intRegFile, NumIntRegs); + SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + SERIALIZE_SCALAR(miscRegs.fpcr); + SERIALIZE_SCALAR(miscRegs.uniq); + SERIALIZE_SCALAR(miscRegs.lock_flag); + SERIALIZE_SCALAR(miscRegs.lock_addr); SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + SERIALIZE_ARRAY(palregs, NumIntRegs); + SERIALIZE_ARRAY(ipr, NumInternalProcRegs); + SERIALIZE_SCALAR(intrflag); + SERIALIZE_SCALAR(pal_shadow); +#endif } void -MipsISA::RegFile::unserialize(Checkpoint *cp, const std::string §ion) +RegFile::unserialize(Checkpoint *cp, const std::string §ion) { - intRegFile.unserialize(cp, section); - floatRegFile.unserialize(cp, section); - miscRegs.unserialize(cp, section); + UNSERIALIZE_ARRAY(intRegFile, NumIntRegs); + UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs); + UNSERIALIZE_SCALAR(miscRegs.fpcr); + UNSERIALIZE_SCALAR(miscRegs.uniq); + UNSERIALIZE_SCALAR(miscRegs.lock_flag); + UNSERIALIZE_SCALAR(miscRegs.lock_addr); UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); +#if FULL_SYSTEM + UNSERIALIZE_ARRAY(palregs, NumIntRegs); + UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); + UNSERIALIZE_SCALAR(intrflag); + UNSERIALIZE_SCALAR(pal_shadow); +#endif +} + + +#if FULL_SYSTEM +void +PTE::serialize(std::ostream &os) +{ + SERIALIZE_SCALAR(tag); + SERIALIZE_SCALAR(ppn); + SERIALIZE_SCALAR(xre); + SERIALIZE_SCALAR(xwe); + SERIALIZE_SCALAR(asn); + SERIALIZE_SCALAR(asma); + SERIALIZE_SCALAR(fonr); + SERIALIZE_SCALAR(fonw); + SERIALIZE_SCALAR(valid); +} + + +void +PTE::unserialize(Checkpoint *cp, const std::string §ion) +{ + UNSERIALIZE_SCALAR(tag); + UNSERIALIZE_SCALAR(ppn); + UNSERIALIZE_SCALAR(xre); + UNSERIALIZE_SCALAR(xwe); + UNSERIALIZE_SCALAR(asn); + UNSERIALIZE_SCALAR(asma); + UNSERIALIZE_SCALAR(fonr); + UNSERIALIZE_SCALAR(fonw); + UNSERIALIZE_SCALAR(valid); } #endif //FULL_SYSTEM diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh index 603af60e2..71da82ffa 100644 --- a/arch/mips/isa_traits.hh +++ b/arch/mips/isa_traits.hh @@ -29,13 +29,14 @@ #ifndef __ARCH_MIPS_ISA_TRAITS_HH__ #define __ARCH_MIPS_ISA_TRAITS_HH__ -//This makes sure the big endian versions of certain functions are used. namespace LittleEndianGuest {} -using namespace LittleEndianGuest +using namespace LittleEndianGuest; -#include "arch/mips/faults.hh" +//#include "arch/mips/faults.hh" #include "base/misc.hh" +#include "config/full_system.hh" #include "sim/host.hh" +#include "sim/faults.hh" class FastCPU; class FullCPU; @@ -43,453 +44,260 @@ class Checkpoint; #define TARGET_MIPS -template <class ISA> class StaticInst; -template <class ISA> class StaticInstPtr; +class StaticInst; +class StaticInstPtr; -//namespace MIPS34K -//{ -// int DTB_ASN_ASN(uint64_t reg); -// int ITB_ASN_ASN(uint64_t reg); -//} +namespace MIPS34K { +int DTB_ASN_ASN(uint64_t reg); +int ITB_ASN_ASN(uint64_t reg); +} -class MipsISA +namespace MipsISA { - public: - - typedef uint32_t MachInst; - typedef uint64_t Addr; - typedef uint8_t RegIndex; - - enum - { - MemoryEnd = 0xffffffffffffffffULL, - - NumFloatRegs = 32, - NumMiscRegs = 32, - MaxRegsOfAnyType = 32, - // Static instruction parameters - MaxInstSrcRegs = 3, - MaxInstDestRegs = 2, - - // Maximum trap level - MaxTL = 4 + typedef uint32_t MachInst; +// typedef uint64_t Addr; + typedef uint8_t RegIndex; + + enum { + MemoryEnd = 0xffffffffffffffffULL, + + NumIntRegs = 32, + NumFloatRegs = 32, + NumMiscRegs = 32, + + MaxRegsOfAnyType = 32, + // Static instruction parameters + MaxInstSrcRegs = 3, + MaxInstDestRegs = 2, + + // semantically meaningful register indices + ZeroReg = 31, // architecturally meaningful + // the rest of these depend on the ABI + StackPointerReg = 30, + GlobalPointerReg = 29, + ProcedureValueReg = 27, + ReturnAddressReg = 26, + ReturnValueReg = 0, + FramePointerReg = 15, + ArgumentReg0 = 16, + ArgumentReg1 = 17, + ArgumentReg2 = 18, + ArgumentReg3 = 19, + ArgumentReg4 = 20, + ArgumentReg5 = 21, + + LogVMPageSize = 13, // 8K bytes + VMPageSize = (1 << LogVMPageSize), + + BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned + + WordBytes = 4, + HalfwordBytes = 2, + ByteBytes = 1, + DepNA = 0, + }; + + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 32, + Ctrl_Base_DepTag = 64, + Fpcr_DepTag = 64, // floating point control register + Uniq_DepTag = 65, + IPR_Base_DepTag = 66 + }; + + typedef uint64_t IntReg; + typedef IntReg IntRegFile[NumIntRegs]; + + // floating point register file entry type + typedef union { + uint64_t q; + double d; + } FloatReg; + + typedef union { + uint64_t q[NumFloatRegs]; // integer qword view + double d[NumFloatRegs]; // double-precision floating point view + } FloatRegFile; + + // control register file contents + typedef uint64_t MiscReg; + typedef struct { + uint64_t fpcr; // floating point condition codes + uint64_t uniq; // process-unique register + bool lock_flag; // lock flag for LL/SC + Addr lock_addr; // lock address for LL/SC + } MiscRegFile; + +extern const Addr PageShift; +extern const Addr PageBytes; +extern const Addr PageMask; +extern const Addr PageOffset; + +#if FULL_SYSTEM + + typedef uint64_t InternalProcReg; + +#include "arch/mips/isa_fullsys_traits.hh" + +#else + enum { + NumInternalProcRegs = 0 + }; +#endif - // semantically meaningful register indices - ZeroReg = 0, // architecturally meaningful - // the rest of these depend on the ABI - } - typedef uint64_t IntReg; + enum { + TotalNumRegs = + NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs + }; + + enum { + TotalDataRegs = NumIntRegs + NumFloatRegs + }; + + typedef union { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + struct RegFile { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegs; // control register file + Addr pc; // program counter + Addr npc; // next-cycle program counter +#if FULL_SYSTEM + IntReg palregs[NumIntRegs]; // PAL shadow registers + InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs + int intrflag; // interrupt flag + bool pal_shadow; // using pal_shadow registers + inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } + inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } +#endif // FULL_SYSTEM + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + StaticInstPtr decodeInst(MachInst); + + // return a no-op instruction... used for instruction fetch faults + extern const MachInst NoopMachInst; + + enum annotes { + ANNOTE_NONE = 0, + // An impossible number for instruction annotations + ITOUCH_ANNOTE = 0xffffffff, + }; + + static inline bool isCallerSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); + } + + static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return (reg >= 9 && reg <= 15); + } + + static inline bool isCallerSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + static inline bool isCalleeSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + static inline Addr alignAddress(const Addr &addr, + unsigned int nbytes) { + return (addr & ~(nbytes - 1)); + } + + // Instruction address compression hooks + static inline Addr realPCToFetchPC(const Addr &addr) { + return addr; + } + + static inline Addr fetchPCToRealPC(const Addr &addr) { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + static inline size_t fetchInstSize() { + return sizeof(MachInst); + } + + static inline MachInst makeRegisterCopy(int dest, int src) { + panic("makeRegisterCopy not implemented"); + return 0; + } + + // Machine operations + + void saveMachineReg(AnyReg &savereg, const RegFile ®_file, + int regnum); + + void restoreMachineReg(RegFile ®s, const AnyReg ®, + int regnum); + +#if 0 + static void serializeSpecialRegs(const Serializable::Proxy &proxy, + const RegFile ®s); + + static void unserializeSpecialRegs(const IniFile *db, + const std::string &category, + ConfigNode *node, + RegFile ®s); +#endif - class IntRegFile - { - private: - //For right now, let's pretend the register file is static - IntReg regs[32]; - public: - IntReg & operator [] (RegIndex index) - { - //Don't allow indexes outside of the 32 registers - index &= 0x1F - return regs[index]; - } - }; - - void inline serialize(std::ostream & os) - { - SERIALIZE_ARRAY(regs, 32); - } - - void inline unserialize(Checkpoint &*cp, const std::string §ion) - { - UNSERIALIZE_ARRAY(regs, 32); - } - - class FloatRegFile - { - private: - //By using the largest data type, we ensure everything - //is aligned correctly in memory - union - { - double double rawRegs[16]; - uint64_t regDump[32]; - }; - class QuadRegs - { - private: - FloatRegFile * parent; - public: - QuadRegs(FloatRegFile * p) : parent(p) {;} - double double & operator [] (RegIndex index) - { - //Quad floats are index by the single - //precision register the start on, - //and only 16 should be accessed - index = (index >> 2) & 0xF; - return parent->rawRegs[index]; - } - }; - class DoubleRegs - { - private: - FloatRegFile * parent; - public: - DoubleRegs(FloatRegFile * p) : parent(p) {;} - double & operator [] (RegIndex index) - { - //Double floats are index by the single - //precision register the start on, - //and only 32 should be accessed - index = (index >> 1) & 0x1F - return ((double [])parent->rawRegs)[index]; - } - } - class SingleRegs - { - private: - FloatRegFile * parent; - public: - SingleRegs(FloatRegFile * p) : parent(p) {;} - double & operator [] (RegFile index) - { - //Only 32 single floats should be accessed - index &= 0x1F - return ((float [])parent->rawRegs)[index]; - } - } - public: - void inline serialize(std::ostream & os) - { - SERIALIZE_ARRAY(regDump, 32); - } - - void inline unserialize(Checkpoint &* cp, std::string & section) - { - UNSERIALIZE_ARRAY(regDump, 32); - } - - QuadRegs quadRegs; - DoubleRegs doubleRegs; - SingleRegs singleRegs; - FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) - {;} - }; - - // control register file contents - typedef uint64_t MiscReg; - // The control registers, broken out into fields - class MiscRegFile - { - public: - union - { - uint16_t pstate; // Process State Register - struct - { - uint16_t ag:1; // Alternate Globals - uint16_t ie:1; // Interrupt enable - uint16_t priv:1; // Privelege mode - uint16_t am:1; // Address mask - uint16_t pef:1; // PSTATE enable floating-point - uint16_t red:1; // RED (reset, error, debug) state - uint16_t mm:2; // Memory Model - uint16_t tle:1; // Trap little-endian - uint16_t cle:1; // Current little-endian - } pstateFields; - } - uint64_t tba; // Trap Base Address - union - { - uint64_t y; // Y (used in obsolete multiplication) - struct - { - uint64_t value:32; // The actual value stored in y - const uint64_t :32; // reserved bits - } yFields; - } - uint8_t pil; // Process Interrupt Register - uint8_t cwp; // Current Window Pointer - uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) - union - { - uint8_t ccr; // Condition Code Register - struct - { - union - { - uint8_t icc:4; // 32-bit condition codes - struct - { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } iccFields:4; - } :4; - union - { - uint8_t xcc:4; // 64-bit condition codes - struct - { - uint8_t c:1; // Carry - uint8_t v:1; // Overflow - uint8_t z:1; // Zero - uint8_t n:1; // Negative - } xccFields:4; - } :4; - } ccrFields; - } - uint8_t asi; // Address Space Identifier - uint8_t tl; // Trap Level - uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) - uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) - union - { - uint64_t tstate[MaxTL]; // Trap State - struct - { - //Values are from previous trap level - uint64_t cwp:5; // Current Window Pointer - const uint64_t :2; // Reserved bits - uint64_t pstate:10; // Process State - const uint64_t :6; // Reserved bits - uint64_t asi:8; // Address Space Identifier - uint64_t ccr:8; // Condition Code Register - } tstateFields[MaxTL]; - } - union - { - uint64_t tick; // Hardware clock-tick counter - struct - { - uint64_t counter:63; // Clock-tick count - uint64_t npt:1; // Non-priveleged trap - } tickFields; - } - uint8_t cansave; // Savable windows - uint8_t canrestore; // Restorable windows - uint8_t otherwin; // Other windows - uint8_t cleanwin; // Clean windows - union - { - uint8_t wstate; // Window State - struct - { - uint8_t normal:3; // Bits TT<4:2> are set to on a normal - // register window trap - uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" - // register window trap - } wstateFields; - } - union - { - uint64_t ver; // Version - struct - { - uint64_t maxwin:5; // Max CWP value - const uint64_t :2; // Reserved bits - uint64_t maxtl:8; // Maximum trap level - const uint64_t :8; // Reserved bits - uint64_t mask:8; // Processor mask set revision number - uint64_t impl:16; // Implementation identification number - uint64_t manuf:16; // Manufacturer code - } verFields; - } - union - { - uint64_t fsr; // Floating-Point State Register - struct - { - union - { - uint64_t cexc:5; // Current excpetion - struct - { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } cexecFields:5; - } :5; - union - { - uint64_t aexc:5; // Accrued exception - struct - { - uint64_t nxc:1; // Inexact - uint64_t dzc:1; // Divide by zero - uint64_t ufc:1; // Underflow - uint64_t ofc:1; // Overflow - uint64_t nvc:1; // Invalid operand - } aexecFields:5; - } :5; - uint64_t fcc0:2; // Floating-Point condtion codes - const uint64_t :1; // Reserved bits - uint64_t qne:1; // Deferred trap queue not empty - // with no queue, it should read 0 - uint64_t ftt:3; // Floating-Point trap type - uint64_t ver:3; // Version (of the FPU) - const uint64_t :2; // Reserved bits - uint64_t ns:1; // Nonstandard floating point - union - { - uint64_t tem:5; // Trap Enable Mask - struct - { - uint64_t nxm:1; // Inexact - uint64_t dzm:1; // Divide by zero - uint64_t ufm:1; // Underflow - uint64_t ofm:1; // Overflow - uint64_t nvm:1; // Invalid operand - } temFields:5; - } :5; - const uint64_t :2; // Reserved bits - uint64_t rd:2; // Rounding direction - uint64_t fcc1:2; // Floating-Point condition codes - uint64_t fcc2:2; // Floating-Point condition codes - uint64_t fcc3:2; // Floating-Point condition codes - const uint64_t :26; // Reserved bits - } fsrFields; - } - union - { - uint8_t fprs; // Floating-Point Register State - struct - { - dl:1; // Dirty lower - du:1; // Dirty upper - fef:1; // FPRS enable floating-Point - } fprsFields; - }; - - void serialize(std::ostream & os) - { - SERIALIZE_SCALAR(pstate); - SERIAlIZE_SCALAR(tba); - SERIALIZE_SCALAR(y); - SERIALIZE_SCALAR(pil); - SERIALIZE_SCALAR(cwp); - SERIALIZE_ARRAY(tt, MaxTL); - SERIALIZE_SCALAR(ccr); - SERIALIZE_SCALAR(asi); - SERIALIZE_SCALAR(tl); - SERIALIZE_SCALAR(tpc); - SERIALIZE_SCALAR(tnpc); - SERIALIZE_ARRAY(tstate, MaxTL); - SERIALIZE_SCALAR(tick); - SERIALIZE_SCALAR(cansave); - SERIALIZE_SCALAR(canrestore); - SERIALIZE_SCALAR(otherwin); - SERIALIZE_SCALAR(cleanwin); - SERIALIZE_SCALAR(wstate); - SERIALIZE_SCALAR(ver); - SERIALIZE_SCALAR(fsr); - SERIALIZE_SCALAR(fprs); - } - - void unserialize(Checkpoint &* cp, std::string & section) - { - UNSERIALIZE_SCALAR(pstate); - UNSERIAlIZE_SCALAR(tba); - UNSERIALIZE_SCALAR(y); - UNSERIALIZE_SCALAR(pil); - UNSERIALIZE_SCALAR(cwp); - UNSERIALIZE_ARRAY(tt, MaxTL); - UNSERIALIZE_SCALAR(ccr); - UNSERIALIZE_SCALAR(asi); - UNSERIALIZE_SCALAR(tl); - UNSERIALIZE_SCALAR(tpc); - UNSERIALIZE_SCALAR(tnpc); - UNSERIALIZE_ARRAY(tstate, MaxTL); - UNSERIALIZE_SCALAR(tick); - UNSERIALIZE_SCALAR(cansave); - UNSERIALIZE_SCALAR(canrestore); - UNSERIALIZE_SCALAR(otherwin); - UNSERIALIZE_SCALAR(cleanwin); - UNSERIALIZE_SCALAR(wstate); - UNSERIALIZE_SCALAR(ver); - UNSERIALIZE_SCALAR(fsr); - UNSERIALIZE_SCALAR(fprs); - } - }; - - typedef union - { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - struct RegFile - { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file - - Addr pc; // Program Counter - Addr npc; // Next Program Counter - Addr nnpc; // Next next program Counter - - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - }; - - static StaticInstPtr<MipsISA> decodeInst(MachInst); - - // return a no-op instruction... used for instruction fetch faults - static const MachInst NoopMachInst; - - // Instruction address compression hooks - static inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - static inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - static inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template <class XC> - static void zeroRegisters(XC *xc); + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + void zeroRegisters(XC *xc); + + +//typedef MipsISA TheISA; + +//typedef TheISA::MachInst MachInst; +//typedef TheISA::Addr Addr; +//typedef TheISA::RegIndex RegIndex; +//typedef TheISA::IntReg IntReg; +//typedef TheISA::IntRegFile IntRegFile; +//typedef TheISA::FloatReg FloatReg; +//typedef TheISA::FloatRegFile FloatRegFile; +//typedef TheISA::MiscReg MiscReg; +//typedef TheISA::MiscRegFile MiscRegFile; +//typedef TheISA::AnyReg AnyReg; +//typedef TheISA::RegFile RegFile; + +//const int NumIntRegs = TheISA::NumIntRegs; +//const int NumFloatRegs = TheISA::NumFloatRegs; +//const int NumMiscRegs = TheISA::NumMiscRegs; +//const int TotalNumRegs = TheISA::TotalNumRegs; +//const int VMPageSize = TheISA::VMPageSize; +//const int LogVMPageSize = TheISA::LogVMPageSize; +//const int ZeroReg = TheISA::ZeroReg; +//const int StackPointerReg = TheISA::StackPointerReg; +//const int GlobalPointerReg = TheISA::GlobalPointerReg; +//const int ReturnAddressReg = TheISA::ReturnAddressReg; +//const int ReturnValueReg = TheISA::ReturnValueReg; +//const int ArgumentReg0 = TheISA::ArgumentReg0; +//const int ArgumentReg1 = TheISA::ArgumentReg1; +//const int ArgumentReg2 = TheISA::ArgumentReg2; +//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; +const Addr MaxAddr = (Addr)-1; }; - -typedef MIPSISA TheISA; - -typedef TheISA::MachInst MachInst; -typedef TheISA::Addr Addr; -typedef TheISA::RegIndex RegIndex; -typedef TheISA::IntReg IntReg; -typedef TheISA::IntRegFile IntRegFile; -typedef TheISA::FloatReg FloatReg; -typedef TheISA::FloatRegFile FloatRegFile; -typedef TheISA::MiscReg MiscReg; -typedef TheISA::MiscRegFile MiscRegFile; -typedef TheISA::AnyReg AnyReg; -typedef TheISA::RegFile RegFile; - -const int VMPageSize = TheISA::VMPageSize; -const int LogVMPageSize = TheISA::LogVMPageSize; -const int ZeroReg = TheISA::ZeroReg; -const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; -const int MaxAddr = (Addr)-1; - -#ifndef FULL_SYSTEM +#if !FULL_SYSTEM class SyscallReturn { public: template <class T> @@ -526,7 +334,10 @@ class SyscallReturn { #endif -#ifdef FULL_SYSTEM +#if FULL_SYSTEM +//typedef TheISA::InternalProcReg InternalProcReg; +//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; +//const int NumInterruptLevels = TheISA::NumInterruptLevels; #include "arch/mips/mips34k.hh" #endif diff --git a/arch/mips/linux_process.cc b/arch/mips/linux_process.cc new file mode 100644 index 000000000..d3aca15bc --- /dev/null +++ b/arch/mips/linux_process.cc @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/mips_common_syscall_emul.hh" +#include "arch/mips/mips_linux_process.hh" +#include "arch/mips/isa_traits.hh" + +#include "base/trace.hh" +#include "cpu/exec_context.hh" +#include "kern/linux/linux.hh" +#include "mem/functional/functional.hh" + +#include "sim/process.hh" +#include "sim/syscall_emul.hh" + +using namespace std; +using namespace MipsISA; + +/// Target uname() handler. +static SyscallReturn +unameFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + + strcpy(name->sysname, "Linux"); + strcpy(name->nodename, "m5.eecs.umich.edu"); + strcpy(name->release, "2.4.20"); + strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); + strcpy(name->machine, "mips"); + + name.copyOut(xc->mem); + return 0; +} + +/// Target osf_getsysyinfo() handler. Even though this call is +/// borrowed from Tru64, the subcases that get used appear to be +/// different in practice from those used by Tru64 processes. +static SyscallReturn +osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 45: { // GSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + *fpcr = 0; + fpcr.copyOut(xc->mem); + return 0; + } + + default: + cerr << "osf_getsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + +/// Target osf_setsysinfo() handler. +static SyscallReturn +osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, + ExecContext *xc) +{ + unsigned op = xc->getSyscallArg(0); + // unsigned nbytes = xc->getSyscallArg(2); + + switch (op) { + + case 14: { // SSI_IEEE_FP_CONTROL + TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + // I don't think this exactly matches the HW FPCR + fpcr.copyIn(xc->mem); + DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " + " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); + return 0; + } + + default: + cerr << "osf_setsysinfo: unknown op " << op << endl; + abort(); + break; + } + + return 1; +} + + +SyscallDesc MipsLinuxProcess::syscallDescs[] = { + /* 0 */ SyscallDesc("osf_syscall", unimplementedFunc), + /* 1 */ SyscallDesc("exit", exitFunc), + /* 2 */ SyscallDesc("fork", unimplementedFunc), + /* 3 */ SyscallDesc("read", readFunc), + /* 4 */ SyscallDesc("write", writeFunc), + /* 5 */ SyscallDesc("osf_old_open", unimplementedFunc), + /* 6 */ SyscallDesc("close", closeFunc), + /* 7 */ SyscallDesc("osf_wait4", unimplementedFunc), + /* 8 */ SyscallDesc("osf_old_creat", unimplementedFunc), + /* 9 */ SyscallDesc("link", unimplementedFunc), + /* 10 */ SyscallDesc("unlink", unlinkFunc), + /* 11 */ SyscallDesc("osf_execve", unimplementedFunc), + /* 12 */ SyscallDesc("chdir", unimplementedFunc), + /* 13 */ SyscallDesc("fchdir", unimplementedFunc), + /* 14 */ SyscallDesc("mknod", unimplementedFunc), + /* 15 */ SyscallDesc("chmod", chmodFunc<Linux>), + /* 16 */ SyscallDesc("chown", chownFunc), + /* 17 */ SyscallDesc("brk", obreakFunc), + /* 18 */ SyscallDesc("osf_getfsstat", unimplementedFunc), + /* 19 */ SyscallDesc("lseek", lseekFunc), + /* 20 */ SyscallDesc("getxpid", getpidFunc), + /* 21 */ SyscallDesc("osf_mount", unimplementedFunc), + /* 22 */ SyscallDesc("umount", unimplementedFunc), + /* 23 */ SyscallDesc("setuid", setuidFunc), + /* 24 */ SyscallDesc("getxuid", getuidFunc), + /* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc), + /* 26 */ SyscallDesc("osf_ptrace", unimplementedFunc), + /* 27 */ SyscallDesc("osf_nrecvmsg", unimplementedFunc), + /* 28 */ SyscallDesc("osf_nsendmsg", unimplementedFunc), + /* 29 */ SyscallDesc("osf_nrecvfrom", unimplementedFunc), + /* 30 */ SyscallDesc("osf_naccept", unimplementedFunc), + /* 31 */ SyscallDesc("osf_ngetpeername", unimplementedFunc), + /* 32 */ SyscallDesc("osf_ngetsockname", unimplementedFunc), + /* 33 */ SyscallDesc("access", unimplementedFunc), + /* 34 */ SyscallDesc("osf_chflags", unimplementedFunc), + /* 35 */ SyscallDesc("osf_fchflags", unimplementedFunc), + /* 36 */ SyscallDesc("sync", unimplementedFunc), + /* 37 */ SyscallDesc("kill", unimplementedFunc), + /* 38 */ SyscallDesc("osf_old_stat", unimplementedFunc), + /* 39 */ SyscallDesc("setpgid", unimplementedFunc), + /* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc), + /* 41 */ SyscallDesc("dup", unimplementedFunc), + /* 42 */ SyscallDesc("pipe", unimplementedFunc), + /* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc), + /* 44 */ SyscallDesc("osf_profil", unimplementedFunc), + /* 45 */ SyscallDesc("open", openFunc<Linux>), + /* 46 */ SyscallDesc("osf_old_sigaction", unimplementedFunc), + /* 47 */ SyscallDesc("getxgid", getgidFunc), + /* 48 */ SyscallDesc("osf_sigprocmask", ignoreFunc), + /* 49 */ SyscallDesc("osf_getlogin", unimplementedFunc), + /* 50 */ SyscallDesc("osf_setlogin", unimplementedFunc), + /* 51 */ SyscallDesc("acct", unimplementedFunc), + /* 52 */ SyscallDesc("sigpending", unimplementedFunc), + /* 53 */ SyscallDesc("osf_classcntl", unimplementedFunc), + /* 54 */ SyscallDesc("ioctl", ioctlFunc<Linux>), + /* 55 */ SyscallDesc("osf_reboot", unimplementedFunc), + /* 56 */ SyscallDesc("osf_revoke", unimplementedFunc), + /* 57 */ SyscallDesc("symlink", unimplementedFunc), + /* 58 */ SyscallDesc("readlink", unimplementedFunc), + /* 59 */ SyscallDesc("execve", unimplementedFunc), + /* 60 */ SyscallDesc("umask", unimplementedFunc), + /* 61 */ SyscallDesc("chroot", unimplementedFunc), + /* 62 */ SyscallDesc("osf_old_fstat", unimplementedFunc), + /* 63 */ SyscallDesc("getpgrp", unimplementedFunc), + /* 64 */ SyscallDesc("getpagesize", getpagesizeFunc), + /* 65 */ SyscallDesc("osf_mremap", unimplementedFunc), + /* 66 */ SyscallDesc("vfork", unimplementedFunc), + /* 67 */ SyscallDesc("stat", statFunc<Linux>), + /* 68 */ SyscallDesc("lstat", lstatFunc<Linux>), + /* 69 */ SyscallDesc("osf_sbrk", unimplementedFunc), + /* 70 */ SyscallDesc("osf_sstk", unimplementedFunc), + /* 71 */ SyscallDesc("mmap", mmapFunc<Linux>), + /* 72 */ SyscallDesc("osf_old_vadvise", unimplementedFunc), + /* 73 */ SyscallDesc("munmap", munmapFunc), + /* 74 */ SyscallDesc("mprotect", ignoreFunc), + /* 75 */ SyscallDesc("madvise", unimplementedFunc), + /* 76 */ SyscallDesc("vhangup", unimplementedFunc), + /* 77 */ SyscallDesc("osf_kmodcall", unimplementedFunc), + /* 78 */ SyscallDesc("osf_mincore", unimplementedFunc), + /* 79 */ SyscallDesc("getgroups", unimplementedFunc), + /* 80 */ SyscallDesc("setgroups", unimplementedFunc), + /* 81 */ SyscallDesc("osf_old_getpgrp", unimplementedFunc), + /* 82 */ SyscallDesc("setpgrp", unimplementedFunc), + /* 83 */ SyscallDesc("osf_setitimer", unimplementedFunc), + /* 84 */ SyscallDesc("osf_old_wait", unimplementedFunc), + /* 85 */ SyscallDesc("osf_table", unimplementedFunc), + /* 86 */ SyscallDesc("osf_getitimer", unimplementedFunc), + /* 87 */ SyscallDesc("gethostname", gethostnameFunc), + /* 88 */ SyscallDesc("sethostname", unimplementedFunc), + /* 89 */ SyscallDesc("getdtablesize", unimplementedFunc), + /* 90 */ SyscallDesc("dup2", unimplementedFunc), + /* 91 */ SyscallDesc("fstat", fstatFunc<Linux>), + /* 92 */ SyscallDesc("fcntl", fcntlFunc), + /* 93 */ SyscallDesc("osf_select", unimplementedFunc), + /* 94 */ SyscallDesc("poll", unimplementedFunc), + /* 95 */ SyscallDesc("fsync", unimplementedFunc), + /* 96 */ SyscallDesc("setpriority", unimplementedFunc), + /* 97 */ SyscallDesc("socket", unimplementedFunc), + /* 98 */ SyscallDesc("connect", unimplementedFunc), + /* 99 */ SyscallDesc("accept", unimplementedFunc), + /* 100 */ SyscallDesc("getpriority", unimplementedFunc), + /* 101 */ SyscallDesc("send", unimplementedFunc), + /* 102 */ SyscallDesc("recv", unimplementedFunc), + /* 103 */ SyscallDesc("sigreturn", unimplementedFunc), + /* 104 */ SyscallDesc("bind", unimplementedFunc), + /* 105 */ SyscallDesc("setsockopt", unimplementedFunc), + /* 106 */ SyscallDesc("listen", unimplementedFunc), + /* 107 */ SyscallDesc("osf_plock", unimplementedFunc), + /* 108 */ SyscallDesc("osf_old_sigvec", unimplementedFunc), + /* 109 */ SyscallDesc("osf_old_sigblock", unimplementedFunc), + /* 110 */ SyscallDesc("osf_old_sigsetmask", unimplementedFunc), + /* 111 */ SyscallDesc("sigsuspend", unimplementedFunc), + /* 112 */ SyscallDesc("osf_sigstack", ignoreFunc), + /* 113 */ SyscallDesc("recvmsg", unimplementedFunc), + /* 114 */ SyscallDesc("sendmsg", unimplementedFunc), + /* 115 */ SyscallDesc("osf_old_vtrace", unimplementedFunc), + /* 116 */ SyscallDesc("osf_gettimeofday", unimplementedFunc), + /* 117 */ SyscallDesc("osf_getrusage", unimplementedFunc), + /* 118 */ SyscallDesc("getsockopt", unimplementedFunc), + /* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc), + /* 120 */ SyscallDesc("readv", unimplementedFunc), + /* 121 */ SyscallDesc("writev", writevFunc<Linux>), + /* 122 */ SyscallDesc("osf_settimeofday", unimplementedFunc), + /* 123 */ SyscallDesc("fchown", fchownFunc), + /* 124 */ SyscallDesc("fchmod", fchmodFunc<Linux>), + /* 125 */ SyscallDesc("recvfrom", unimplementedFunc), + /* 126 */ SyscallDesc("setreuid", unimplementedFunc), + /* 127 */ SyscallDesc("setregid", unimplementedFunc), + /* 128 */ SyscallDesc("rename", renameFunc), + /* 129 */ SyscallDesc("truncate", unimplementedFunc), + /* 130 */ SyscallDesc("ftruncate", unimplementedFunc), + /* 131 */ SyscallDesc("flock", unimplementedFunc), + /* 132 */ SyscallDesc("setgid", unimplementedFunc), + /* 133 */ SyscallDesc("sendto", unimplementedFunc), + /* 134 */ SyscallDesc("shutdown", unimplementedFunc), + /* 135 */ SyscallDesc("socketpair", unimplementedFunc), + /* 136 */ SyscallDesc("mkdir", unimplementedFunc), + /* 137 */ SyscallDesc("rmdir", unimplementedFunc), + /* 138 */ SyscallDesc("osf_utimes", unimplementedFunc), + /* 139 */ SyscallDesc("osf_old_sigreturn", unimplementedFunc), + /* 140 */ SyscallDesc("osf_adjtime", unimplementedFunc), + /* 141 */ SyscallDesc("getpeername", unimplementedFunc), + /* 142 */ SyscallDesc("osf_gethostid", unimplementedFunc), + /* 143 */ SyscallDesc("osf_sethostid", unimplementedFunc), + /* 144 */ SyscallDesc("getrlimit", getrlimitFunc<Linux>), + /* 145 */ SyscallDesc("setrlimit", ignoreFunc), + /* 146 */ SyscallDesc("osf_old_killpg", unimplementedFunc), + /* 147 */ SyscallDesc("setsid", unimplementedFunc), + /* 148 */ SyscallDesc("quotactl", unimplementedFunc), + /* 149 */ SyscallDesc("osf_oldquota", unimplementedFunc), + /* 150 */ SyscallDesc("getsockname", unimplementedFunc), + /* 151 */ SyscallDesc("osf_pread", unimplementedFunc), + /* 152 */ SyscallDesc("osf_pwrite", unimplementedFunc), + /* 153 */ SyscallDesc("osf_pid_block", unimplementedFunc), + /* 154 */ SyscallDesc("osf_pid_unblock", unimplementedFunc), + /* 155 */ SyscallDesc("osf_signal_urti", unimplementedFunc), + /* 156 */ SyscallDesc("sigaction", ignoreFunc), + /* 157 */ SyscallDesc("osf_sigwaitprim", unimplementedFunc), + /* 158 */ SyscallDesc("osf_nfssvc", unimplementedFunc), + /* 159 */ SyscallDesc("osf_getdirentries", unimplementedFunc), + /* 160 */ SyscallDesc("osf_statfs", unimplementedFunc), + /* 161 */ SyscallDesc("osf_fstatfs", unimplementedFunc), + /* 162 */ SyscallDesc("unknown #162", unimplementedFunc), + /* 163 */ SyscallDesc("osf_async_daemon", unimplementedFunc), + /* 164 */ SyscallDesc("osf_getfh", unimplementedFunc), + /* 165 */ SyscallDesc("osf_getdomainname", unimplementedFunc), + /* 166 */ SyscallDesc("setdomainname", unimplementedFunc), + /* 167 */ SyscallDesc("unknown #167", unimplementedFunc), + /* 168 */ SyscallDesc("unknown #168", unimplementedFunc), + /* 169 */ SyscallDesc("osf_exportfs", unimplementedFunc), + /* 170 */ SyscallDesc("unknown #170", unimplementedFunc), + /* 171 */ SyscallDesc("unknown #171", unimplementedFunc), + /* 172 */ SyscallDesc("unknown #172", unimplementedFunc), + /* 173 */ SyscallDesc("unknown #173", unimplementedFunc), + /* 174 */ SyscallDesc("unknown #174", unimplementedFunc), + /* 175 */ SyscallDesc("unknown #175", unimplementedFunc), + /* 176 */ SyscallDesc("unknown #176", unimplementedFunc), + /* 177 */ SyscallDesc("unknown #177", unimplementedFunc), + /* 178 */ SyscallDesc("unknown #178", unimplementedFunc), + /* 179 */ SyscallDesc("unknown #179", unimplementedFunc), + /* 180 */ SyscallDesc("unknown #180", unimplementedFunc), + /* 181 */ SyscallDesc("osf_alt_plock", unimplementedFunc), + /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), + /* 183 */ SyscallDesc("unknown #183", unimplementedFunc), + /* 184 */ SyscallDesc("osf_getmnt", unimplementedFunc), + /* 185 */ SyscallDesc("unknown #185", unimplementedFunc), + /* 186 */ SyscallDesc("unknown #186", unimplementedFunc), + /* 187 */ SyscallDesc("osf_alt_sigpending", unimplementedFunc), + /* 188 */ SyscallDesc("osf_alt_setsid", unimplementedFunc), + /* 189 */ SyscallDesc("unknown #189", unimplementedFunc), + /* 190 */ SyscallDesc("unknown #190", unimplementedFunc), + /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), + /* 192 */ SyscallDesc("unknown #192", unimplementedFunc), + /* 193 */ SyscallDesc("unknown #193", unimplementedFunc), + /* 194 */ SyscallDesc("unknown #194", unimplementedFunc), + /* 195 */ SyscallDesc("unknown #195", unimplementedFunc), + /* 196 */ SyscallDesc("unknown #196", unimplementedFunc), + /* 197 */ SyscallDesc("unknown #197", unimplementedFunc), + /* 198 */ SyscallDesc("unknown #198", unimplementedFunc), + /* 199 */ SyscallDesc("osf_swapon", unimplementedFunc), + /* 200 */ SyscallDesc("msgctl", unimplementedFunc), + /* 201 */ SyscallDesc("msgget", unimplementedFunc), + /* 202 */ SyscallDesc("msgrcv", unimplementedFunc), + /* 203 */ SyscallDesc("msgsnd", unimplementedFunc), + /* 204 */ SyscallDesc("semctl", unimplementedFunc), + /* 205 */ SyscallDesc("semget", unimplementedFunc), + /* 206 */ SyscallDesc("semop", unimplementedFunc), + /* 207 */ SyscallDesc("osf_utsname", unimplementedFunc), + /* 208 */ SyscallDesc("lchown", unimplementedFunc), + /* 209 */ SyscallDesc("osf_shmat", unimplementedFunc), + /* 210 */ SyscallDesc("shmctl", unimplementedFunc), + /* 211 */ SyscallDesc("shmdt", unimplementedFunc), + /* 212 */ SyscallDesc("shmget", unimplementedFunc), + /* 213 */ SyscallDesc("osf_mvalid", unimplementedFunc), + /* 214 */ SyscallDesc("osf_getaddressconf", unimplementedFunc), + /* 215 */ SyscallDesc("osf_msleep", unimplementedFunc), + /* 216 */ SyscallDesc("osf_mwakeup", unimplementedFunc), + /* 217 */ SyscallDesc("msync", unimplementedFunc), + /* 218 */ SyscallDesc("osf_signal", unimplementedFunc), + /* 219 */ SyscallDesc("osf_utc_gettime", unimplementedFunc), + /* 220 */ SyscallDesc("osf_utc_adjtime", unimplementedFunc), + /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), + /* 222 */ SyscallDesc("osf_security", unimplementedFunc), + /* 223 */ SyscallDesc("osf_kloadcall", unimplementedFunc), + /* 224 */ SyscallDesc("unknown #224", unimplementedFunc), + /* 225 */ SyscallDesc("unknown #225", unimplementedFunc), + /* 226 */ SyscallDesc("unknown #226", unimplementedFunc), + /* 227 */ SyscallDesc("unknown #227", unimplementedFunc), + /* 228 */ SyscallDesc("unknown #228", unimplementedFunc), + /* 229 */ SyscallDesc("unknown #229", unimplementedFunc), + /* 230 */ SyscallDesc("unknown #230", unimplementedFunc), + /* 231 */ SyscallDesc("unknown #231", unimplementedFunc), + /* 232 */ SyscallDesc("unknown #232", unimplementedFunc), + /* 233 */ SyscallDesc("getpgid", unimplementedFunc), + /* 234 */ SyscallDesc("getsid", unimplementedFunc), + /* 235 */ SyscallDesc("sigaltstack", ignoreFunc), + /* 236 */ SyscallDesc("osf_waitid", unimplementedFunc), + /* 237 */ SyscallDesc("osf_priocntlset", unimplementedFunc), + /* 238 */ SyscallDesc("osf_sigsendset", unimplementedFunc), + /* 239 */ SyscallDesc("osf_set_speculative", unimplementedFunc), + /* 240 */ SyscallDesc("osf_msfs_syscall", unimplementedFunc), + /* 241 */ SyscallDesc("osf_sysinfo", unimplementedFunc), + /* 242 */ SyscallDesc("osf_uadmin", unimplementedFunc), + /* 243 */ SyscallDesc("osf_fuser", unimplementedFunc), + /* 244 */ SyscallDesc("osf_proplist_syscall", unimplementedFunc), + /* 245 */ SyscallDesc("osf_ntp_adjtime", unimplementedFunc), + /* 246 */ SyscallDesc("osf_ntp_gettime", unimplementedFunc), + /* 247 */ SyscallDesc("osf_pathconf", unimplementedFunc), + /* 248 */ SyscallDesc("osf_fpathconf", unimplementedFunc), + /* 249 */ SyscallDesc("unknown #249", unimplementedFunc), + /* 250 */ SyscallDesc("osf_uswitch", unimplementedFunc), + /* 251 */ SyscallDesc("osf_usleep_thread", unimplementedFunc), + /* 252 */ SyscallDesc("osf_audcntl", unimplementedFunc), + /* 253 */ SyscallDesc("osf_audgen", unimplementedFunc), + /* 254 */ SyscallDesc("sysfs", unimplementedFunc), + /* 255 */ SyscallDesc("osf_subsys_info", unimplementedFunc), + /* 256 */ SyscallDesc("osf_getsysinfo", osf_getsysinfoFunc), + /* 257 */ SyscallDesc("osf_setsysinfo", osf_setsysinfoFunc), + /* 258 */ SyscallDesc("osf_afs_syscall", unimplementedFunc), + /* 259 */ SyscallDesc("osf_swapctl", unimplementedFunc), + /* 260 */ SyscallDesc("osf_memcntl", unimplementedFunc), + /* 261 */ SyscallDesc("osf_fdatasync", unimplementedFunc), + /* 262 */ SyscallDesc("unknown #262", unimplementedFunc), + /* 263 */ SyscallDesc("unknown #263", unimplementedFunc), + /* 264 */ SyscallDesc("unknown #264", unimplementedFunc), + /* 265 */ SyscallDesc("unknown #265", unimplementedFunc), + /* 266 */ SyscallDesc("unknown #266", unimplementedFunc), + /* 267 */ SyscallDesc("unknown #267", unimplementedFunc), + /* 268 */ SyscallDesc("unknown #268", unimplementedFunc), + /* 269 */ SyscallDesc("unknown #269", unimplementedFunc), + /* 270 */ SyscallDesc("unknown #270", unimplementedFunc), + /* 271 */ SyscallDesc("unknown #271", unimplementedFunc), + /* 272 */ SyscallDesc("unknown #272", unimplementedFunc), + /* 273 */ SyscallDesc("unknown #273", unimplementedFunc), + /* 274 */ SyscallDesc("unknown #274", unimplementedFunc), + /* 275 */ SyscallDesc("unknown #275", unimplementedFunc), + /* 276 */ SyscallDesc("unknown #276", unimplementedFunc), + /* 277 */ SyscallDesc("unknown #277", unimplementedFunc), + /* 278 */ SyscallDesc("unknown #278", unimplementedFunc), + /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), + /* 280 */ SyscallDesc("unknown #280", unimplementedFunc), + /* 281 */ SyscallDesc("unknown #281", unimplementedFunc), + /* 282 */ SyscallDesc("unknown #282", unimplementedFunc), + /* 283 */ SyscallDesc("unknown #283", unimplementedFunc), + /* 284 */ SyscallDesc("unknown #284", unimplementedFunc), + /* 285 */ SyscallDesc("unknown #285", unimplementedFunc), + /* 286 */ SyscallDesc("unknown #286", unimplementedFunc), + /* 287 */ SyscallDesc("unknown #287", unimplementedFunc), + /* 288 */ SyscallDesc("unknown #288", unimplementedFunc), + /* 289 */ SyscallDesc("unknown #289", unimplementedFunc), + /* 290 */ SyscallDesc("unknown #290", unimplementedFunc), + /* 291 */ SyscallDesc("unknown #291", unimplementedFunc), + /* 292 */ SyscallDesc("unknown #292", unimplementedFunc), + /* 293 */ SyscallDesc("unknown #293", unimplementedFunc), + /* 294 */ SyscallDesc("unknown #294", unimplementedFunc), + /* 295 */ SyscallDesc("unknown #295", unimplementedFunc), + /* 296 */ SyscallDesc("unknown #296", unimplementedFunc), + /* 297 */ SyscallDesc("unknown #297", unimplementedFunc), + /* 298 */ SyscallDesc("unknown #298", unimplementedFunc), + /* 299 */ SyscallDesc("unknown #299", unimplementedFunc), +/* + * Linux-specific system calls begin at 300 + */ + /* 300 */ SyscallDesc("bdflush", unimplementedFunc), + /* 301 */ SyscallDesc("sethae", unimplementedFunc), + /* 302 */ SyscallDesc("mount", unimplementedFunc), + /* 303 */ SyscallDesc("old_adjtimex", unimplementedFunc), + /* 304 */ SyscallDesc("swapoff", unimplementedFunc), + /* 305 */ SyscallDesc("getdents", unimplementedFunc), + /* 306 */ SyscallDesc("create_module", unimplementedFunc), + /* 307 */ SyscallDesc("init_module", unimplementedFunc), + /* 308 */ SyscallDesc("delete_module", unimplementedFunc), + /* 309 */ SyscallDesc("get_kernel_syms", unimplementedFunc), + /* 310 */ SyscallDesc("syslog", unimplementedFunc), + /* 311 */ SyscallDesc("reboot", unimplementedFunc), + /* 312 */ SyscallDesc("clone", unimplementedFunc), + /* 313 */ SyscallDesc("uselib", unimplementedFunc), + /* 314 */ SyscallDesc("mlock", unimplementedFunc), + /* 315 */ SyscallDesc("munlock", unimplementedFunc), + /* 316 */ SyscallDesc("mlockall", unimplementedFunc), + /* 317 */ SyscallDesc("munlockall", unimplementedFunc), + /* 318 */ SyscallDesc("sysinfo", unimplementedFunc), + /* 319 */ SyscallDesc("_sysctl", unimplementedFunc), + /* 320 */ SyscallDesc("was sys_idle", unimplementedFunc), + /* 321 */ SyscallDesc("oldumount", unimplementedFunc), + /* 322 */ SyscallDesc("swapon", unimplementedFunc), + /* 323 */ SyscallDesc("times", ignoreFunc), + /* 324 */ SyscallDesc("personality", unimplementedFunc), + /* 325 */ SyscallDesc("setfsuid", unimplementedFunc), + /* 326 */ SyscallDesc("setfsgid", unimplementedFunc), + /* 327 */ SyscallDesc("ustat", unimplementedFunc), + /* 328 */ SyscallDesc("statfs", unimplementedFunc), + /* 329 */ SyscallDesc("fstatfs", unimplementedFunc), + /* 330 */ SyscallDesc("sched_setparam", unimplementedFunc), + /* 331 */ SyscallDesc("sched_getparam", unimplementedFunc), + /* 332 */ SyscallDesc("sched_setscheduler", unimplementedFunc), + /* 333 */ SyscallDesc("sched_getscheduler", unimplementedFunc), + /* 334 */ SyscallDesc("sched_yield", unimplementedFunc), + /* 335 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), + /* 336 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), + /* 337 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), + /* 338 */ SyscallDesc("afs_syscall", unimplementedFunc), + /* 339 */ SyscallDesc("uname", unameFunc), + /* 340 */ SyscallDesc("nanosleep", unimplementedFunc), + /* 341 */ SyscallDesc("mremap", unimplementedFunc), + /* 342 */ SyscallDesc("nfsservctl", unimplementedFunc), + /* 343 */ SyscallDesc("setresuid", unimplementedFunc), + /* 344 */ SyscallDesc("getresuid", unimplementedFunc), + /* 345 */ SyscallDesc("pciconfig_read", unimplementedFunc), + /* 346 */ SyscallDesc("pciconfig_write", unimplementedFunc), + /* 347 */ SyscallDesc("query_module", unimplementedFunc), + /* 348 */ SyscallDesc("prctl", unimplementedFunc), + /* 349 */ SyscallDesc("pread", unimplementedFunc), + /* 350 */ SyscallDesc("pwrite", unimplementedFunc), + /* 351 */ SyscallDesc("rt_sigreturn", unimplementedFunc), + /* 352 */ SyscallDesc("rt_sigaction", ignoreFunc), + /* 353 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), + /* 354 */ SyscallDesc("rt_sigpending", unimplementedFunc), + /* 355 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), + /* 356 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), + /* 357 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), + /* 358 */ SyscallDesc("select", unimplementedFunc), + /* 359 */ SyscallDesc("gettimeofday", gettimeofdayFunc<Linux>), + /* 360 */ SyscallDesc("settimeofday", unimplementedFunc), + /* 361 */ SyscallDesc("getitimer", unimplementedFunc), + /* 362 */ SyscallDesc("setitimer", unimplementedFunc), + /* 363 */ SyscallDesc("utimes", utimesFunc<Linux>), + /* 364 */ SyscallDesc("getrusage", getrusageFunc<Linux>), + /* 365 */ SyscallDesc("wait4", unimplementedFunc), + /* 366 */ SyscallDesc("adjtimex", unimplementedFunc), + /* 367 */ SyscallDesc("getcwd", unimplementedFunc), + /* 368 */ SyscallDesc("capget", unimplementedFunc), + /* 369 */ SyscallDesc("capset", unimplementedFunc), + /* 370 */ SyscallDesc("sendfile", unimplementedFunc), + /* 371 */ SyscallDesc("setresgid", unimplementedFunc), + /* 372 */ SyscallDesc("getresgid", unimplementedFunc), + /* 373 */ SyscallDesc("dipc", unimplementedFunc), + /* 374 */ SyscallDesc("pivot_root", unimplementedFunc), + /* 375 */ SyscallDesc("mincore", unimplementedFunc), + /* 376 */ SyscallDesc("pciconfig_iobase", unimplementedFunc), + /* 377 */ SyscallDesc("getdents64", unimplementedFunc), + /* 378 */ SyscallDesc("gettid", unimplementedFunc), + /* 379 */ SyscallDesc("readahead", unimplementedFunc), + /* 380 */ SyscallDesc("security", unimplementedFunc), + /* 381 */ SyscallDesc("tkill", unimplementedFunc), + /* 382 */ SyscallDesc("setxattr", unimplementedFunc), + /* 383 */ SyscallDesc("lsetxattr", unimplementedFunc), + /* 384 */ SyscallDesc("fsetxattr", unimplementedFunc), + /* 385 */ SyscallDesc("getxattr", unimplementedFunc), + /* 386 */ SyscallDesc("lgetxattr", unimplementedFunc), + /* 387 */ SyscallDesc("fgetxattr", unimplementedFunc), + /* 388 */ SyscallDesc("listxattr", unimplementedFunc), + /* 389 */ SyscallDesc("llistxattr", unimplementedFunc), + /* 390 */ SyscallDesc("flistxattr", unimplementedFunc), + /* 391 */ SyscallDesc("removexattr", unimplementedFunc), + /* 392 */ SyscallDesc("lremovexattr", unimplementedFunc), + /* 393 */ SyscallDesc("fremovexattr", unimplementedFunc), + /* 394 */ SyscallDesc("futex", unimplementedFunc), + /* 395 */ SyscallDesc("sched_setaffinity", unimplementedFunc), + /* 396 */ SyscallDesc("sched_getaffinity", unimplementedFunc), + /* 397 */ SyscallDesc("tuxcall", unimplementedFunc), + /* 398 */ SyscallDesc("io_setup", unimplementedFunc), + /* 399 */ SyscallDesc("io_destroy", unimplementedFunc), + /* 400 */ SyscallDesc("io_getevents", unimplementedFunc), + /* 401 */ SyscallDesc("io_submit", unimplementedFunc), + /* 402 */ SyscallDesc("io_cancel", unimplementedFunc), + /* 403 */ SyscallDesc("unknown #403", unimplementedFunc), + /* 404 */ SyscallDesc("unknown #404", unimplementedFunc), + /* 405 */ SyscallDesc("exit_group", exitFunc), // exit all threads... + /* 406 */ SyscallDesc("lookup_dcookie", unimplementedFunc), + /* 407 */ SyscallDesc("sys_epoll_create", unimplementedFunc), + /* 408 */ SyscallDesc("sys_epoll_ctl", unimplementedFunc), + /* 409 */ SyscallDesc("sys_epoll_wait", unimplementedFunc), + /* 410 */ SyscallDesc("remap_file_pages", unimplementedFunc), + /* 411 */ SyscallDesc("set_tid_address", unimplementedFunc), + /* 412 */ SyscallDesc("restart_syscall", unimplementedFunc), + /* 413 */ SyscallDesc("fadvise64", unimplementedFunc), + /* 414 */ SyscallDesc("timer_create", unimplementedFunc), + /* 415 */ SyscallDesc("timer_settime", unimplementedFunc), + /* 416 */ SyscallDesc("timer_gettime", unimplementedFunc), + /* 417 */ SyscallDesc("timer_getoverrun", unimplementedFunc), + /* 418 */ SyscallDesc("timer_delete", unimplementedFunc), + /* 419 */ SyscallDesc("clock_settime", unimplementedFunc), + /* 420 */ SyscallDesc("clock_gettime", unimplementedFunc), + /* 421 */ SyscallDesc("clock_getres", unimplementedFunc), + /* 422 */ SyscallDesc("clock_nanosleep", unimplementedFunc), + /* 423 */ SyscallDesc("semtimedop", unimplementedFunc), + /* 424 */ SyscallDesc("tgkill", unimplementedFunc), + /* 425 */ SyscallDesc("stat64", unimplementedFunc), + /* 426 */ SyscallDesc("lstat64", lstat64Func<Linux>), + /* 427 */ SyscallDesc("fstat64", fstat64Func<Linux>), + /* 428 */ SyscallDesc("vserver", unimplementedFunc), + /* 429 */ SyscallDesc("mbind", unimplementedFunc), + /* 430 */ SyscallDesc("get_mempolicy", unimplementedFunc), + /* 431 */ SyscallDesc("set_mempolicy", unimplementedFunc), + /* 432 */ SyscallDesc("mq_open", unimplementedFunc), + /* 433 */ SyscallDesc("mq_unlink", unimplementedFunc), + /* 434 */ SyscallDesc("mq_timedsend", unimplementedFunc), + /* 435 */ SyscallDesc("mq_timedreceive", unimplementedFunc), + /* 436 */ SyscallDesc("mq_notify", unimplementedFunc), + /* 437 */ SyscallDesc("mq_getsetattr", unimplementedFunc), + /* 438 */ SyscallDesc("waitid", unimplementedFunc), + /* 439 */ SyscallDesc("add_key", unimplementedFunc), + /* 440 */ SyscallDesc("request_key", unimplementedFunc), + /* 441 */ SyscallDesc("keyctl", unimplementedFunc) +}; + +MipsLinuxProcess::MipsLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp) + : LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp), + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +{ + init_regs->intRegFile[0] = 0; +} + + + +SyscallDesc* +MipsLinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum > Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} diff --git a/arch/mips/linux_process.hh b/arch/mips/linux_process.hh new file mode 100644 index 000000000..5408a6c44 --- /dev/null +++ b/arch/mips/linux_process.hh @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_LINUX_PROCESS_HH__ +#define __MIPS_LINUX_PROCESS_HH__ + +#include "sim/process.hh" + + +/// A process with emulated Mips/Linux syscalls. +class MipsLinuxProcess : public LiveProcess +{ + public: + /// Constructor. + MipsLinuxProcess(const std::string &name, + ObjectFile *objFile, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp); + + virtual SyscallDesc* getDesc(int callnum); + + /// The target system's hostname. + static const char *hostname; + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + const int Num_Syscall_Descs; +}; + + +#endif // __MIPS_LINUX_PROCESS_HH__ diff --git a/base/loader/exec_aout.h b/base/loader/exec_aout.h index 76ebe9bb5..3863a92fb 100644 --- a/base/loader/exec_aout.h +++ b/base/loader/exec_aout.h @@ -55,6 +55,6 @@ (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ N_GETMAGIC(ex) != ZMAGIC) -#include "targetarch/aout_machdep.h" +#include "arch/aout_machdep.h" #endif /* !_SYS_EXEC_AOUT_H_ */ diff --git a/base/loader/exec_ecoff.h b/base/loader/exec_ecoff.h index 4eece4318..79cd22a6e 100644 --- a/base/loader/exec_ecoff.h +++ b/base/loader/exec_ecoff.h @@ -37,7 +37,7 @@ #ifndef _SYS_EXEC_ECOFF_H_ #define _SYS_EXEC_ECOFF_H_ -#include "targetarch/ecoff_machdep.h" +#include "arch/ecoff_machdep.h" struct ecoff_filehdr { coff_ushort f_magic; /* magic number */ diff --git a/base/refcnt.hh b/base/refcnt.hh index 9d9ed4337..de589f7c5 100644 --- a/base/refcnt.hh +++ b/base/refcnt.hh @@ -29,6 +29,8 @@ #ifndef __REFCNT_HH__ #define __REFCNT_HH__ +#include <stddef.h> //For the NULL macro definition + class RefCounted { private: diff --git a/base/remote_gdb.cc b/base/remote_gdb.cc index 17ec21fed..f56ddf7cf 100644 --- a/base/remote_gdb.cc +++ b/base/remote_gdb.cc @@ -129,7 +129,7 @@ #include "cpu/static_inst.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; @@ -371,7 +371,7 @@ RemoteGDB::acc(Addr va, size_t len) if (AlphaISA::PcPAL(va) || va < 0x10000) return true; - Addr ptbr = context->regs.ipr[AlphaISA::IPR_PALtemp20]; + Addr ptbr = context->readMiscReg(AlphaISA::IPR_PALtemp20); TheISA::PageTableEntry pte = kernel_pte_lookup(pmem, ptbr, va); if (!pte.valid()) { DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); diff --git a/cpu/SConscript b/cpu/SConscript index dbe174660..af6bab4eb 100644 --- a/cpu/SConscript +++ b/cpu/SConscript @@ -32,13 +32,28 @@ import os.path # Import build environment variable from SConstruct. Import('env') +################################################################# +# +# Generate StaticInst execute() method signatures. +# +# There must be one signature for each CPU model compiled in. +# Since the set of compiled-in models is flexible, we generate a +# header containing the appropriate set of signatures on the fly. +# +################################################################# + +# CPU model-specific data is contained in cpu_models.py +# Convert to SCons File node to get path handling models_db = File('cpu_models.py') +# slurp in contents of file execfile(models_db.srcnode().abspath) +# Template for execute() signature. exec_sig_template = ''' virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; ''' +# Generate header. def gen_cpu_exec_signatures(target, source, env): f = open(str(target[0]), 'w') print >> f, ''' @@ -52,7 +67,22 @@ def gen_cpu_exec_signatures(target, source, env): #endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ ''' -env.Command('static_inst_exec_sigs.hh', models_db, gen_cpu_exec_signatures) +# Generate string that gets printed when header is rebuilt +def gen_sigs_string(target, source, env): + return "Generating static_inst_exec_sigs.hh: " \ + + ', '.join(env['CPU_MODELS']) + +# Add command to generate header to environment. +env.Command('static_inst_exec_sigs.hh', models_db, + Action(gen_cpu_exec_signatures, gen_sigs_string, + varlist = ['CPU_MODELS'])) + +################################################################# +# +# Include CPU-model-specific files based on set of models +# specified in CPU_MODELS build option. +# +################################################################# sources = [] diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index 86314bef1..5905cdad2 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -36,7 +36,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" -#include "arch/alpha/faults.hh" +#include "arch/faults.hh" #include "cpu/exetrace.hh" #include "mem/mem_req.hh" @@ -45,6 +45,7 @@ #include "cpu/o3/alpha_cpu.hh" using namespace std; +using namespace TheISA; #define NOHASH #ifndef NOHASH @@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars() asid = 0; // Initialize the fault to be unimplemented opcode. - fault = UnimplementedOpcodeFault; + fault = new UnimplementedOpcodeFault; ++instcount; @@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes) break; default: - fault = MachineCheckFault; + fault = genMachineCheckFault(); break; } diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc index 9bed3ba47..7dd9bf58d 100644 --- a/cpu/exec_context.cc +++ b/cpu/exec_context.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2005 The Regents of The University of Michigan + * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -35,12 +35,13 @@ #include "base/callback.hh" #include "base/cprintf.hh" #include "base/output.hh" +#include "base/trace.hh" #include "cpu/profile.hh" #include "kern/kernel_stats.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" #else #include "sim/process.hh" #endif @@ -53,10 +54,10 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_mem) : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), - cpu_id(-1), mem(_mem), itb(_itb), dtb(_dtb), system(_sys), - memctrl(_sys->memctrl), physmem(_sys->physmem), + cpu_id(-1), lastActivate(0), lastSuspend(0), mem(_mem), itb(_itb), + dtb(_dtb), system(_sys), memctrl(_sys->memctrl), physmem(_sys->physmem), kernelBinning(system->kernelBinning), bin(kernelBinning->bin), - fnbin(kernelBinning->fnbin), profile(NULL), + fnbin(kernelBinning->fnbin), profile(NULL), quiesceEvent(this), func_exe_inst(0), storeCondFailures(0) { kernelStats = new Kernel::Statistics(this); @@ -79,8 +80,8 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid) : _status(ExecContext::Unallocated), - cpu(_cpu), thread_num(_thread_num), cpu_id(-1), - process(_process), mem(process->getMemory()), asid(_asid), + cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0), + lastSuspend(0), process(_process), mem(process->getMemory()), asid(_asid), func_exe_inst(0), storeCondFailures(0) { memset(®s, 0, sizeof(RegFile)); @@ -109,6 +110,23 @@ ExecContext::dumpFuncProfile() std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); profile->dump(this, *os); } + +ExecContext::EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc) + : Event(&mainEventQueue), xc(_xc) +{ +} + +void +ExecContext::EndQuiesceEvent::process() +{ + xc->activate(); +} + +const char* +ExecContext::EndQuiesceEvent::description() +{ + return "End Quiesce Event."; +} #endif void @@ -143,7 +161,12 @@ ExecContext::serialize(ostream &os) SERIALIZE_SCALAR(inst); #if FULL_SYSTEM + Tick quiesceEndTick = 0; + if (quiesceEvent.scheduled()) + quiesceEndTick = quiesceEvent.when(); + SERIALIZE_SCALAR(quiesceEndTick); kernelStats->serialize(os); + #endif } @@ -158,6 +181,11 @@ ExecContext::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(inst); #if FULL_SYSTEM + Tick quiesceEndTick; + UNSERIALIZE_SCALAR(quiesceEndTick); + if (quiesceEndTick) + quiesceEvent.schedule(quiesceEndTick); + kernelStats->unserialize(cp, section); #endif } @@ -169,6 +197,8 @@ ExecContext::activate(int delay) if (status() == Active) return; + lastActivate = curTick; + _status = Active; cpu->activateContext(thread_num, delay); } @@ -179,6 +209,9 @@ ExecContext::suspend() if (status() == Suspended) return; + lastActivate = curTick; + lastSuspend = curTick; +/* #if FULL_SYSTEM // Don't change the status from active if there are pending interrupts if (cpu->check_interrupts()) { @@ -186,7 +219,7 @@ ExecContext::suspend() return; } #endif - +*/ _status = Suspended; cpu->suspendContext(thread_num); } @@ -227,7 +260,7 @@ ExecContext::trap(Fault fault) /** @todo: Going to hack it for now. Do a true fixup later. */ #if FULL_SYSTEM - ev5_trap(fault); + fault->ev5_trap(this); #else fatal("fault (%d) detected @ PC 0x%08p", fault, readPC()); #endif diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 3e0d77254..d8ec88537 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2001-2005 The Regents of The University of Michigan + * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,6 +32,7 @@ #include "config/full_system.hh" #include "mem/functional/functional.hh" #include "mem/mem_req.hh" +#include "sim/eventq.hh" #include "sim/host.hh" #include "sim/serialize.hh" #include "arch/isa_traits.hh" @@ -46,7 +47,7 @@ class BaseCPU; #if FULL_SYSTEM #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" +#include "arch/tlb.hh" class FunctionProfile; class ProfileNode; @@ -71,6 +72,7 @@ class ExecContext typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::MiscRegFile MiscRegFile; + typedef TheISA::MiscReg MiscReg; public: enum Status { @@ -131,6 +133,9 @@ class ExecContext // it belongs. For full-system mode, this is the system CPU ID. int cpu_id; + Tick lastActivate; + Tick lastSuspend; + #if FULL_SYSTEM FunctionalMemory *mem; AlphaITB *itb; @@ -153,6 +158,22 @@ class ExecContext Addr profilePC; void dumpFuncProfile(); + /** Event for timing out quiesce instruction */ + struct EndQuiesceEvent : public Event + { + /** A pointer to the execution context that is quiesced */ + ExecContext *xc; + + EndQuiesceEvent(ExecContext *_xc); + + /** Event process to occur at interrupt*/ + virtual void process(); + + /** Event description */ + virtual const char *description(); + }; + EndQuiesceEvent quiesceEvent; + #else Process *process; @@ -270,8 +291,8 @@ class ExecContext #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { MiscRegFile *cregs = &req->xc->regs.miscRegs; - cregs->lock_addr = req->paddr; - cregs->lock_flag = true; + cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr); + cregs->setReg(TheISA::Lock_Flag_DepTag, true); } #endif @@ -297,10 +318,12 @@ class ExecContext req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { - req->result = cregs->lock_flag; - if (!cregs->lock_flag || - ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { - cregs->lock_flag = false; + bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag); + Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag); + req->result = lock_flag; + if (!lock_flag || + ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); if (((++req->xc->storeCondFailures) % 100000) == 0) { std::cerr << "Warning: " << req->xc->storeCondFailures @@ -321,8 +344,9 @@ class ExecContext // through. for (int i = 0; i < system->execContexts.size(); i++){ cregs = &system->execContexts[i]->regs.miscRegs; - if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { - cregs->lock_flag = false; + if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) == + (req->paddr & ~0xf)) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); } } @@ -398,34 +422,32 @@ class ExecContext regs.npc = val; } - uint64_t readUniq() + MiscReg readMiscReg(int misc_reg) { - return regs.miscRegs.uniq; + return regs.miscRegs.readReg(misc_reg); } - void setUniq(uint64_t val) + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - regs.miscRegs.uniq = val; + return regs.miscRegs.readRegWithEffect(misc_reg, fault, this); } - uint64_t readFpcr() + Fault setMiscReg(int misc_reg, const MiscReg &val) { - return regs.miscRegs.fpcr; + return regs.miscRegs.setReg(misc_reg, val); } - void setFpcr(uint64_t val) + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - regs.miscRegs.fpcr = val; + return regs.miscRegs.setRegWithEffect(misc_reg, val, this); } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault fault); + void ev5_temp_trap(Fault fault); bool simPalCheck(int palFunc); #endif diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index b35bcf9e3..38c00a3a9 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -41,6 +41,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> { protected: typedef TheISA::IntReg IntReg; + typedef TheISA::MiscReg MiscReg; + public: typedef typename Impl::Params Params; @@ -111,33 +113,24 @@ class AlphaFullCPU : public FullO3CPU<Impl> // Later on may want to remove this misc stuff from the regfile and // have it handled at this level. Might prove to be an issue when // trying to rename source/destination registers... - uint64_t readUniq() - { - return this->regFile.readUniq(); - } - - void setUniq(uint64_t val) + MiscReg readMiscReg(int misc_reg) { - this->regFile.setUniq(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; } - uint64_t readFpcr() + Fault setMiscReg(int misc_reg, const MiscReg &val) { - return this->regFile.readFpcr(); - } - - void setFpcr(uint64_t val) - { - this->regFile.setFpcr(val); + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; } // Most of the full system code and syscall emulation is not yet // implemented. These functions do show what the final interface will // look like. #if FULL_SYSTEM - uint64_t *getIpr(); - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); int readIntrFlag(); void setIntrFlag(int val); Fault hwrei(); @@ -216,8 +209,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { MiscRegFile *cregs = &req->xc->regs.miscRegs; - cregs->lock_addr = req->paddr; - cregs->lock_flag = true; + cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr); + cregs->setReg(TheISA::Lock_Flag_DepTag, true); } #endif @@ -242,22 +235,24 @@ class AlphaFullCPU : public FullO3CPU<Impl> // If this is a store conditional, act appropriately if (req->flags & LOCKED) { - cregs = &this->xc->regs.miscRegs; + cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { - req->result = cregs->lock_flag; - if (!cregs->lock_flag || - ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { - cregs->lock_flag = false; + bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag); + Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag); + req->result = lock_flag; + if (!lock_flag || + ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); if (((++req->xc->storeCondFailures) % 100000) == 0) { std::cerr << "Warning: " << req->xc->storeCondFailures << " consecutive store conditional failures " - << "on cpu " << this->cpu_id + << "on cpu " << req->xc->cpu_id << std::endl; } return NoFault; @@ -273,14 +268,15 @@ class AlphaFullCPU : public FullO3CPU<Impl> // through. for (int i = 0; i < this->system->execContexts.size(); i++){ cregs = &this->system->execContexts[i]->regs.miscRegs; - if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { - cregs->lock_flag = false; + if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) == + (req->paddr & ~0xf)) { + cregs->setReg(TheISA::Lock_Flag_DepTag, false); } } #endif - return this->mem->write(req, (T)::htog(data)); + return this->mem->write(req, (T)htog(data)); } template <class T> diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 3547fb1b5..95d2f8f37 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -50,8 +50,8 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 7ec1ba663..daa61bb1c 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC() this->xc->regs.floatRegFile.q[i] = this->regFile.readFloatRegInt(renamed_reg); } - +/* this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr; this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq; this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag; this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr; - +*/ this->xc->regs.pc = this->rob.readHeadPC(); this->xc->regs.npc = this->xc->regs.pc+4; @@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC() this->regFile.setFloatRegInt(renamed_reg, this->xc->regs.floatRegFile.q[i]); } - + /* // Then loop through the misc registers. this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr; this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq; this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag; this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr; - + */ // Then finally set the PC and the next PC. // regFile.pc = xc->regs.pc; // regFile.npc = xc->regs.npc; @@ -238,27 +238,6 @@ AlphaFullCPU<Impl>::copyFromXC() #if FULL_SYSTEM template <class Impl> -uint64_t * -AlphaFullCPU<Impl>::getIpr() -{ - return this->regFile.getIpr(); -} - -template <class Impl> -uint64_t -AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault) -{ - return this->regFile.readIpr(idx, fault); -} - -template <class Impl> -Fault -AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val) -{ - return this->regFile.setIpr(idx, val); -} - -template <class Impl> int AlphaFullCPU<Impl>::readIntrFlag() { @@ -277,16 +256,14 @@ template <class Impl> Fault AlphaFullCPU<Impl>::hwrei() { - uint64_t *ipr = getIpr(); - if (!inPalMode()) - return UnimplementedOpcodeFault; + return new UnimplementedOpcodeFault; - this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); + this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); // kernelStats.hwrei(); - if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) + if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) // AlphaISA::swap_palshadow(®s, false); this->checkInterrupts = true; @@ -329,31 +306,32 @@ AlphaFullCPU<Impl>::trap(Fault fault) // miss uint64_t PC = this->commit.readCommitPC(); - DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name"); - this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name")); + DPRINTF(Fault, "Fault %s\n", fault->name()); + this->recordEvent(csprintf("Fault %s", fault->name())); -// kernelStats.fault(fault); + //kernelStats.fault(fault); - if (fault == ArithmeticFault) + if (fault->isA<ArithmeticFault>()) panic("Arithmetic traps are unimplemented!"); - AlphaISA::InternalProcReg *ipr = getIpr(); - // exception restart address - Get the commit PC - if (fault != InterruptFault || !inPalMode(PC)) - ipr[AlphaISA::IPR_EXC_ADDR] = PC; + if (!fault->isA<InterruptFault>() || !inPalMode(PC)) + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); - if (fault == PalFault || fault == ArithmeticFault /* || + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || fault == InterruptFault && !PC_PAL(regs.pc) */) { // traps... skip faulting instruction - ipr[AlphaISA::IPR_EXC_ADDR] += 4; + AlphaISA::MiscReg ipr_exc_addr = + this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); + this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, + ipr_exc_addr + 4); } if (!inPalMode(PC)) swapPALShadow(true); - this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] + - AlphaISA::fault_addr(fault) ); + this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); this->regFile.setNextPC(PC + sizeof(MachInst)); } diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index f282c287c..e7f7d3a57 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -54,6 +54,8 @@ class AlphaDynInst : public BaseDynInst<Impl> typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ typedef TheISA::IntReg IntReg; + /** Misc register index type. */ + typedef TheISA::MiscReg MiscReg; enum { MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs @@ -75,15 +77,35 @@ class AlphaDynInst : public BaseDynInst<Impl> } public: - uint64_t readUniq(); - void setUniq(uint64_t val); + MiscReg readMiscReg(int misc_reg) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } + + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return 0; + } - uint64_t readFpcr(); - void setFpcr(uint64_t val); + Fault setMiscReg(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } + + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + { + // Dummy function for now. + // @todo: Fix this once reg file gets fixed. + return NoFault; + } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); Fault hwrei(); int readIntrFlag(); void setIntrFlag(int val); diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh index eebe7675a..96b7d3430 100644 --- a/cpu/o3/alpha_dyn_inst_impl.hh +++ b/cpu/o3/alpha_dyn_inst_impl.hh @@ -67,50 +67,8 @@ AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst) } } -template <class Impl> -uint64_t -AlphaDynInst<Impl>::readUniq() -{ - return this->cpu->readUniq(); -} - -template <class Impl> -void -AlphaDynInst<Impl>::setUniq(uint64_t val) -{ - this->cpu->setUniq(val); -} - -template <class Impl> -uint64_t -AlphaDynInst<Impl>::readFpcr() -{ - return this->cpu->readFpcr(); -} - -template <class Impl> -void -AlphaDynInst<Impl>::setFpcr(uint64_t val) -{ - this->cpu->setFpcr(val); -} - #if FULL_SYSTEM template <class Impl> -uint64_t -AlphaDynInst<Impl>::readIpr(int idx, Fault &fault) -{ - return this->cpu->readIpr(idx, fault); -} - -template <class Impl> -Fault -AlphaDynInst<Impl>::setIpr(int idx, uint64_t val) -{ - return this->cpu->setIpr(idx, val); -} - -template <class Impl> Fault AlphaDynInst<Impl>::hwrei() { diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index 0a77b83dc..2725684f7 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -30,7 +30,7 @@ #define __BPRED_UNIT_HH__ // For Addr type. -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index e4de1d304..c74c77ddf 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -31,7 +31,7 @@ #include <vector> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 706657887..a8c620028 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -264,13 +264,13 @@ FullO3CPU<Impl>::init() regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i]; regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i]; } - +/* // Then loop through the misc registers. regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr; regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq; regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag; regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; - +*/ // Then finally set the PC and the next PC. regFile.pc = src_xc->regs.pc; regFile.npc = src_xc->regs.npc; diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 321d61dce..02908887e 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include "sim/process.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" using namespace EV5; #endif @@ -152,11 +152,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); } + { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); } + { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ee7b8858e..691a75382 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -31,14 +31,14 @@ // @todo: Destructor -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/faults.hh" +#include "arch/isa_traits.hh" +#include "arch/faults.hh" #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/alpha/ev5.hh" +#include "arch/ev5.hh" #include "kern/kernel_stats.hh" using namespace EV5; @@ -56,6 +56,8 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::MiscRegFile MiscRegFile; + typedef TheISA::MiscReg MiscReg; + //Note that most of the definitions of the IntReg, FloatReg, etc. exist //within the Impl/ISA class and not within this PhysRegFile class. @@ -194,30 +196,21 @@ class PhysRegFile //Consider leaving this stuff and below in some implementation specific //file as opposed to the general register file. Or have a derived class. - uint64_t readUniq() - { - return miscRegs.uniq; - } - - void setUniq(uint64_t val) - { - miscRegs.uniq = val; - } - - uint64_t readFpcr() + MiscReg readMiscReg(int misc_reg) { - return miscRegs.fpcr; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return 0; } - void setFpcr(uint64_t val) + Fault setMiscReg(int misc_reg, const MiscReg &val) { - miscRegs.fpcr = val; + // Dummy function for now. + // @todo: Fix this once proxy XC is used. + return NoFault; } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault); - Fault setIpr(int idx, uint64_t val); - InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } #endif @@ -272,368 +265,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, memset(floatRegFile, 0, sizeof(*floatRegFile)); } -#if FULL_SYSTEM - -//Problem: This code doesn't make sense at the RegFile level because it -//needs things such as the itb and dtb. Either put it at the CPU level or -//the DynInst level. -template <class Impl> -uint64_t -PhysRegFile<Impl>::readIpr(int idx, Fault &fault) -{ - uint64_t retval = 0; // return value, default 0 - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PALtemp23: - case TheISA::IPR_PAL_BASE: - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - case TheISA::IPR_ISR: - case TheISA::IPR_EXC_ADDR: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_MCSR: - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - case TheISA::IPR_SIRR: - case TheISA::IPR_ICSR: - case TheISA::IPR_ICM: - case TheISA::IPR_DTB_CM: - case TheISA::IPR_IPLR: - case TheISA::IPR_INTID: - case TheISA::IPR_PMCTR: - // no side-effect - retval = ipr[idx]; - break; - - case TheISA::IPR_CC: - retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= curTick & ULL(0x00000000ffffffff); - break; - - case TheISA::IPR_VA: - retval = ipr[idx]; - break; - - case TheISA::IPR_VA_FORM: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_IFAULT_VA_FORM: - case TheISA::IPR_EXC_MASK: - case TheISA::IPR_EXC_SUM: - retval = ipr[idx]; - break; - - case TheISA::IPR_DTB_PTE: - { - TheISA::PTE &pte = cpu->dtb->index(1); - - retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; - retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; - retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; - retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; - retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; - retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; - retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; - } - break; - - // write only registers - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - case TheISA::IPR_ALT_MODE: - case TheISA::IPR_DTB_IA: - case TheISA::IPR_DTB_IAP: - case TheISA::IPR_ITB_IA: - case TheISA::IPR_ITB_IAP: - fault = UnimplementedOpcodeFault; - break; - - default: - // invalid IPR - fault = UnimplementedOpcodeFault; - break; - } - - return retval; -} - -extern int break_ipl; - -template <class Impl> -Fault -PhysRegFile<Impl>::setIpr(int idx, uint64_t val) -{ - uint64_t old; - - switch (idx) { - case TheISA::IPR_PALtemp0: - case TheISA::IPR_PALtemp1: - case TheISA::IPR_PALtemp2: - case TheISA::IPR_PALtemp3: - case TheISA::IPR_PALtemp4: - case TheISA::IPR_PALtemp5: - case TheISA::IPR_PALtemp6: - case TheISA::IPR_PALtemp7: - case TheISA::IPR_PALtemp8: - case TheISA::IPR_PALtemp9: - case TheISA::IPR_PALtemp10: - case TheISA::IPR_PALtemp11: - case TheISA::IPR_PALtemp12: - case TheISA::IPR_PALtemp13: - case TheISA::IPR_PALtemp14: - case TheISA::IPR_PALtemp15: - case TheISA::IPR_PALtemp16: - case TheISA::IPR_PALtemp17: - case TheISA::IPR_PALtemp18: - case TheISA::IPR_PALtemp19: - case TheISA::IPR_PALtemp20: - case TheISA::IPR_PALtemp21: - case TheISA::IPR_PALtemp22: - case TheISA::IPR_PAL_BASE: - case TheISA::IPR_IC_PERR_STAT: - case TheISA::IPR_DC_PERR_STAT: - case TheISA::IPR_PMCTR: - // write entire quad w/ no side-effect - ipr[idx] = val; - break; - - case TheISA::IPR_CC_CTL: - // This IPR resets the cycle counter. We assume this only - // happens once... let's verify that. - assert(ipr[idx] == 0); - ipr[idx] = 1; - break; - - case TheISA::IPR_CC: - // This IPR only writes the upper 64 bits. It's ok to write - // all 64 here since we mask out the lower 32 in rpcc (see - // isa_desc). - ipr[idx] = val; - break; - - case TheISA::IPR_PALtemp23: - // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_PTE: - // write entire quad w/ no side-effect, tag is forthcoming - ipr[idx] = val; - break; - - case TheISA::IPR_EXC_ADDR: - // second least significant bit in PC is always zero - ipr[idx] = val & ~2; - break; - - case TheISA::IPR_ASTRR: - case TheISA::IPR_ASTER: - // only write least significant four bits - privilege mask - ipr[idx] = val & 0xf; - break; - - case TheISA::IPR_IPLR: - // only write least significant five bits - interrupt level - ipr[idx] = val & 0x1f; - break; - - case TheISA::IPR_DTB_CM: - - case TheISA::IPR_ICM: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_ALT_MODE: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case TheISA::IPR_MCSR: - // more here after optimization... - ipr[idx] = val; - break; - - case TheISA::IPR_SIRR: - // only write software interrupt mask - ipr[idx] = val & 0x7fff0; - break; - - case TheISA::IPR_ICSR: - ipr[idx] = val & ULL(0xffffff0300); - break; - - case TheISA::IPR_IVPTBR: - case TheISA::IPR_MVPTBR: - ipr[idx] = val & ULL(0xffffffffc0000000); - break; - - case TheISA::IPR_DC_TEST_CTL: - ipr[idx] = val & 0x1ffb; - break; - - case TheISA::IPR_DC_MODE: - case TheISA::IPR_MAF_MODE: - ipr[idx] = val & 0x3f; - break; - - case TheISA::IPR_ITB_ASN: - ipr[idx] = val & 0x7f0; - break; - - case TheISA::IPR_DTB_ASN: - ipr[idx] = val & ULL(0xfe00000000000000); - break; - - case TheISA::IPR_EXC_SUM: - case TheISA::IPR_EXC_MASK: - // any write to this register clears it - ipr[idx] = 0; - break; - - case TheISA::IPR_INTID: - case TheISA::IPR_SL_RCV: - case TheISA::IPR_MM_STAT: - case TheISA::IPR_ITB_PTE_TEMP: - case TheISA::IPR_DTB_PTE_TEMP: - // read-only registers - return UnimplementedOpcodeFault; - - case TheISA::IPR_HWINT_CLR: - case TheISA::IPR_SL_XMIT: - case TheISA::IPR_DC_FLUSH: - case TheISA::IPR_IC_FLUSH: - // the following are write only - ipr[idx] = val; - break; - - case TheISA::IPR_DTB_IA: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushAll(); - break; - - case TheISA::IPR_DTB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->dtb->flushProcesses(); - break; - - case TheISA::IPR_DTB_IS: - // really a control write - ipr[idx] = val; - - cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN])); - break; - - case TheISA::IPR_DTB_TAG: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->dtb->insert(val, pte); - } - break; - - case TheISA::IPR_ITB_PTE: { - struct TheISA::PTE pte; - - // FIXME: granularity hints NYI... - if (ITB_PTE_GH(val) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = ITB_PTE_PPN(val); - pte.xre = ITB_PTE_XRE(val); - pte.xwe = 0; - pte.fonr = ITB_PTE_FONR(val); - pte.fonw = ITB_PTE_FONW(val); - pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]); - - // insert new TAG/PTE value into data TLB - cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte); - } - break; - - case TheISA::IPR_ITB_IA: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushAll(); - break; - - case TheISA::IPR_ITB_IAP: - // really a control write - ipr[idx] = 0; - - cpu->itb->flushProcesses(); - break; - - case TheISA::IPR_ITB_IS: - // really a control write - ipr[idx] = val; - - cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN])); - break; - - default: - // invalid IPR - return UnimplementedOpcodeFault; - } - - // no error... - return NoFault; -} - -#endif // #if FULL_SYSTEM - #endif // __CPU_O3_CPU_REGFILE_HH__ diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 009a81b98..e7ed3cfe0 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -29,7 +29,7 @@ #ifndef __CPU_OOO_CPU_OOO_IMPL_HH__ #define __CPU_OOO_CPU_OOO_IMPL_HH__ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" template <class Impl> class OoOCPU; diff --git a/cpu/ozone/ea_list.cc b/cpu/ozone/ea_list.cc index 80cf80fb8..6114a0ca1 100644 --- a/cpu/ozone/ea_list.cc +++ b/cpu/ozone/ea_list.cc @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "cpu/ooo_cpu/ea_list.hh" diff --git a/cpu/ozone/ea_list.hh b/cpu/ozone/ea_list.hh index def7e67d5..c0eee4bb8 100644 --- a/cpu/ozone/ea_list.hh +++ b/cpu/ozone/ea_list.hh @@ -32,7 +32,7 @@ #include <list> #include <utility> -#include "arch/alpha/isa_traits.hh" +#include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" /** diff --git a/cpu/profile.hh b/cpu/profile.hh index 18061f9bf..1eb012a27 100644 --- a/cpu/profile.hh +++ b/cpu/profile.hh @@ -33,7 +33,7 @@ #include "cpu/static_inst.hh" #include "sim/host.hh" -#include "targetarch/stacktrace.hh" +#include "arch/stacktrace.hh" class ProfileNode { diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 944bdbb0a..ca5d54694 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -67,9 +67,9 @@ #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" #include "sim/system.hh" -#include "targetarch/alpha_memory.hh" -#include "targetarch/stacktrace.hh" -#include "targetarch/vtophys.hh" +#include "arch/tlb.hh" +#include "arch/stacktrace.hh" +#include "arch/vtophys.hh" #else // !FULL_SYSTEM #include "mem/functional/functional.hh" #endif // FULL_SYSTEM @@ -347,12 +347,12 @@ SimpleCPU::copySrcTranslate(Addr src) // translate to physical address Fault fault = xc->translateDataReadReq(memReq); - assert(fault != AlignmentFault); - if (fault == NoFault) { xc->copySrcAddr = src; xc->copySrcPhysAddr = memReq->paddr + offset; } else { + assert(!fault->isAlignmentFault()); + xc->copySrcAddr = 0; xc->copySrcPhysAddr = 0; } @@ -382,8 +382,6 @@ SimpleCPU::copy(Addr dest) // translate to physical address Fault fault = xc->translateDataWriteReq(memReq); - assert(fault != AlignmentFault); - if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. @@ -402,6 +400,9 @@ SimpleCPU::copy(Addr dest) dcacheInterface->access(memReq); } } + else + assert(!fault->isAlignmentFault()); + return fault; } @@ -659,12 +660,11 @@ SimpleCPU::tick() int ipl = 0; int summary = 0; checkInterrupts = false; - IntReg *ipr = xc->regs.ipr; - if (xc->regs.ipr[IPR_SIRR]) { + if (xc->readMiscReg(IPR_SIRR)) { for (int i = INTLEVEL_SOFTWARE_MIN; i < INTLEVEL_SOFTWARE_MAX; i++) { - if (ipr[IPR_SIRR] & (ULL(1) << i)) { + if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { // See table 4-19 of 21164 hardware reference ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; summary |= (ULL(1) << i); @@ -682,16 +682,16 @@ SimpleCPU::tick() } } - if (ipr[IPR_ASTRR]) + if (xc->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); - if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) { - ipr[IPR_ISR] = summary; - ipr[IPR_INTID] = ipl; - xc->ev5_trap(InterruptFault); + if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { + xc->setMiscReg(IPR_ISR, summary); + xc->setMiscReg(IPR_INTID, ipl); + (new InterruptFault)->ev5_trap(xc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - ipr[IPR_IPLR], ipl, summary); + xc->readMiscReg(IPR_IPLR), ipl, summary); } } #endif @@ -782,7 +782,7 @@ SimpleCPU::tick() } if (xc->profile) { - bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0; + bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; xc->profilePC = usermode ? 1 : xc->regs.pc; ProfileNode *node = xc->profile->consume(xc, inst); if (node) @@ -812,7 +812,7 @@ SimpleCPU::tick() if (fault != NoFault) { #if FULL_SYSTEM - xc->ev5_trap(fault); + fault->ev5_trap(xc); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); #endif // FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index ed7b1e29b..243172821 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU { protected: typedef TheISA::MachInst MachInst; + typedef TheISA::MiscReg MiscReg; public: // main simulation loop (one cycle) void tick(); @@ -321,20 +322,32 @@ class SimpleCPU : public BaseCPU uint64_t readPC() { return xc->readPC(); } void setNextPC(uint64_t val) { xc->setNextPC(val); } - uint64_t readUniq() { return xc->readUniq(); } - void setUniq(uint64_t val) { xc->setUniq(val); } + MiscReg readMiscReg(int misc_reg) + { + return xc->readMiscReg(misc_reg); + } + + MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + { + return xc->readMiscRegWithEffect(misc_reg, fault); + } - uint64_t readFpcr() { return xc->readFpcr(); } - void setFpcr(uint64_t val) { xc->setFpcr(val); } + Fault setMiscReg(int misc_reg, const MiscReg &val) + { + return xc->setMiscReg(misc_reg, val); + } + + Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + { + return xc->setMiscRegWithEffect(misc_reg, val); + } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } - Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } Fault hwrei() { return xc->hwrei(); } int readIntrFlag() { return xc->readIntrFlag(); } void setIntrFlag(int val) { xc->setIntrFlag(val); } bool inPalMode() { return xc->inPalMode(); } - void ev5_trap(Fault fault) { xc->ev5_trap(fault); } + void ev5_trap(Fault fault) { fault->ev5_trap(xc); } bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } #else void syscall() { xc->syscall(); } diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index a0287a2de..5566f2f6d 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -109,6 +109,8 @@ class StaticInstBase : public RefCounted IsCall, ///< Subroutine call. IsReturn, ///< Subroutine return. + IsCondDelaySlot,///< Conditional Delay-Slot Instruction + IsThreadSync, ///< Thread synchronization operation. IsSerializing, ///< Serializes pipeline: won't execute until all diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 94f834b4f..6ca5e3a06 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) } break; default: - return MachineCheckFault; + return genMachineCheckFault(); } return NoFault; @@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) val = *(uint64_t *)data; break; default: - return MachineCheckFault; + return genMachineCheckFault(); } Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 4b08d8497..ed8c794f9 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -49,7 +49,7 @@ #include "sim/debug.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" const char *NsRxStateStrings[] = { @@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) reg |= M5REG_RX_THREAD; if (params()->tx_thread) reg |= M5REG_TX_THREAD; + if (params()->rss) + reg |= M5REG_RSS; break; default: @@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cdd8e4b9e..59c55056e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -385,6 +385,7 @@ class NSGigE : public PciDev uint32_t rx_fifo_size; bool rx_thread; bool tx_thread; + bool rss; bool dma_no_allocate; }; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index eadc60d03..5f6fa2cc5 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -306,6 +306,7 @@ /* M5 control register */ #define M5REG_RESERVED 0xfffffffc +#define M5REG_RSS 0x00000004 #define M5REG_RX_THREAD 0x00000002 #define M5REG_TX_THREAD 0x00000001 diff --git a/dev/pcidev.hh b/dev/pcidev.hh index 9427463bf..bdfc6b932 100644 --- a/dev/pcidev.hh +++ b/dev/pcidev.hh @@ -260,6 +260,7 @@ class PciDev : public DmaDevice inline Fault PciDev::readBar(MemReqPtr &req, uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return readBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data) return readBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return readBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } inline Fault PciDev::writeBar(MemReqPtr &req, const uint8_t *data) { + using namespace TheISA; if (isBAR(req->paddr, 0)) return writeBar0(req, req->paddr - BARAddrs[0], data); if (isBAR(req->paddr, 1)) @@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data) return writeBar4(req, req->paddr - BARAddrs[4], data); if (isBAR(req->paddr, 5)) return writeBar5(req, req->paddr - BARAddrs[5], data); - return MachineCheckFault; + return genMachineCheckFault(); } #endif // __DEV_PCIDEV_HH__ diff --git a/dev/pktfifo.cc b/dev/pktfifo.cc index b4fab2d6f..639009be9 100644 --- a/dev/pktfifo.cc +++ b/dev/pktfifo.cc @@ -31,6 +31,36 @@ using namespace std; +bool +PacketFifo::copyout(void *dest, int offset, int len) +{ + char *data = (char *)dest; + if (offset + len >= size()) + return false; + + list<PacketPtr>::iterator p = fifo.begin(); + list<PacketPtr>::iterator end = fifo.end(); + while (len > 0) { + while (offset >= (*p)->length) { + offset -= (*p)->length; + ++p; + } + + if (p == end) + panic("invalid fifo"); + + int size = min((*p)->length - offset, len); + memcpy(data, (*p)->data, size); + offset = 0; + len -= size; + data += size; + ++p; + } + + return true; +} + + void PacketFifo::serialize(const string &base, ostream &os) { @@ -40,8 +70,8 @@ PacketFifo::serialize(const string &base, ostream &os) paramOut(os, base + ".packets", fifo.size()); int i = 0; - std::list<PacketPtr>::iterator p = fifo.begin(); - std::list<PacketPtr>::iterator end = fifo.end(); + list<PacketPtr>::iterator p = fifo.begin(); + list<PacketPtr>::iterator end = fifo.end(); while (p != end) { (*p)->serialize(csprintf("%s.packet%d", base, i), os); ++p; diff --git a/dev/pktfifo.hh b/dev/pktfifo.hh index e63fd291f..e245840a8 100644 --- a/dev/pktfifo.hh +++ b/dev/pktfifo.hh @@ -127,6 +127,35 @@ class PacketFifo fifo.erase(i); } + bool copyout(void *dest, int offset, int len); + + int countPacketsBefore(iterator end) + { + iterator i = fifo.begin(); + int count = 0; + + while (i != end) { + ++count; + ++i; + } + + return count; + } + + int countPacketsAfter(iterator i) + { + iterator end = fifo.end(); + int count = 0; + + while (i != end) { + ++count; + ++i; + } + + return count; + } + + /** * Serialization stuff */ diff --git a/dev/sinic.cc b/dev/sinic.cc index c499d2f49..363994919 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -47,7 +47,7 @@ #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/stats.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace Net; using namespace TheISA; @@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = readBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -376,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data) Fault Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data) assert(config.command & PCI_CMD_MSE); Fault fault = writeBar(req, data); - if (fault == MachineCheckFault) { + if (fault->isMachineCheckFault()) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return MachineCheckFault; + return genMachineCheckFault(); } return fault; @@ -472,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data) Fault Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { - int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; + int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -489,30 +489,17 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d", info.name, cpu, daddr, req->paddr, req->vaddr, req->size); - //uint32_t reg32 = *(uint32_t *)data; + uint32_t reg32 = *(uint32_t *)data; uint64_t reg64 = *(uint64_t *)data; + VirtualReg &vnic = virtualRegs[index]; + DPRINTF(EthernetPIO, "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n", - info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr, - req->paddr, req->vaddr, req->size); + info.name, cpu, info.size == 4 ? reg32 : reg64, + daddr, req->paddr, req->vaddr, req->size); prepareWrite(cpu, index); - regWrite(daddr, cpu, data); - - return NoFault; -} - -void -Device::regWrite(Addr daddr, int cpu, const uint8_t *data) -{ - Addr index = daddr >> Regs::VirtualShift; - Addr raddr = daddr & Regs::VirtualMask; - - uint32_t reg32 = *(uint32_t *)data; - uint64_t reg64 = *(uint64_t *)data; - VirtualReg &vnic = virtualRegs[index]; - switch (raddr) { case Regs::Config: changeConfig(reg32); @@ -559,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data) } break; } + + return NoFault; } void @@ -772,6 +761,8 @@ Device::reset() regs.Config |= Config_RxThread; if (params()->tx_thread) regs.Config |= Config_TxThread; + if (params()->rss) + regs.Config |= Config_RSS; regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; regs.RxMaxCopy = params()->rx_max_copy; regs.TxMaxCopy = params()->tx_max_copy; @@ -1635,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(Device) @@ -1677,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(Device) @@ -1725,6 +1718,7 @@ CREATE_SIM_OBJECT(Device) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new Device(params); } diff --git a/dev/sinic.hh b/dev/sinic.hh index 97ebf4c30..25172fa45 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -280,7 +280,6 @@ class Device : public Base Fault iprRead(Addr daddr, int cpu, uint64_t &result); Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); /** @@ -356,6 +355,7 @@ class Device : public Base bool dma_no_allocate; bool rx_thread; bool tx_thread; + bool rss; }; protected: diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index fc1f4c06b..f90432398 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address __SINIC_REG32(Size, 0x68); // register addres space size // Config register bits +__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling __SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads __SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread __SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter diff --git a/kern/freebsd/freebsd_system.cc b/kern/freebsd/freebsd_system.cc index a9052081a..7ba385267 100644 --- a/kern/freebsd/freebsd_system.cc +++ b/kern/freebsd/freebsd_system.cc @@ -42,7 +42,7 @@ #include "sim/builder.hh" #include "arch/isa_traits.hh" #include "sim/byteswap.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #define TIMER_FREQUENCY 1193180 diff --git a/kern/kernel_stats.cc b/kern/kernel_stats.cc index 6d2f2a774..33485ca15 100644 --- a/kern/kernel_stats.cc +++ b/kern/kernel_stats.cc @@ -136,7 +136,7 @@ Statistics::regStats(const string &_name) } } - _faults +/* _faults .init(NumFaults) .name(name() + ".faults") .desc("number of faults") @@ -147,7 +147,7 @@ Statistics::regStats(const string &_name) const char *str = (*ListOfFaults[i])->name; if (str) _faults.subname(i, str); - } + }*/ _mode .init(cpu_mode_num) @@ -240,7 +240,7 @@ Statistics::swpipl(int ipl) void Statistics::mode(cpu_mode newmode) { - Addr pcbb = xc->regs.ipr[AlphaISA::IPR_PALtemp23]; + Addr pcbb = xc->readMiscReg(AlphaISA::IPR_PALtemp23); if ((newmode == kernel || newmode == interrupt) && pcbb == idleProcess) diff --git a/kern/kernel_stats.hh b/kern/kernel_stats.hh index 02d78e4d9..4896a0705 100644 --- a/kern/kernel_stats.hh +++ b/kern/kernel_stats.hh @@ -151,7 +151,7 @@ class Statistics : public Serializable Stats::Vector<> _callpal; Stats::Vector<> _syscall; - Stats::Vector<> _faults; +// Stats::Vector<> _faults; Stats::Vector<> _mode; Stats::Vector<> _modeGood; @@ -178,10 +178,8 @@ class Statistics : public Serializable void hwrei() { _hwrei++; } void fault(Fault fault) { - if(fault == NoFault) _faults[0]++; - else if(fault == MachineCheckFault) _faults[2]++; - else if(fault == AlignmentFault) _faults[7]++; - else _faults[fault->id]++; + if(fault != NoFault) + fault->stat()++; }// FIXME: When there are no generic system fault objects, this will go back to _faults[fault]++; } void swpipl(int ipl); void mode(cpu_mode newmode); diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc index db13da0ec..d7ec8a327 100644 --- a/kern/linux/linux_system.cc +++ b/kern/linux/linux_system.cc @@ -47,8 +47,8 @@ #include "sim/builder.hh" #include "sim/byteswap.hh" #include "dev/platform.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" +#include "arch/arguments.hh" +#include "arch/vtophys.hh" using namespace std; using namespace TheISA; diff --git a/kern/linux/printk.cc b/kern/linux/printk.cc index fbc8bdad1..f5313759b 100644 --- a/kern/linux/printk.cc +++ b/kern/linux/printk.cc @@ -30,7 +30,7 @@ #include <algorithm> #include "base/trace.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" using namespace std; diff --git a/kern/system_events.cc b/kern/system_events.cc index 55595b9b6..91625e60a 100644 --- a/kern/system_events.cc +++ b/kern/system_events.cc @@ -67,7 +67,7 @@ FnEvent::process(ExecContext *xc) void IdleStartEvent::process(ExecContext *xc) { - xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]); + xc->kernelStats->setIdleProcess(xc->readMiscReg(AlphaISA::IPR_PALtemp23)); remove(); } diff --git a/kern/tru64/dump_mbuf.cc b/kern/tru64/dump_mbuf.cc index efdaed62d..10137ceb0 100644 --- a/kern/tru64/dump_mbuf.cc +++ b/kern/tru64/dump_mbuf.cc @@ -34,9 +34,9 @@ #include "cpu/exec_context.hh" #include "kern/tru64/mbuf.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace TheISA; diff --git a/kern/tru64/printf.cc b/kern/tru64/printf.cc index 12a089c40..77ac17c3a 100644 --- a/kern/tru64/printf.cc +++ b/kern/tru64/printf.cc @@ -32,8 +32,8 @@ #include "base/cprintf.hh" #include "base/trace.hh" #include "sim/host.hh" -#include "targetarch/arguments.hh" -#include "targetarch/vtophys.hh" +#include "arch/arguments.hh" +#include "arch/vtophys.hh" using namespace std; diff --git a/kern/tru64/tru64.hh b/kern/tru64/tru64.hh index 1579a54d8..ad568cb0c 100644 --- a/kern/tru64/tru64.hh +++ b/kern/tru64/tru64.hh @@ -729,7 +729,7 @@ class Tru64 { regs->floatRegFile.q[i] = htog(sc->sc_fpregs[i]); } - regs->miscRegs.fpcr = htog(sc->sc_fpcr); + xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr)); return 0; } @@ -889,7 +889,7 @@ class Tru64 { ssp->nxm_sysevent = htog(0); if (i == 0) { - uint64_t uniq = xc->regs.miscRegs.uniq; + uint64_t uniq = xc->readMiscReg(TheISA::Uniq_DepTag); ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset)); ssp->nxm_u.nxm_active = htog(uniq | 1); } @@ -924,7 +924,7 @@ class Tru64 { ec->regs.intRegFile[TheISA::ArgumentReg0] = gtoh(attrp->registers.a0); ec->regs.intRegFile[27/*t12*/] = gtoh(attrp->registers.pc); ec->regs.intRegFile[TheISA::StackPointerReg] = gtoh(attrp->registers.sp); - ec->regs.miscRegs.uniq = uniq_val; + ec->setMiscReg(TheISA::Uniq_DepTag, uniq_val); ec->regs.pc = gtoh(attrp->registers.pc); ec->regs.npc = gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst); diff --git a/kern/tru64/tru64_events.cc b/kern/tru64/tru64_events.cc index 2fe6a2dc4..1fd26b87b 100644 --- a/kern/tru64/tru64_events.cc +++ b/kern/tru64/tru64_events.cc @@ -33,7 +33,7 @@ #include "kern/tru64/dump_mbuf.hh" #include "kern/tru64/printf.hh" #include "mem/functional/memory_control.hh" -#include "targetarch/arguments.hh" +#include "arch/arguments.hh" #include "arch/isa_traits.hh" using namespace TheISA; diff --git a/kern/tru64/tru64_system.cc b/kern/tru64/tru64_system.cc index 8337d38db..aa78e8de6 100644 --- a/kern/tru64/tru64_system.cc +++ b/kern/tru64/tru64_system.cc @@ -37,7 +37,7 @@ #include "mem/functional/physical.hh" #include "sim/builder.hh" #include "arch/isa_traits.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" using namespace std; diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 3a7f88d04..6113e656f 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -86,6 +86,7 @@ class EtherDevBase(PciDevice): intr_delay = Param.Latency('10us', "Interrupt propagation delay") rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") tx_thread = Param.Bool(False, "dedicated kernel threads for receive") + rss = Param.Bool(False, "Receive Side Scaling") class NSGigE(EtherDevBase): type = 'NSGigE' diff --git a/sim/faults.cc b/sim/faults.cc index 58a631263..78bfc8092 100644 --- a/sim/faults.cc +++ b/sim/faults.cc @@ -28,9 +28,6 @@ #include "sim/faults.hh" -NoFaultType * const NoFault = new NoFaultType("none"); -MachineCheckFaultType * const MachineCheckFault = - new MachineCheckFaultType("mchk"); -AlignmentFaultType * const AlignmentFault = - new AlignmentFaultType("unalign"); +FaultName MachineCheckFault::_name = "mchk"; +FaultName AlignmentFault::_name = "unalign"; diff --git a/sim/faults.hh b/sim/faults.hh index dbec399af..9b8c94cda 100644 --- a/sim/faults.hh +++ b/sim/faults.hh @@ -29,34 +29,63 @@ #ifndef __FAULTS_HH__ #define __FAULTS_HH__ +#include "base/refcnt.hh" +#include "sim/stats.hh" +#include "config/full_system.hh" + +class ExecContext; class FaultBase; -typedef FaultBase * Fault; +typedef RefCountingPtr<FaultBase> Fault; + +typedef const char * FaultName; +typedef Stats::Scalar<> FaultStat; -class FaultBase +// Each class has it's name statically define in _name, +// and has a virtual function to access it's name. +// The function is necessary because otherwise, all objects +// which are being accessed cast as a FaultBase * (namely +// all faults returned using the Fault type) will use the +// generic FaultBase name. + +class FaultBase : public RefCounted { -public: - FaultBase(char * newName, int newId = 0) : name(newName), id(newId) {;} - const char * name; - int id; + public: + virtual FaultName name() = 0; + virtual FaultStat & stat() = 0; +#if FULL_SYSTEM + virtual void ev5_trap(ExecContext * xc) = 0; +#endif + template<typename T> + bool isA() {return dynamic_cast<T *>(this);} + virtual bool isMachineCheckFault() {return false;} + virtual bool isAlignmentFault() {return false;} }; -extern class NoFaultType : public FaultBase -{ -public: - NoFaultType(char * newName) : FaultBase(newName) {;} -} * const NoFault; +FaultBase * const NoFault = 0; -extern class MachineCheckFaultType : public FaultBase +//The ISAs are each responsible for providing a genMachineCheckFault and a +//genAlignmentFault functions, which return faults to use in the case of a +//machine check fault or an alignment fault, respectively. Base classes which +//provide the name() function, and the isMachineCheckFault and isAlignmentFault +//functions are provided below. + +class MachineCheckFault : public virtual FaultBase { -public: - MachineCheckFaultType(char * newName) : FaultBase(newName) {;} -} * const MachineCheckFault; + private: + static FaultName _name; + public: + FaultName name() {return _name;} + bool isMachineCheckFault() {return true;} +}; -extern class AlignmentFaultType : public FaultBase +class AlignmentFault : public virtual FaultBase { -public: - AlignmentFaultType(char * newName) : FaultBase(newName) {;} -} * const AlignmentFault; + private: + static FaultName _name; + public: + FaultName name() {return _name;} + bool isAlignmentFault() {return true;} +}; #endif // __FAULTS_HH__ diff --git a/sim/process.cc b/sim/process.cc index 0a7e46082..e3cae2855 100644 --- a/sim/process.cc +++ b/sim/process.cc @@ -48,10 +48,8 @@ #include "sim/stats.hh" #include "sim/syscall_emul.hh" -#ifdef TARGET_ALPHA -#include "arch/alpha/alpha_tru64_process.hh" -#include "arch/alpha/alpha_linux_process.hh" -#endif +#include "arch/tru64_process.hh" +#include "arch/linux_process.hh" using namespace std; using namespace TheISA; diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc index 0250352f4..f4285be8a 100644 --- a/sim/pseudo_inst.cc +++ b/sim/pseudo_inst.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ #include <string> #include "sim/pseudo_inst.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "cpu/base.hh" #include "cpu/sampler/sampler.hh" #include "cpu/exec_context.hh" @@ -78,6 +78,42 @@ namespace AlphaPseudo } void + quiesceNs(ExecContext *xc, uint64_t ns) + { + if (!doQuiesce || ns == 0) + return; + + if (xc->quiesceEvent.scheduled()) + xc->quiesceEvent.reschedule(curTick + Clock::Int::ns * ns); + else + xc->quiesceEvent.schedule(curTick + Clock::Int::ns * ns); + + xc->suspend(); + xc->kernelStats->quiesce(); + } + + void + quiesceCycles(ExecContext *xc, uint64_t cycles) + { + if (!doQuiesce || cycles == 0) + return; + + if (xc->quiesceEvent.scheduled()) + xc->quiesceEvent.reschedule(curTick + xc->cpu->cycles(cycles)); + else + xc->quiesceEvent.schedule(curTick + xc->cpu->cycles(cycles)); + + xc->suspend(); + xc->kernelStats->quiesce(); + } + + uint64_t + quiesceTime(ExecContext *xc) + { + return (xc->lastActivate - xc->lastSuspend) / Clock::Int::ns ; + } + + void ivlb(ExecContext *xc) { xc->kernelStats->ivlb(); diff --git a/sim/pseudo_inst.hh b/sim/pseudo_inst.hh index 3857f2050..4dd427c99 100644 --- a/sim/pseudo_inst.hh +++ b/sim/pseudo_inst.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -44,6 +44,9 @@ namespace AlphaPseudo void arm(ExecContext *xc); void quiesce(ExecContext *xc); + void quiesceNs(ExecContext *xc, uint64_t ns); + void quiesceCycles(ExecContext *xc, uint64_t cycles); + uint64_t quiesceTime(ExecContext *xc); void ivlb(ExecContext *xc); void ivle(ExecContext *xc); void m5exit(ExecContext *xc, Tick delay); diff --git a/sim/system.cc b/sim/system.cc index e138a6c22..8820922c1 100644 --- a/sim/system.cc +++ b/sim/system.cc @@ -5,7 +5,7 @@ #include "kern/kernel_stats.hh" #include "mem/functional/memory_control.hh" #include "mem/functional/physical.hh" -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "sim/builder.hh" #include "arch/isa_traits.hh" #include "sim/byteswap.hh" diff --git a/sim/vptr.hh b/sim/vptr.hh index 7ec43602d..0ec452f25 100644 --- a/sim/vptr.hh +++ b/sim/vptr.hh @@ -29,7 +29,7 @@ #ifndef __ARCH_ALPHA_VPTR_HH__ #define __ARCH_ALPHA_VPTR_HH__ -#include "targetarch/vtophys.hh" +#include "arch/vtophys.hh" #include "arch/isa_traits.hh" class ExecContext; diff --git a/util/m5/Makefile b/util/m5/Makefile index 6e4ad31a3..518542322 100644 --- a/util/m5/Makefile +++ b/util/m5/Makefile @@ -1,26 +1,50 @@ -AS=as -CC=cc -LD=cc +# Copyright (c) 2005-2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -CCFLAGS=-O2 -#LDFLAGS=-non_shared +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld -all: m5 +CFLAGS=-O2 +OBJS=m5.o m5op.o -m5: m5op.o m5.o - $(LD) $(LDFLAGS) -o $@ $> - strip $@ +all: m5 -clean: - @rm -f m5 *.o *.d *~ .#* +%.o: %.S + $(CC) $(CFLAGS) -o $@ -c $< -.SUFFIXES: -.SUFFIXES:.o .c .s +%.o: %.c + $(CC) $(CFLAGS) -o $@ -c $< -# C Compilation -.c.o: - $(CC) $(CCFLAGS) -o $@ -c $< +m5: $(OBJS) + $(CC) -o $@ $(OBJS) -# Assembly -.s.o: - $(AS) $(ASFLAGS) -o $@ $< +clean: + rm -f *.o m5 diff --git a/util/m5/m5.c b/util/m5/m5.c index 942ad5ba4..6fdbc0500 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -73,7 +73,7 @@ main(int argc, char *argv[]) usage(); arg1 = strtoul(argv[2], NULL, 0); - ivlb(arg1); + m5_ivlb(arg1); return 0; } @@ -82,7 +82,7 @@ main(int argc, char *argv[]) usage(); arg1 = strtoul(argv[2], NULL, 0); - ivle(arg1); + m5_ivle(arg1); return 0; } @@ -90,7 +90,7 @@ main(int argc, char *argv[]) if (argc != 2) usage(); - printf("%ld", initparam()); + printf("%ld", m5_initparam()); return 0; } @@ -98,7 +98,7 @@ main(int argc, char *argv[]) if (argc != 2) usage(); - param = initparam(); + param = m5_initparam(); // run-time, rampup-time, rampdown-time, warmup-time, connections printf("%d %d %d %d %d", (param >> 48) & 0xfff, (param >> 36) & 0xfff, (param >> 24) & 0xfff, @@ -112,7 +112,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - m5exit(arg1); + m5_exit(arg1); return 0; default: @@ -127,7 +127,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - reset_stats(arg1, arg2); + m5_reset_stats(arg1, arg2); return 0; default: @@ -142,7 +142,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - dump_stats(arg1, arg2); + m5_dump_stats(arg1, arg2); return 0; default: @@ -157,7 +157,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - dumpreset_stats(arg1, arg2); + m5_dumpreset_stats(arg1, arg2); return 0; default: @@ -172,7 +172,7 @@ main(int argc, char *argv[]) case 3: arg1 = strtoul(argv[2], NULL, 0); case 2: - checkpoint(arg1, arg2); + m5_checkpoint(arg1, arg2); return 0; default: diff --git a/util/m5/m5op.S b/util/m5/m5op.S new file mode 100644 index 000000000..a53c45277 --- /dev/null +++ b/util/m5/m5op.S @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define m5_op 0x01 + +#define arm_func 0x00 +#define quiesce_func 0x01 +#define quiescens_func 0x02 +#define quiescecycle_func 0x03 +#define quiescetime_func 0x04 +#define ivlb_func 0x10 +#define ivle_func 0x11 +#define exit_old_func 0x20 // deprectated! +#define exit_func 0x21 +#define initparam_func 0x30 +#define resetstats_func 0x40 +#define dumpstats_func 0x41 +#define dumprststats_func 0x42 +#define ckpt_func 0x43 +#define readfile_func 0x50 +#define debugbreak_func 0x51 +#define switchcpu_func 0x52 +#define addsymbol_func 0x53 +#define panic_func 0x54 + +#define INST(op, ra, rb, func) \ + .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) + +#define LEAF(func) \ + .align 3; \ + .globl func; \ + .ent func; \ +func: + +#define RET \ + ret ($26) + +#define END(func) \ + .end func + +#define ARM(reg) INST(m5_op, reg, 0, arm_func) +#define QUIESCE INST(m5_op, 0, 0, quiesce_func) +#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) +#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) +#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) +#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func) +#define IVLE(reg) INST(m5_op, reg, 0, ivle_func) +#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) +#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) +#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) +#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) +#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) +#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) +#define READFILE INST(m5_op, 0, 0, readfile_func) +#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) +#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) +#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) +#define PANIC INST(m5_op, 0, 0, panic_func) + + .set noreorder + + .align 4 +LEAF(arm) + ARM(16) + RET +END(arm) + + .align 4 +LEAF(quiesce) + QUIESCE + RET +END(quiesce) + + .align 4 +LEAF(quiesceNs) + QUIESCENS(16) + RET +END(quiesceNs) + + .align 4 +LEAF(quiesceCycle) + QUIESCECYC(16) + RET +END(quiesceCycle) + + .align 4 +LEAF(quiesceTime) + QUIESCETIME + RET +END(quiesceTime) + + + .align 4 +LEAF(m5_ivlb) + IVLB(16) + RET +END(m5_ivlb) + + .align 4 +LEAF(m5_ivle) + IVLE(16) + RET +END(m5_ivle) + + .align 4 +LEAF(m5_exit) + M5EXIT(16) + RET +END(m5_exit) + + .align 4 +LEAF(m5_initparam) + INITPARAM(0) + RET +END(m5_initparam) + + .align 4 +LEAF(m5_reset_stats) + RESET_STATS(16, 17) + RET +END(m5_reset_stats) + + .align 4 +LEAF(m5_dump_stats) + DUMP_STATS(16, 17) + RET +END(m5_dump_stats) + + .align 4 +LEAF(m5_dumpreset_stats) + DUMPRST_STATS(16, 17) + RET +END(m5_dumpreset_stats) + + .align 4 +LEAF(m5_checkpoint) + CHECKPOINT(16, 17) + RET +END(m5_checkpoint) + + .align 4 +LEAF(m5_readfile) + READFILE + RET +END(m5_readfile) + + .align 4 +LEAF(m5_debugbreak) + DEBUGBREAK + RET +END(m5_debugbreak) + + .align 4 +LEAF(m5_switchcpu) + SWITCHCPU + RET +END(m5_switchcpu) + + .align 4 +LEAF(m5_addsymbol) + ADDSYMBOL(16, 17) + RET +END(m5_addsymbol) + + .align 4 +LEAF(m5_panic) + PANIC + RET +END(m5_panic) + + diff --git a/util/m5/m5op.h b/util/m5/m5op.h index 91dc4cc8b..34ac7760d 100644 --- a/util/m5/m5op.h +++ b/util/m5/m5op.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 2003-2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -29,17 +29,26 @@ #ifndef __M5OP_H__ #define __M5OP_H__ -#include <inttypes.h> +#include <asm/types.h> void arm(uint64_t address); -void quiesce(); -void ivlb(uint64_t interval); -void ivle(uint64_t interval); -void m5exit(uint64_t ns_delay); -uint64_t initparam(); -void checkpoint(uint64_t ns_delay, uint64_t ns_period); -void reset_stats(uint64_t ns_delay, uint64_t ns_period); -void dump_stats(uint64_t ns_delay, uint64_t ns_period); -void dumpreset_stats(uint64_t ns_delay, uint64_t ns_period); +void quiesce(void); +void quiesceNs(uint64_t ns); +void quiesceCycle(uint64_t cycles); +uint64_t quiesceTime(void); + +void m5_ivlb(uint64_t interval); +void m5_ivle(uint64_t interval); +void m5_exit(uint64_t ns_delay); +uint64_t m5_initparam(void); +void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period); +void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period); +void m5_dump_stats(uint64_t ns_delay, uint64_t ns_period); +void m5_dumpreset_stats(uint64_t ns_delay, uint64_t ns_period); +uint64_t m5_readfile(void *buffer, uint64_t len, uint64_t offset); +void m5_debugbreak(void); +void m5_switchcpu(void); +void m5_addsymbol(uint64_t addr, char *symbol); +void m5_panic(void); #endif // __M5OP_H__ diff --git a/util/m5/m5op.s b/util/m5/m5op.s deleted file mode 100644 index e779e4209..000000000 --- a/util/m5/m5op.s +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2003, 2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <machine/asm.h> -#include <regdef.h> - -#define m5_op 0x01 - -#define arm_func 0x00 -#define quiesce_func 0x01 -#define ivlb_func 0x10 -#define ivle_func 0x11 -#define exit_old_func 0x20 // deprectated! -#define exit_func 0x21 -#define initparam_func 0x30 -#define resetstats_func 0x40 -#define dumpstats_func 0x41 -#define dumprststats_func 0x42 -#define ckpt_func 0x43 - -#define INST(op, ra, rb, func) \ - .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) - -#define ARM(reg) INST(m5_op, reg, 0, arm_func) -#define QUIESCE() INST(m5_op, 0, 0, quiesce_func) -#define IVLB(reg) INST(m5_op, reg, 0, ivlb_func) -#define IVLE(reg) INST(m5_op, reg, 0, ivle_func) -#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) -#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) -#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) -#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) -#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) -#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) - - .set noreorder - - .align 4 -LEAF(arm) - ARM(16) - RET -END(arm) - - .align 4 -LEAF(quiesce) - QUIESCE() - RET -END(quiesce) - - .align 4 -LEAF(ivlb) - IVLB(16) - RET -END(ivlb) - - .align 4 -LEAF(ivle) - IVLE(16) - RET -END(ivle) - - .align 4 -LEAF(m5exit) - M5EXIT(16) - RET -END(m5exit) - - .align 4 -LEAF(initparam) - INITPARAM(0) - RET -END(initparam) - - .align 4 -LEAF(reset_stats) - RESET_STATS(16, 17) - RET -END(reset_stats) - - .align 4 -LEAF(dump_stats) - DUMP_STATS(16, 17) - RET -END(dump_stats) - - .align 4 -LEAF(dumpreset_stats) - DUMPRST_STATS(16, 17) - RET -END(dumpreset_stats) - - .align 4 -LEAF(checkpoint) - CHECKPOINT(16, 17) - RET -END(checkpoint) - diff --git a/util/stats/barchart.py b/util/stats/barchart.py index 3f202d9bf..5d6dd0ab1 100644 --- a/util/stats/barchart.py +++ b/util/stats/barchart.py @@ -42,13 +42,18 @@ class BarChart(ChartOptions): super(BarChart, self).__init__(default, **kwargs) self.inputdata = None self.chartdata = None + self.inputerr = None + self.charterr = None def gen_colors(self, count): cmap = matplotlib.cm.get_cmap(self.colormap) if count == 1: return cmap([ 0.5 ]) - else: - return cmap(arange(count) / float(count - 1)) + + if count < 5: + return cmap(arange(5) / float(4))[:count] + + return cmap(arange(count) / float(count - 1)) # The input data format does not match the data format that the # graph function takes because it is intuitive. The conversion @@ -89,6 +94,32 @@ class BarChart(ChartOptions): data = property(get_data, set_data) + def set_err(self, err): + if err is None: + self.inputerr = None + self.charterr = None + return + + err = array(err) + dim = len(shape(err)) + if dim not in (1, 2, 3): + raise AttributeError, "Input err must be a 1, 2, or 3d matrix" + self.inputerr = err + + if dim == 1: + self.charterr = array([[err]]) + + if dim == 2: + self.charterr = transpose([err], axes=(2,0,1)) + + if dim == 3: + self.charterr = transpose(err, axes=(1,2,0)) + + def get_err(self): + return self.inputerr + + err = property(get_err, set_err) + # Graph the chart data. # Input is a 3d matrix that describes a plot that has multiple # groups, multiple bars in each group, and multiple values stacked @@ -123,6 +154,9 @@ class BarChart(ChartOptions): dim = len(shape(self.inputdata)) cshape = shape(self.chartdata) + if self.charterr is not None and shape(self.charterr) != cshape: + raise AttributeError, 'Dimensions of error and data do not match' + if dim == 1: colors = self.gen_colors(cshape[2]) colors = [ [ colors ] * cshape[1] ] * cshape[0] @@ -143,7 +177,8 @@ class BarChart(ChartOptions): inner_axes = None if self.xsubticks is not None: color = self.figure.get_facecolor() - self.metaaxes = self.figure.add_axes(self.figure_size, axisbg=color, frameon=False) + self.metaaxes = self.figure.add_axes(self.figure_size, + axisbg=color, frameon=False) for tick in self.metaaxes.xaxis.majorTicks: tick.tick1On = False tick.tick2On = False @@ -151,9 +186,9 @@ class BarChart(ChartOptions): self.metaaxes.set_yticks([]) size = [0] * 4 size[0] = self.figure_size[0] - size[1] = self.figure_size[1] + .05 + size[1] = self.figure_size[1] + .12 size[2] = self.figure_size[2] - size[3] = self.figure_size[3] - .05 + size[3] = self.figure_size[3] - .12 self.axes = self.figure.add_axes(size) outer_axes = self.metaaxes inner_axes = self.axes @@ -163,12 +198,9 @@ class BarChart(ChartOptions): inner_axes = self.axes bars_in_group = len(self.chartdata) - if bars_in_group < 5: - width = 1.0 / ( bars_in_group + 1) - center = width / 2 - else: - width = .8 / bars_in_group - center = .1 + + width = 1.0 / ( bars_in_group + 1) + center = width / 2 bars = [] for i,stackdata in enumerate(self.chartdata): @@ -177,9 +209,12 @@ class BarChart(ChartOptions): for j,bardata in enumerate(stackdata): bardata = array(bardata) ind = arange(len(bardata)) + i * width + center + yerr = None + if self.charterr is not None: + yerr = self.charterr[i][j] bar = self.axes.bar(ind, bardata, width, bottom=bottom, - color=colors[i][j]) - if dim != 1: + color=colors[i][j], yerr=yerr) + if self.xsubticks is not None: self.metaaxes.bar(ind, [0] * len(bardata), width) stack.append(bar) bottom += bardata @@ -205,9 +240,11 @@ class BarChart(ChartOptions): outer_axes.set_xticklabels(self.xticks) if self.xsubticks is not None: - inner_axes.set_xticks(arange((cshape[0] + 1)*cshape[2])*width + 2*center) + numticks = (cshape[0] + 1) * cshape[2] + inner_axes.set_xticks(arange(numticks) * width + 2 * center) self.xsubticks.append('') - inner_axes.set_xticklabels(self.xsubticks * cshape[2], fontsize=8) + inner_axes.set_xticklabels(self.xsubticks * cshape[2], fontsize=7, + rotation=90) if self.legend is not None: if dim == 1: @@ -218,8 +255,12 @@ class BarChart(ChartOptions): number = len(bars[0]) lbars = [ bars[0][number - j - 1][0] for j in xrange(number)] - self.figure.legend(lbars, self.legend, self.legend_loc, - prop=FontProperties(size=self.legend_size)) + if self.fig_legend: + self.figure.legend(lbars, self.legend, self.legend_loc, + prop=FontProperties(size=self.legend_size)) + else: + self.axes.legend(lbars, self.legend, self.legend_loc, + prop=FontProperties(size=self.legend_size)) if self.title is not None: self.axes.set_title(self.title) @@ -243,7 +284,7 @@ class BarChart(ChartOptions): ylabel = [] #if self.ylabel: # ylabel = [ self.ylabel[i] ] - f.write(', '.join(ylabel + [ '%f' % val for val in row]) + '\n') + f.write(', '.join(ylabel + [ '%f' % v for v in row]) + '\n') if dim == 3: f.write("don't do 3D csv files\n") pass @@ -281,7 +322,6 @@ if __name__ == '__main__': chart1.legend = [ 'x%d' % x for x in xrange(myshape[-1]) ] chart1.xticks = [ 'xtick%d' % x for x in xrange(myshape[0]) ] chart1.title = 'this is the title' - chart1.figure_size = [0.1, 0.2, 0.7, 0.85 ] if len(myshape) > 2: chart1.xsubticks = [ '%d' % x for x in xrange(myshape[1]) ] chart1.graph() @@ -298,4 +338,4 @@ if __name__ == '__main__': chart2.savefig('/tmp/test2.png') chart2.savefig('/tmp/test2.ps') - pylab.myshow() +# pylab.show() diff --git a/util/stats/categories.py b/util/stats/categories.py index 8d5d506a2..6d8568879 100644 --- a/util/stats/categories.py +++ b/util/stats/categories.py @@ -1,4 +1,4 @@ -# Copyright (c) 2005 The Regents of The University of Michigan +# Copyright (c) 2005-2006 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -33,10 +33,14 @@ func_categories = { \ 'skb_clone_fraglist' : 'buffer', 'skb_seq_read' : 'buffer', 'sock_alloc_send_skb' : 'buffer', + 'sinic_rxskb_alloc' : 'buffer', # Copy functions + 'sinic_copyfrom' : 'copy', '__copy_user' : 'copy', 'skb_copy_bits' : 'copy', + 'skb_copy_datagram_iovec' : 'copy', + 'sinic_vcopy_iov' : 'idle', # Driver functions 'do_tx_done' : 'driver', diff --git a/util/stats/chart.py b/util/stats/chart.py index 095620172..369a57fc6 100644 --- a/util/stats/chart.py +++ b/util/stats/chart.py @@ -31,6 +31,7 @@ class ChartOptions(object): defaults = { 'chart_size' : (8, 4), 'figure_size' : [0.1, 0.1, 0.6, 0.85], 'title' : None, + 'fig_legend' : True, 'legend' : None, 'legend_loc' : 'upper right', 'legend_size' : 6, diff --git a/util/stats/db.py b/util/stats/db.py index d9b78c7d1..c0e7796eb 100644 --- a/util/stats/db.py +++ b/util/stats/db.py @@ -158,7 +158,7 @@ class Database(object): return None from info import ProxyError, scalar, vector, value, values, total, len - if system is None and hasattr('system', job): + if system is None and hasattr(job, 'system'): system = job.system if system is not None: diff --git a/util/stats/output.py b/util/stats/output.py index e67751bbc..abfb8d901 100644 --- a/util/stats/output.py +++ b/util/stats/output.py @@ -1,4 +1,4 @@ -# Copyright (c) 2005 The Regents of The University of Michigan +# Copyright (c) 2005-2006 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -103,15 +103,17 @@ class StatOutput(ChartOptions): else: groups.append(group) - if not groupopts: - raise AttributeError, 'No group selected for graph group' + has_group = bool(groupopts) + if has_group: + groupopts = [ group for group in crossproduct(groupopts) ] + else: + groupopts = [ None ] - if not baropts: + if baropts: + baropts = [ bar for bar in crossproduct(baropts) ] + else: raise AttributeError, 'No group selected for graph bars' - groupopts = [ group for group in crossproduct(groupopts) ] - baropts = [ bar for bar in crossproduct(baropts) ] - directory = expanduser(graphdir) if not isdir(directory): os.mkdir(directory) @@ -124,12 +126,13 @@ class StatOutput(ChartOptions): for options in self.jobfile.options(groups): chart = BarChart(self) - data = zeros((len(groupopts), len(baropts)), Float) data = [ [ None ] * len(baropts) for i in xrange(len(groupopts)) ] enabled = False stacked = 0 for g,gopt in enumerate(groupopts): for b,bopt in enumerate(baropts): + if gopt is None: + gopt = [] job = self.jobfile.job(options + gopt + bopt) if not job: continue @@ -168,19 +171,24 @@ class StatOutput(ChartOptions): if data.sum() == 0: continue + dim = len(data.shape) x = data.shape[0] - y = data.shape[1] xkeep = [ i for i in xrange(x) if data[i].sum() != 0 ] + y = data.shape[1] ykeep = [ i for i in xrange(y) if data[:,i].sum() != 0 ] data = data.take(xkeep, axis=0) data = data.take(ykeep, axis=1) + if not has_group: + data = data.take([ 0 ], axis=0) chart.data = data - gopts = [ groupopts[i] for i in xkeep ] - bopts = [ baropts[i] for i in ykeep ] + bopts = [ baropts[i] for i in ykeep ] bdescs = [ ' '.join([o.desc for o in opt]) for opt in bopts] - gdescs = [ ' '.join([o.desc for o in opt]) for opt in gopts] + + if has_group: + gopts = [ groupopts[i] for i in xkeep ] + gdescs = [ ' '.join([o.desc for o in opt]) for opt in gopts] if chart.legend is None: if stacked: @@ -192,7 +200,10 @@ class StatOutput(ChartOptions): chart.legend = bdescs if chart.xticks is None: - chart.xticks = gdescs + if has_group: + chart.xticks = gdescs + else: + chart.xticks = [] chart.graph() names = [ opt.name for opt in options ] diff --git a/util/stats/stats.py b/util/stats/stats.py index b75d9fec0..08281287f 100755 --- a/util/stats/stats.py +++ b/util/stats/stats.py @@ -262,6 +262,7 @@ def commands(options, command, args): from output import StatOutput output = StatOutput(options.jobfile, source) output.xlabel = 'System Configuration' + output.colormap = 'RdYlGn' if command == 'stat' or command == 'formula': if len(args) != 1: @@ -286,7 +287,6 @@ def commands(options, command, args): raise CommandException from info import ProxyGroup - sim_seconds = source['sim_seconds'] proxy = ProxyGroup(system = source[options.system]) system = proxy.system @@ -294,7 +294,6 @@ def commands(options, command, args): bytes = etherdev.rxBytes + etherdev.txBytes kbytes = bytes / 1024 packets = etherdev.rxPackets + etherdev.txPackets - bps = etherdev.rxBandwidth + etherdev.txBandwidth def display(): if options.graph: @@ -337,7 +336,7 @@ def commands(options, command, args): return if command == 'pps': - output.stat = packets / sim_seconds + output.stat = packets / source['sim_seconds'] output.ylabel = 'Packets/s' display() return @@ -355,7 +354,7 @@ def commands(options, command, args): if command == 'txbps': output.stat = etherdev.txBandwidth / 1e9 if command == 'bps': - output.stat = bps / 1e9 + output.stat = (etherdev.rxBandwidth + etherdev.txBandwidth) / 1e9 output.ylabel = 'Bandwidth (Gbps)' output.ylim = [ 0.0, 10.0 ] |