diff options
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 9 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index b1818adf0..fccfe2897 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -166,7 +166,7 @@ def format Thumb32BranchesAndMiscCtrl() {{ ((enable ? 1 : 0) << 9); return new Cps(machInst, mods); } else if ((op2 & 0xf0) == 0xf0) { - return new WarnUnimplemented("dbg", machInst); + return new Dbg(machInst); } else { switch (op2) { case 0x0: diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 33197eaec..120372603 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -708,6 +708,15 @@ let {{ decoder_output += BasicConstructor.subst(dmbIop) exec_output += PredOpExecute.subst(dmbIop) + dbgCode = ''' + ''' + dbgIop = InstObjParams("dbg", "Dbg", "PredOp", + {"code": dbgCode, + "predicate_test": predicateTest}) + header_output += BasicDeclare.subst(dbgIop) + decoder_output += BasicConstructor.subst(dbgIop) + exec_output += PredOpExecute.subst(dbgIop) + cpsCode = ''' uint32_t mode = bits(imm, 4, 0); uint32_t f = bits(imm, 5); |