diff options
-rwxr-xr-x | SConstruct | 16 | ||||
-rw-r--r-- | src/arch/arm/isa.hh | 2 | ||||
-rw-r--r-- | src/cpu/reg_class.hh | 2 |
3 files changed, 10 insertions, 10 deletions
diff --git a/SConstruct b/SConstruct index 79522e46f..f689b556a 100755 --- a/SConstruct +++ b/SConstruct @@ -484,11 +484,11 @@ if main['GCC']: compareVersions(main['GCC_VERSION'], '4.9') >= 0: main.Append(CCFLAGS=['-fsanitize=address,undefined', '-fno-omit-frame-pointer'], - LINKFLAGS='-fsanitize=address,undefined') + LINKFLAGS='-fsanitize=address,undefined') else: main.Append(CCFLAGS=['-fsanitize=address', '-fno-omit-frame-pointer'], - LINKFLAGS='-fsanitize=address') + LINKFLAGS='-fsanitize=address') # Only gcc >= 4.9 supports UBSan, so check both the version # and the command-line option before adding the compiler and # linker flags. @@ -541,16 +541,16 @@ elif main['CLANG']: # versions here. if GetOption('with_ubsan'): if GetOption('with_asan'): - env.Append(CCFLAGS=['-fsanitize=address,undefined', - '-fno-omit-frame-pointer'], + main.Append(CCFLAGS=['-fsanitize=address,undefined', + '-fno-omit-frame-pointer'], LINKFLAGS='-fsanitize=address,undefined') else: - env.Append(CCFLAGS='-fsanitize=undefined', - LINKFLAGS='-fsanitize=undefined') + main.Append(CCFLAGS='-fsanitize=undefined', + LINKFLAGS='-fsanitize=undefined') elif GetOption('with_asan'): - env.Append(CCFLAGS=['-fsanitize=address', - '-fno-omit-frame-pointer'], + main.Append(CCFLAGS=['-fsanitize=address', + '-fno-omit-frame-pointer'], LINKFLAGS='-fsanitize=address') else: diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 0521c43f9..7b39682f9 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -461,7 +461,7 @@ namespace ArmISA return INTREG_SP0; default: panic("Invalid exception level"); - break; + return 0; // Never happens. } } else { return flattenIntRegModeIndex(reg); diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 617d17e35..69da9cf7e 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -84,7 +84,7 @@ class RegId { static constexpr size_t Scale = TheISA::NumVecElemPerVecReg; friend struct std::hash<RegId>; public: - RegId() {}; + RegId() : regClass(IntRegClass), regIdx(0), elemIdx(-1) {} RegId(RegClass reg_class, RegIndex reg_idx) : regClass(reg_class), regIdx(reg_idx), elemIdx(-1) { |