diff options
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py | 11 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 7d955eb3e..5d817d2c2 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -829,7 +829,7 @@ 0x0: fxsave(); 0x1: fxrstor(); 0x2: ldmxcsr(); - 0x3: stmxcsr(); + 0x3: Inst::STMXCSR(Md); 0x4: Inst::UD2(); 0x5: decode MODRM_MOD { 0x3: BasicOperate::LFENCE( diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py index 687391b47..831a266c7 100644 --- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py @@ -54,6 +54,15 @@ # Authors: Gabe Black microcode = ''' -# STMXCSR +def macroop STMXCSR_M { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + st t1, seg, sib, disp +}; + +def macroop STMXCSR_P { + rdval t1, "InstRegIndex(MISCREG_MXCSR)" + rdip t7 + st t1, seg, riprel, disp +}; # LDMXCSR ''' |