diff options
| -rw-r--r-- | src/arch/arm/isa/bitfields.isa | 89 | ||||
| -rw-r--r-- | src/arch/arm/types.hh | 75 |
2 files changed, 9 insertions, 155 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index c9f15ff59..5785939cc 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -36,30 +36,17 @@ // Opcode fields def bitfield ENCODING encoding; def bitfield OPCODE opcode; -def bitfield OPCODE_24_23 opcode24_23; def bitfield MEDIA_OPCODE mediaOpcode; def bitfield MEDIA_OPCODE2 mediaOpcode2; def bitfield OPCODE_24 opcode24; def bitfield OPCODE_23_20 opcode23_20; def bitfield OPCODE_23_21 opcode23_21; -def bitfield OPCODE_23 opcode23; -def bitfield OPCODE_22_8 opcode22_8; -def bitfield OPCODE_22_21 opcode22_21; def bitfield OPCODE_22 opcode22; -def bitfield OPCODE_21_20 opcode21_20; -def bitfield OPCODE_20 opcode20; -def bitfield OPCODE_19_18 opcode19_18; def bitfield OPCODE_19 opcode19; def bitfield OPCODE_15_12 opcode15_12; def bitfield OPCODE_15 opcode15; -def bitfield OPCODE_9 opcode9; def bitfield MISC_OPCODE miscOpcode; -def bitfield OPCODE_7_5 opcode7_5; -def bitfield OPCODE_7_6 opcode7_6; def bitfield OPCODE_7 opcode7; -def bitfield OPCODE_6_5 opcode6_5; -def bitfield OPCODE_6 opcode6; -def bitfield OPCODE_5 opcode5; def bitfield OPCODE_4 opcode4; def bitfield IS_MISC isMisc; @@ -76,85 +63,23 @@ def bitfield RM rm; def bitfield RS rs; -def bitfield RDUP rdup; -def bitfield RNDN rddn; - -def bitfield RDHI rdhi; -def bitfield RDLO rdlo; - -def bitfield U_FIELD uField; - -def bitfield PUSWL puswl; -def bitfield PREPOST puswl.prepost; -def bitfield UP puswl.up; -def bitfield PSRUSER puswl.psruser; -def bitfield WRITEBACK puswl.writeback; +def bitfield PUSWL puswl; +def bitfield PREPOST puswl.prepost; +def bitfield UP puswl.up; +def bitfield PSRUSER puswl.psruser; +def bitfield WRITEBACK puswl.writeback; def bitfield LOADOP puswl.loadOp; -def bitfield PUBWL pubwl; -def bitfield PUIWL puiwl; -def bitfield BYTEACCESS byteAccess; - -def bitfield LUAS luas; - -def bitfield IMM imm; -def bitfield IMMED_7_4 immed7_4; -def bitfield IMMED_3_0 immed3_0; - -def bitfield F_MSR msr.f; -def bitfield S_MSR msr.s; -def bitfield X_MSR msr.x; -def bitfield C_MSR msr.c; - -def bitfield Y_6 y; -def bitfield X_5 x; - -def bitfield IMMED_15_4 immed15_4; - -def bitfield W_FIELD wField; +def bitfield PUBWL pubwl; -def bitfield ROTATE rotate; -def bitfield IMMED_7_0 immed7_0; +def bitfield IMM imm; -def bitfield T_FIELD tField; def bitfield IMMED_11_0 immed11_0; -def bitfield IMMED_20_16 immed20_16; -def bitfield IMMED_19_16 immed19_16; - def bitfield IMMED_HI_11_8 immedHi11_8; def bitfield IMMED_LO_3_0 immedLo3_0; -def bitfield ROT rot; - -def bitfield R_FIELD rField; - -def bitfield CARET caret; -def bitfield REGLIST regList; - -def bitfield OFFSET offset; -def bitfield COPRO copro; -def bitfield OP1_7_4 op1_7_4; -def bitfield CM cm; - -def bitfield L_FIELD lField; -def bitfield CD cd; -def bitfield OPTION option; - -def bitfield OP1_23_20 op1_23_20; -def bitfield CN cn; -def bitfield OP2_7_5 op2_7_5; - -def bitfield OP1_23_21 op1_23_21; - def bitfield IMMED_23_0 immed23_0; -def bitfield M_FIELD mField; -def bitfield A_FIELD aField; -def bitfield I_FIELD iField; -def bitfield F_FIELD fField; -def bitfield MODE mode; - -def bitfield A_BLX aBlx; def bitfield CPNUM cpNum; // Note that FP Regs are only 3 bits diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 707d7d0f6..3a0fdf2a5 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -47,28 +47,15 @@ namespace ArmISA Bitfield<27, 25> encoding; Bitfield<24, 21> opcode; Bitfield<24, 20> mediaOpcode; - Bitfield<24, 23> opcode24_23; Bitfield<24> opcode24; Bitfield<23, 20> opcode23_20; Bitfield<23, 21> opcode23_21; - Bitfield<23> opcode23; - Bitfield<22, 8> opcode22_8; - Bitfield<22, 21> opcode22_21; Bitfield<22> opcode22; - Bitfield<21, 20> opcode21_20; - Bitfield<20> opcode20; - Bitfield<19, 18> opcode19_18; Bitfield<19> opcode19; Bitfield<15, 12> opcode15_12; Bitfield<15> opcode15; - Bitfield<9> opcode9; Bitfield<7, 4> miscOpcode; - Bitfield<7, 5> opcode7_5; - Bitfield<7, 6> opcode7_6; Bitfield<7> opcode7; - Bitfield<6, 5> opcode6_5; - Bitfield<6> opcode6; - Bitfield<5> opcode5; Bitfield<4> opcode4; Bitfield<31, 28> condCode; @@ -81,14 +68,6 @@ namespace ArmISA Bitfield<11, 8> rs; - Bitfield<19, 16> rdup; - Bitfield<15, 12> rddn; - - Bitfield<15, 12> rdhi; - Bitfield<11, 8> rdlo; - - Bitfield<23> uField; - SubBitUnion(puswl, 24, 20) Bitfield<24> prepost; Bitfield<23> up; @@ -98,72 +77,22 @@ namespace ArmISA EndSubBitUnion(puswl) Bitfield<24, 20> pubwl; - Bitfield<24, 20> puiwl; - Bitfield<22> byteAccess; - - Bitfield<23, 20> luas; - - SubBitUnion(imm, 7, 0) - Bitfield<7, 4> imm7_4; - Bitfield<3, 0> imm3_0; - EndSubBitUnion(imm) - SubBitUnion(msr, 19, 16) - Bitfield<19> f; - Bitfield<18> s; - Bitfield<17> x; - Bitfield<16> c; - EndSubBitUnion(msr) - - Bitfield<6> y; - Bitfield<5> x; - - Bitfield<15, 4> immed15_4; - - Bitfield<21> wField; + Bitfield<7, 0> imm; Bitfield<11, 8> rotate; - Bitfield<7, 0> immed7_0; - Bitfield<21> tField; Bitfield<11, 0> immed11_0; - - Bitfield<20, 16> immed20_16; - Bitfield<19, 16> immed19_16; + Bitfield<7, 0> immed7_0; Bitfield<11, 8> immedHi11_8; Bitfield<3, 0> immedLo3_0; - - Bitfield<11, 10> rot; - - Bitfield<5> rField; - Bitfield<22> caret; Bitfield<15, 0> regList; Bitfield<23, 0> offset; - Bitfield<11, 8> copro; - Bitfield<7, 4> op1_7_4; - Bitfield<3, 0> cm; - Bitfield<22> lField; - Bitfield<15, 12> cd; - Bitfield<7, 0> option; - - Bitfield<23, 20> op1_23_20; - Bitfield<19, 16> cn; - Bitfield<7, 5> op2_7_5; - - Bitfield<23, 21> op1_23_21; - Bitfield<23, 0> immed23_0; - Bitfield<17> mField; - Bitfield<8> aField; - Bitfield<7> iField; - Bitfield<6> fField; - Bitfield<4, 0> mode; - - Bitfield<24> aBlx; Bitfield<11, 8> cpNum; Bitfield<18, 16> fn; |