diff options
| -rw-r--r-- | src/arch/arm/faults.hh | 3 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 8 | ||||
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 6 |
3 files changed, 13 insertions, 4 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 6c1b223ab..633e74eae 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -92,7 +92,8 @@ class ArmFault : public FaultBase // to allow the translation function to inform // the memory access function not to proceed // for a Prefetch that misses in the TLB. - PrefetchTLBMiss + PrefetchTLBMiss = 0x1f, + PrefetchUncacheable = 0x20 }; struct FaultVals diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f142e03f8..e5f5b36f6 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -556,9 +556,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, outerAttrs: %d\n", te->shareable, te->innerAttrs, te->outerAttrs); setAttr(te->attributes); - if (te->nonCacheable) + if (te->nonCacheable) { req->setFlags(Request::UNCACHEABLE); + // Prevent prefetching from I/O devices. + if (req->isPrefetch()) { + return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable); + } + } + switch ( (dacr >> (te->domain * 2)) & 0x3) { case 0: domainFaults++; diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index e1af20852..3f53b4197 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1222,8 +1222,7 @@ DefaultIEW<Impl>::executeInsts() // Execute instruction. // Note that if the instruction faults, it will be handled // at the commit stage. - if (inst->isMemRef() && - (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { + if (inst->isMemRef()) { DPRINTF(IEW, "Execute: Calculating address for memory " "reference.\n"); @@ -1232,6 +1231,9 @@ DefaultIEW<Impl>::executeInsts() // Loads will mark themselves as executed, and their writeback // event adds the instruction to the queue to commit fault = ldstQueue.executeLoad(inst); + if (inst->isDataPrefetch() || inst->isInstPrefetch()) { + fault = NoFault; + } } else if (inst->isStore()) { fault = ldstQueue.executeStore(inst); |