diff options
| -rw-r--r-- | src/arch/x86/insts/microregop.cc | 99 | ||||
| -rw-r--r-- | src/arch/x86/insts/microregop.hh | 97 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 204 |
3 files changed, 311 insertions, 89 deletions
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index 481d9f0ad..3c60d7212 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -56,10 +56,109 @@ */ #include "arch/x86/insts/microregop.hh" +#include "arch/x86/miscregs.hh" +#include "base/condcodes.hh" #include <string> namespace X86ISA { + uint64_t RegOpBase::genFlags(uint64_t oldFlags, uint64_t flagMask, + uint64_t _dest, uint64_t _src1, uint64_t _src2) const + { + uint64_t flags = oldFlags & ~flagMask; + if(flagMask & CFBit && findCarry(dataSize, _dest, _src1, _src2)) + flags |= CFBit; + if(flagMask & PFBit && findParity(dataSize, _dest)) + flags |= PFBit; + if(flagMask & ECFBit && findCarry(dataSize, _dest, _src1, _src2)) + flags |= ECFBit; + if(flagMask & AFBit && findCarry(4, _dest, _src1, _src2)) + flags |= AFBit; + if(flagMask & EZFBit && findZero(dataSize, _dest)) + flags |= EZFBit; + if(flagMask & ZFBit && findZero(dataSize, _dest)) + flags |= ZFBit; + if(flagMask & SFBit && findNegative(dataSize, _dest)) + flags |= SFBit; + if(flagMask & OFBit && findOverflow(dataSize, _dest, _src1, _src2)) + flags |= OFBit; + return flags; + } + + bool RegOpBase::checkCondition(uint64_t flags) const + { + CCFlagBits ccflags = flags; + switch(ext) + { + case ConditionTests::True: + return true; + case ConditionTests::ECF: + return ccflags.ECF; + case ConditionTests::EZF: + return ccflags.EZF; + case ConditionTests::SZnZF: + return !(!ccflags.EZF & ccflags.ZF); + case ConditionTests::MSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::STRZ: + panic("This condition is not implemented!"); + case ConditionTests::MSTRC: + panic("This condition is not implemented!"); + case ConditionTests::STRZnZF: + panic("This condition is not implemented!"); + case ConditionTests::OF: + return ccflags.OF; + case ConditionTests::CF: + return ccflags.CF; + case ConditionTests::ZF: + return ccflags.ZF; + case ConditionTests::CvZF: + return ccflags.CF | ccflags.ZF; + case ConditionTests::SF: + return ccflags.SF; + case ConditionTests::PF: + return ccflags.PF; + case ConditionTests::SxOF: + return ccflags.SF ^ ccflags.OF; + case ConditionTests::SxOvZF: + return ccflags.SF ^ ccflags.OF | ccflags.ZF; + case ConditionTests::False: + return false; + case ConditionTests::NotECF: + return !ccflags.ECF; + case ConditionTests::NotEZF: + return !ccflags.EZF; + case ConditionTests::NotSZnZF: + return !ccflags.EZF & ccflags.ZF; + case ConditionTests::NotMSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::NotSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::NotMSTRC: + panic("This condition is not implemented!"); + case ConditionTests::NotSTRZnZF: + panic("This condition is not implemented!"); + case ConditionTests::NotOF: + return !ccflags.OF; + case ConditionTests::NotCF: + return !ccflags.CF; + case ConditionTests::NotZF: + return !ccflags.ZF; + case ConditionTests::NotCvZF: + return !(ccflags.CF | ccflags.ZF); + case ConditionTests::NotSF: + return !ccflags.SF; + case ConditionTests::NotPF: + return !ccflags.PF; + case ConditionTests::NotSxOF: + return !(ccflags.SF ^ ccflags.OF); + case ConditionTests::NotSxOvZF: + return !(ccflags.SF ^ ccflags.OF | ccflags.ZF); + } + panic("Unknown condition: %d\n", ext); + return true; + } + std::string RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index b20f13d55..a8049ba19 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -62,18 +62,84 @@ namespace X86ISA { + namespace ConditionTests + { + enum CondTest { + True, + NotFalse = True, + ECF, + EZF, + SZnZF, + MSTRZ, + STRZ, + MSTRC, + STRZnZF, + OF, + CF, + ZF, + CvZF, + SF, + PF, + SxOF, + SxOvZF, + + False, + NotTrue = False, + NotECF, + NotEZF, + NotSZnZF, + NotMSTRZ, + NotSTRZ, + NotMSTRC, + NotSTRZnZF, + NotOF, + NotCF, + NotZF, + NotCvZF, + NotSF, + NotPF, + NotSxOF, + NotSxOvZF + }; + } + /** * Base classes for RegOps which provides a generateDisassembly method. */ - class RegOp : public X86MicroopBase + class RegOpBase : public X86MicroopBase { protected: const RegIndex src1; - const RegIndex src2; const RegIndex dest; - const bool setStatus; const uint8_t dataSize; - const uint8_t ext; + const uint16_t ext; + + // Constructor + RegOpBase(ExtMachInst _machInst, + const char *mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, RegIndex _dest, + uint8_t _dataSize, uint16_t _ext, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), dest(_dest), + dataSize(_dataSize), ext(_ext) + { + } + + //Figure out what the condition code flags should be. + uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask, + uint64_t _dest, uint64_t _src1, uint64_t _src2) const; + bool checkCondition(uint64_t flags) const; + }; + + class RegOp : public RegOpBase + { + protected: + const RegIndex src2; // Constructor RegOp(ExtMachInst _machInst, @@ -81,13 +147,13 @@ namespace X86ISA bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, RegIndex _src2, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext, + uint8_t _dataSize, uint16_t _ext, OpClass __opClass) : - X86MicroopBase(_machInst, mnem, _instMnem, + RegOpBase(_machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, + _src1, _dest, _dataSize, _ext, __opClass), - src1(_src1), src2(_src2), dest(_dest), - setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + src2(_src2) { } @@ -95,15 +161,10 @@ namespace X86ISA const SymbolTable *symtab) const; }; - class RegOpImm : public X86MicroopBase + class RegOpImm : public RegOpBase { protected: - const RegIndex src1; const uint8_t imm8; - const RegIndex dest; - const bool setStatus; - const uint8_t dataSize; - const uint8_t ext; // Constructor RegOpImm(ExtMachInst _machInst, @@ -111,13 +172,13 @@ namespace X86ISA bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, uint8_t _imm8, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext, + uint8_t _dataSize, uint16_t _ext, OpClass __opClass) : - X86MicroopBase(_machInst, mnem, _instMnem, + RegOpBase(_machInst, mnem, _instMnem, isMicro, isDelayed, isFirst, isLast, + _src1, _dest, _dataSize, _ext, __opClass), - src1(_src1), imm8(_imm8), dest(_dest), - setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + imm8(_imm8) { } diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 542b517fb..dd196a50d 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -67,8 +67,12 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; - %(code)s; - %(flag_code)s; + + if(%(cond_check)s) + { + %(code)s; + %(flag_code)s; + } //Write the resulting state to the execution context if(fault == NoFault) @@ -87,8 +91,12 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; - %(code)s; - %(flag_code)s; + + if(%(cond_check)s) + { + %(code)s; + %(flag_code)s; + } //Write the resulting state to the execution context if(fault == NoFault) @@ -110,12 +118,12 @@ def template MicroRegOpDeclare {{ const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, RegIndex _src2, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext); + uint8_t _dataSize, uint8_t _ext); %(class_name)s(ExtMachInst _machInst, const char * instMnem, RegIndex _src1, RegIndex _src2, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext); + uint8_t _dataSize, uint8_t _ext); %(BasicExecDeclare)s }; @@ -133,12 +141,12 @@ def template MicroRegOpImmDeclare {{ const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, uint8_t _imm8, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext); + uint8_t _dataSize, uint8_t _ext); %(class_name)sImm(ExtMachInst _machInst, const char * instMnem, RegIndex _src1, uint8_t _imm8, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext); + uint8_t _dataSize, uint8_t _ext); %(BasicExecDeclare)s }; @@ -154,10 +162,10 @@ def template MicroRegOpConstructor {{ inline %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, RegIndex _src1, RegIndex _src2, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + uint8_t _dataSize, uint8_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, - _src1, _src2, _dest, _setStatus, _dataSize, _ext, + _src1, _src2, _dest, _dataSize, _ext, %(op_class)s) { buildMe(); @@ -167,10 +175,10 @@ def template MicroRegOpConstructor {{ ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, RegIndex _src2, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + uint8_t _dataSize, uint8_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, - _src1, _src2, _dest, _setStatus, _dataSize, _ext, + _src1, _src2, _dest, _dataSize, _ext, %(op_class)s) { buildMe(); @@ -187,10 +195,10 @@ def template MicroRegOpImmConstructor {{ inline %(class_name)sImm::%(class_name)sImm( ExtMachInst machInst, const char * instMnem, RegIndex _src1, uint8_t _imm8, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + uint8_t _dataSize, uint8_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, false, false, false, false, - _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + _src1, _imm8, _dest, _dataSize, _ext, %(op_class)s) { buildMe(); @@ -200,10 +208,10 @@ def template MicroRegOpImmConstructor {{ ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, RegIndex _src1, uint8_t _imm8, RegIndex _dest, - bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + uint8_t _dataSize, uint8_t _ext) : %(base_class)s(machInst, "%(mnemonic)s", instMnem, isMicro, isDelayed, isFirst, isLast, - _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + _src1, _imm8, _dest, _dataSize, _ext, %(op_class)s) { buildMe(); @@ -211,46 +219,74 @@ def template MicroRegOpImmConstructor {{ }}; let {{ + class X86MicroMeta(type): + def __new__(mcls, name, bases, dict): + abstract = False + if "abstract" in dict: + abstract = dict['abstract'] + del dict['abstract'] + + cls = type.__new__(mcls, name, bases, dict) + if not abstract: + allClasses[name] = cls + return cls + + class XXX86Microop(object): + __metaclass__ = X86MicroMeta + abstract = True + class RegOp(X86Microop): - def __init__(self, dest, src1, src2, setStatus): + abstract = True + def __init__(self, dest, src1, src2, flags): self.dest = dest self.src1 = src1 self.src2 = src2 - self.setStatus = setStatus + self.flags = flags self.dataSize = "env.dataSize" - self.ext = 0 + if flags is None: + self.ext = 0 + else: + if not isinstance(flags, (list, tuple)): + raise Exception, "flags must be a list or tuple of flags" + self.ext = " | ".join(flags) + self.className += "Flags" def getAllocator(self, *microFlags): allocator = '''new %(class_name)s(machInst, mnemonic %(flags)s, %(src1)s, %(src2)s, %(dest)s, - %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "src2" : self.src2, "dest" : self.dest, - "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} return allocator class RegOpImm(X86Microop): - def __init__(self, dest, src1, imm8, setStatus): + abstract = True + def __init__(self, dest, src1, imm8, flags): self.dest = dest self.src1 = src1 self.imm8 = imm8 - self.setStatus = setStatus + self.flags = flags self.dataSize = "env.dataSize" - self.ext = 0 + if flags is None: + self.ext = 0 + else: + if not isinstance(flags, (list, tuple)): + raise Exception, "flags must be a list or tuple of flags" + self.ext = " | ".join(flags) + self.className += "Flags" def getAllocator(self, *microFlags): allocator = '''new %(class_name)s(machInst, mnemonic %(flags)s, %(src1)s, %(imm8)s, %(dest)s, - %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + %(dataSize)s, %(ext)s)''' % { "class_name" : self.className, "flags" : self.microFlagsText(microFlags), "src1" : self.src1, "imm8" : self.imm8, "dest" : self.dest, - "setStatus" : self.cppBool(self.setStatus), "dataSize" : self.dataSize, "ext" : self.ext} return allocator @@ -264,7 +300,8 @@ let {{ decoder_output = "" exec_output = "" - def setUpMicroRegOp(name, Name, base, code, child, flagCode): + # A function which builds the C++ classes that implement the microops + def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck): global header_output global decoder_output global exec_output @@ -272,14 +309,20 @@ let {{ iop = InstObjParams(name, Name, base, {"code" : code, - "flag_code" : flagCode}) + "flag_code" : flagCode, + "cond_check" : condCheck}) header_output += MicroRegOpDeclare.subst(iop) decoder_output += MicroRegOpConstructor.subst(iop) exec_output += MicroRegOpExecute.subst(iop) - microopClasses[name] = child - def defineMicroRegOp(mnemonic, code, flagCode): + checkCCFlagBits = "checkCondition(ccFlagBits)" + genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" + + + # This creates a python representations of a microop which are a cross + # product of reg/immediate and flag/no flag versions. + def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False): Name = mnemonic name = mnemonic.lower() @@ -290,35 +333,47 @@ let {{ regCode = matcher.sub("SrcReg2", code) immCode = matcher.sub("imm8", code) - # Build the all register version of this micro op + if not cc: + flagCode = genCCFlagBits % secondSrc + condCode = "true" + else: + flagCode = "" + condCode = checkCCFlagBits + + regFlagCode = matcher.sub("SrcReg2", flagCode) + immFlagCode = matcher.sub("imm8", flagCode) + class RegOpChild(RegOp): - def __init__(self, dest, src1, src2, setStatus=False): - super(RegOpChild, self).__init__(dest, src1, src2, setStatus) - self.className = Name - self.mnemonic = name + mnemonic = name + className = Name + def __init__(self, dest, src1, src2, flags=None): + super(RegOpChild, self).__init__(dest, src1, src2, flags) + + microopClasses[name] = RegOpChild - setUpMicroRegOp(name, Name, "X86ISA::RegOp", \ - regCode, RegOpChild, flagCode); + setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); + setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); - # Build the immediate version of this micro op class RegOpChildImm(RegOpImm): - def __init__(self, dest, src1, src2, setStatus=False): - super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus) - self.className = Name + "Imm" - self.mnemonic = name + "i" - - setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ - immCode, RegOpChildImm, flagCode); - - defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF - defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "") - defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF - defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF - defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "") - defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF - defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "") - defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg - defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "") + mnemonic = name + 'i' + className = Name + 'Imm' + def __init__(self, dest, src1, src2, flags=None): + super(RegOpChildImm, self).__init__(dest, src1, src2, flags) + + microopClasses[name + 'i'] = RegOpChildImm + + setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); + setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode); + + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True) # This has it's own function because Wr ops have implicit destinations def defineMicroRegOpWr(mnemonic, code): @@ -332,24 +387,27 @@ let {{ regCode = matcher.sub("SrcReg2", code) immCode = matcher.sub("imm8", code) - # Build the all register version of this micro op class RegOpChild(RegOp): - def __init__(self, src1, src2): - super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False) - self.className = Name - self.mnemonic = name + mnemonic = name + className = Name + def __init__(self, src1, src2, flags=None): + super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags) + + microopClasses[name] = RegOpChild - setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, RegOpChild, ""); + setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); + setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); - # Build the immediate version of this micro op class RegOpChildImm(RegOpImm): + mnemonic = name + className = Name def __init__(self, src1, src2): - super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False) - self.className = Name + "Imm" - self.mnemonic = name + "i" + super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None) + + microopClasses[name + 'i'] = RegOpChildImm - setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \ - immCode, RegOpChildImm, ""); + setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); + setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') @@ -360,11 +418,13 @@ let {{ class RegOpChild(RegOp): def __init__(self, dest, src1 = "NUM_INTREGS"): - super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False) + super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None) self.className = Name self.mnemonic = name - setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, RegOpChild, ""); + microopClasses[name] = RegOpChild + + setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); defineMicroRegOpRd('Rdip', 'DestReg = RIP') @@ -374,11 +434,13 @@ let {{ class RegOpChild(RegOpImm): def __init__(self, dest, src1, src2): - super(RegOpChild, self).__init__(dest, src1, src2, False) + super(RegOpChild, self).__init__(dest, src1, src2, None) self.className = Name self.mnemonic = name - setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, RegOpChild, ""); + microopClasses[name] = RegOpChild + + setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); defineMicroRegOpImm('Sext', ''' IntReg val = SrcReg1; |