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-rw-r--r--src/arch/alpha/isa/decoder.isa10
-rw-r--r--src/arch/alpha/isa/fp.isa2
-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/arch/alpha/tlb.cc3
-rw-r--r--src/arch/mips/faults.cc4
-rw-r--r--src/arch/mips/faults.hh7
-rw-r--r--src/arch/mips/isa/decoder.isa10
-rw-r--r--src/arch/mips/isa/formats/control.isa8
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa4
-rw-r--r--src/arch/mips/isa/formats/fp.isa4
-rw-r--r--src/arch/mips/isa/formats/unimp.isa6
-rw-r--r--src/arch/mips/isa/includes.isa2
-rw-r--r--src/arch/sparc/isa/base.isa2
-rw-r--r--src/arch/sparc/isa/includes.isa1
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/includes.isa1
17 files changed, 40 insertions, 32 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 106290784..eecf695da 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
- // return EV5 for FULL_SYSTEM and EV6 otherwise
- 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+ // return EV5 for FullSystem and EV6 otherwise
+ 1: implver({{ Rc = FullSystem ? 1 : 2 }});
}
}
}
@@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
* the parser to understand that.
*/
uint64_t unused_var M5_VAR_USED = Rb;
- Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+ Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable);
// All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
- 0xe000: decode FULL_SYSTEM {
+ 0xe000: decode FullSystem {
0: FailUnimpl::rc_se();
default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
}
- 0xf000: decode FULL_SYSTEM {
+ 0xf000: decode FullSystem {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag;
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e3a6b18ab..5821ebcc5 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -45,7 +45,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+ if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 796c5e38e..e87a184c3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -64,6 +64,7 @@ output decoder {{
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
using namespace AlphaISA;
}};
@@ -81,6 +82,7 @@ output exec {{
#include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index b211c4923..623eafb8a 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -42,6 +42,7 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
+#include "sim/full_system.hh"
using namespace std;
@@ -370,7 +371,7 @@ Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
- if (FULL_SYSTEM && PcPAL(req->getPC()))
+ if (FullSystem && PcPAL(req->getPC()))
req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) {
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9ec93f3fe..fc606ad4b 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -134,7 +134,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
setExceptionState(tc, code());
tc->pcState(vect(tc));
@@ -146,7 +146,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name());
/* All reset activity must be invoked from here */
Addr handler = vect(tc);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 89b6924c6..bce828ec1 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -38,6 +38,7 @@
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
namespace MipsISA
{
@@ -163,7 +164,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
- if (FULL_SYSTEM) {
+ if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
tc->setMiscReg(MISCREG_CAUSE, cause);
@@ -197,7 +198,7 @@ class AddressFault : public MipsFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
- if (FULL_SYSTEM)
+ if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
}
};
@@ -249,7 +250,7 @@ class TlbFault : public AddressFault<T>
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code());
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 7b8dafdba..25b470972 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: add({{
IntReg result;
Rd = result = Rs + Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, Rt)) {
fault = new IntegerOverflowFault();
}
@@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: sub({{
IntReg result;
Rd = result = Rs - Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, ~Rt)) {
fault = new IntegerOverflowFault();
}
@@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: addi({{
IntReg result;
Rt = result = Rs + imm;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, imm)) {
fault = new IntegerOverflowFault();
}
@@ -2433,7 +2433,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
0x3: decode OP default FailUnimpl::rdhwr() {
- 0x0: decode FULL_SYSTEM {
+ 0x0: decode FullSystem {
0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
}
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..2d6748c05 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
%(op_decl)s;
%(op_rd)s;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
@@ -176,7 +176,7 @@ output exec {{
bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
- if (!FULL_SYSTEM)
+ if (!FullSystem)
return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
bool inline
isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
isMMUTLB(%(CPU_exec_context)s *xc)
{
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
- return FULL_SYSTEM && (Config & 0x380) == 0x80;
+ return FullSystem && (Config & 0x380) == 0x80;
}
}};
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
bool
isDspEnabled(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
}
}};
@@ -151,7 +151,7 @@ output exec {{
bool
isDspPresent(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
}
}};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
- if (FULL_SYSTEM)
+ if (FullSystem)
fpResetCauseBits(xc);
%(op_decl)s;
%(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
//Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
bool invalid_op = false;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
invalid_op =
fpInvalidOp((FPOp*)this, xc, Fd, traceData);
}
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
return new CoprocessorUnusableFault(0);
else
@@ -210,7 +210,7 @@ output exec {{
CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
return new CoprocessorUnusableFault(1);
else
@@ -227,7 +227,7 @@ output exec {{
CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2))
return new CoprocessorUnusableFault(2);
else
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index c9f5da41d..944254d90 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -58,6 +58,7 @@ output decoder {{
#include "base/cprintf.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux)
#include <fenv.h>
#endif
@@ -90,6 +91,7 @@ output exec {{
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index a42c96ab1..d38df1c25 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -566,7 +566,7 @@ output exec {{
static inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault;
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 0c49cee16..541254d51 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -74,6 +74,7 @@ output exec {{
#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 4a5cf32d0..4ebf23032 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -394,7 +394,7 @@
default: Inst::RET_FAR();
}
0x4: int3();
- 0x5: decode FULL_SYSTEM default int_Ib() {
+ 0x5: decode FullSystem default int_Ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the predecoder
// will sign extend it, and there's no easy way to
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 2471b61ce..030e36404 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
default: Inst::UD2();
}
}
- 0x05: decode FULL_SYSTEM {
+ 0x05: decode FullSystem {
0: SyscallInst::syscall('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: decode MODE_MODE {
@@ -398,7 +398,7 @@
0x1: Inst::RDTSC();
0x2: Inst::RDMSR();
0x3: rdpmc();
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: SyscallInst::sysenter('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: sysenter();
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 237b29877..9a9759c7a 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -84,6 +84,7 @@ output decoder {{
#include "base/misc.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-23 20:25:21 +0000