diff options
| -rw-r--r-- | arch/alpha/vtophys.cc | 8 | ||||
| -rw-r--r-- | base/callback.hh | 13 | ||||
| -rw-r--r-- | base/intmath.hh | 2 | ||||
| -rw-r--r-- | dev/pcidev.cc | 28 | ||||
| -rw-r--r-- | dev/uart.cc | 2 | ||||
| -rw-r--r-- | sim/system.cc | 4 |
6 files changed, 35 insertions, 22 deletions
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc index 5468d4b07..ca6c280bc 100644 --- a/arch/alpha/vtophys.cc +++ b/arch/alpha/vtophys.cc @@ -109,7 +109,7 @@ vtophys(ExecContext *xc, Addr vaddr) Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr); uint64_t entry = xc->physmem->phys_read_qword(pte); if (pte && entry_valid(entry)) - paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET); + paddr = PMAP_PTE_PA(entry) | (vaddr & ALPHA_PGOFSET); } } @@ -141,7 +141,7 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) int len; paddr = vtophys(xc, src); - len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)cplen); + len = min((int)(ALPHA_PGBYTES - (paddr & ALPHA_PGOFSET)), (int)cplen); dmaaddr = (char *)xc->physmem->dma_addr(paddr, len); assert(dmaaddr); @@ -182,7 +182,7 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) int len; paddr = vtophys(xc, dest); - len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)cplen); + len = min((int)(ALPHA_PGBYTES - (paddr & ALPHA_PGOFSET)), (int)cplen); dmaaddr = (char *)xc->physmem->dma_addr(paddr, len); assert(dmaaddr); @@ -222,7 +222,7 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) int len; paddr = vtophys(xc, vaddr); - len = min((int)(ALPHA_PGBYTES - (paddr & PGOFSET)), (int)maxlen); + len = min((int)(ALPHA_PGBYTES - (paddr & ALPHA_PGOFSET)), (int)maxlen); dmaaddr = (char *)xc->physmem->dma_addr(paddr, len); assert(dmaaddr); diff --git a/base/callback.hh b/base/callback.hh index eee629cf5..342ab7e0f 100644 --- a/base/callback.hh +++ b/base/callback.hh @@ -103,4 +103,17 @@ class CallbackQueue } }; +template <class T, void (T::* F)()> +class MakeCallback : public Callback +{ + private: + T *object; + + public: + MakeCallback(T *o) + : object(o) + { } + void process() { (object->*F)(); } +}; + #endif // __CALLBACK_HH__ diff --git a/base/intmath.hh b/base/intmath.hh index 821514668..5ffe27103 100644 --- a/base/intmath.hh +++ b/base/intmath.hh @@ -120,7 +120,7 @@ FloorLog2(int64_t x) } #if defined(__APPLE__) -int +inline int FloorLog2(size_t x) { assert(x > 0); diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 7b13aac80..950d98b54 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -129,7 +129,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) case PCI0_INTERRUPT_LINE: case PCI_CACHE_LINE_SIZE: case PCI_LATENCY_TIMER: - *(uint8_t *)&config.data[offset] = byte_value; + *(uint8_t *)&config.data[offset] = htoa(byte_value); break; default: @@ -142,7 +142,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) case PCI_COMMAND: case PCI_STATUS: case PCI_CACHE_LINE_SIZE: - *(uint16_t *)&config.data[offset] = half_value; + *(uint16_t *)&config.data[offset] = htoa(half_value); break; default: @@ -166,21 +166,21 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) // to size of memory it needs if (word_value == 0xffffffff) { // This is I/O Space, bottom two bits are read only - if (config.data[offset] & 0x1) { - *(uint32_t *)&config.data[offset] = + if (htoa(config.data[offset]) & 0x1) { + *(uint32_t *)&config.data[offset] = htoa( ~(BARSize[barnum] - 1) | - (config.data[offset] & 0x3); + (htoa(config.data[offset]) & 0x3)); } else { // This is memory space, bottom four bits are read only - *(uint32_t *)&config.data[offset] = + *(uint32_t *)&config.data[offset] = htoa( ~(BARSize[barnum] - 1) | - (config.data[offset] & 0xF); + (htoa(config.data[offset]) & 0xF)); } } else { // This is I/O Space, bottom two bits are read only - if(config.data[offset] & 0x1) { - *(uint32_t *)&config.data[offset] = (word_value & ~0x3) | - (config.data[offset] & 0x3); + if(htoa(config.data[offset]) & 0x1) { + *(uint32_t *)&config.data[offset] = htoa((word_value & ~0x3) | + (htoa(config.data[offset]) & 0x3)); if (word_value & ~0x1) { Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO; @@ -205,8 +205,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) } else { // This is memory space, bottom four bits are read only - *(uint32_t *)&config.data[offset] = (word_value & ~0xF) | - (config.data[offset] & 0xF); + *(uint32_t *)&config.data[offset] = htoa((word_value & ~0xF) | + (htoa(config.data[offset]) & 0xF)); if (word_value & ~0x3) { Addr base_addr = (word_value & ~0x3) + @@ -238,14 +238,14 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) if (word_value == 0xfffffffe) *(uint32_t *)&config.data[offset] = 0xffffffff; else - *(uint32_t *)&config.data[offset] = word_value; + *(uint32_t *)&config.data[offset] = htoa(word_value); break; case PCI_COMMAND: // This could also clear some of the error bits in the Status // register. However they should never get set, so lets ignore // it for now - *(uint16_t *)&config.data[offset] = half_value; + *(uint16_t *)&config.data[offset] = htoa(half_value); break; default: diff --git a/dev/uart.cc b/dev/uart.cc index fca856d5d..f03e3899f 100644 --- a/dev/uart.cc +++ b/dev/uart.cc @@ -287,7 +287,7 @@ Uart::write(MemReqPtr &req, const uint8_t *data) switch (daddr) { case 0x0: if (!(LCR & 0x80)) { // write byte - cons->out(*(uint64_t *)data); + cons->out(*(uint8_t *)data); platform->clearConsoleInt(); status &= ~TX_INT; if (UART_IER_THRI & IER) diff --git a/sim/system.cc b/sim/system.cc index f8312e33b..9fdadf649 100644 --- a/sim/system.cc +++ b/sim/system.cc @@ -156,8 +156,8 @@ System::System(Params *p) if (!hwrpb) panic("could not translate hwrpb addr\n"); - *(uint64_t*)(hwrpb+0x50) = params->system_type; - *(uint64_t*)(hwrpb+0x58) = params->system_rev; + *(uint64_t*)(hwrpb+0x50) = htoa(params->system_type); + *(uint64_t*)(hwrpb+0x58) = htoa(params->system_rev); } else panic("could not find hwrpb\n"); |