diff options
47 files changed, 1077 insertions, 452 deletions
diff --git a/src/SConscript b/src/SConscript index 34c5453b7..7a3b25c92 100644 --- a/src/SConscript +++ b/src/SConscript @@ -277,9 +277,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs): if strip: stripped_bin = bin + '.stripped' if sys.platform == 'sunos5': - newEnv.Command(stripped_bin, bin, 'cp $SOURCE $TARGET; strip $TARGET') + cmd = 'cp $SOURCE $TARGET; strip $TARGET' else: - newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET') + cmd = 'strip $SOURCE -o $TARGET' + newEnv.Command(stripped_bin, bin, cmd) bin = stripped_bin targets = newEnv.Concat(exe, [bin, 'm5py.zip']) newEnv.M5Binary = targets[0] diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 0407ce99b..4887de856 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -44,8 +44,6 @@ namespace AlphaISA { protected: ThreadContext * tc; - //The pc of the current instruction - Addr fetchPC; //The extended machine instruction being generated ExtMachInst ext_inst; @@ -69,10 +67,8 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - fetchPC = _fetchPC; - assert(off == 0); ext_inst = inst; #if FULL_SYSTEM if (pc && 0x1) diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py index a8a63e1f8..32dd79fdf 100644 --- a/src/arch/micro_asm.py +++ b/src/arch/micro_asm.py @@ -127,11 +127,16 @@ def print_error(message): def handle_statement(parser, container, statement): if statement.is_microop: + if statement.mnemonic not in parser.microops.keys(): + raise Exception, "Unrecognized mnemonic: %s" % statement.mnemonic + parser.symbols["__microopClassFromInsideTheAssembler"] = \ + parser.microops[statement.mnemonic] try: - microop = eval('parser.microops[statement.mnemonic](%s)' % - statement.params) + microop = eval('__microopClassFromInsideTheAssembler(%s)' % + statement.params, {}, parser.symbols) except: - print_error("Error creating microop object.") + print_error("Error creating microop object with mnemonic %s." % \ + statement.mnemonic) raise try: for label in statement.labels: @@ -143,8 +148,13 @@ def handle_statement(parser, container, statement): print_error("Error adding microop.") raise elif statement.is_directive: + if statement.name not in container.directives.keys(): + raise Exception, "Unrecognized directive: %s" % statement.name + parser.symbols["__directiveFunctionFromInsideTheAssembler"] = \ + container.directives[statement.name] try: - eval('container.directives[statement.name](%s)' % statement.params) + eval('__directiveFunctionFromInsideTheAssembler(%s)' % + statement.params, {}, parser.symbols) except: print_error("Error executing directive.") print container.directives @@ -212,6 +222,19 @@ def t_params_COLON(t): t.lexer.begin('asm') return t +# Parameters are a string of text which don't contain an unescaped statement +# statement terminator, ie a newline or semi colon. +def t_params_PARAMS(t): + r'([^\n;\\]|(\\[\n;\\]))+' + t.lineno += t.value.count('\n') + unescapeParamsRE = re.compile(r'(\\[\n;\\])') + def unescapeParams(mo): + val = mo.group(0) + return val[1] + t.value = unescapeParamsRE.sub(unescapeParams, t.value) + t.lexer.begin('asm') + return t + # An "ID" in the micro assembler is either a label, directive, or mnemonic # If it's either a directive or a mnemonic, it will be optionally followed by # parameters. If it's a label, the following colon will make the lexer stop @@ -222,28 +245,13 @@ def t_asm_ID(t): t.lexer.begin('params') return t -# If there is a label and you're -not- in the assember (which would be caught +# If there is a label and you're -not- in the assembler (which would be caught # above), don't start looking for parameters. def t_ANY_ID(t): r'[A-Za-z_]\w*' t.type = reserved_map.get(t.value, 'ID') return t -# Parameters are a string of text which don't contain an unescaped statement -# statement terminator, ie a newline or semi colon. -def t_params_PARAMS(t): - r'([^\n;\\]|(\\[\n;\\]))+' - t.lineno += t.value.count('\n') - unescapeParamsRE = re.compile(r'(\\[\n;\\])') - def unescapeParams(mo): - val = mo.group(0) - print "About to sub %s for %s" % (val[1], val) - return val[1] - print "Looking for matches in %s" % t.value - t.value = unescapeParamsRE.sub(unescapeParams, t.value) - t.lexer.begin('asm') - return t - # Braces enter and exit micro assembly def t_INITIAL_LBRACE(t): r'\{' @@ -478,14 +486,11 @@ class MicroAssembler(object): self.parser.microops = microops self.parser.rom = rom self.parser.rom_macroop_type = rom_macroop_type + self.parser.symbols = {} + self.symbols = self.parser.symbols def assemble(self, asm): self.parser.parse(asm, lexer=self.lexer) - # Begin debug printing - for macroop in self.parser.macroops.values(): - print macroop - print self.parser.rom - # End debug printing macroops = self.parser.macroops self.parser.macroops = {} return macroops diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index 90f768d73..e310dded4 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -66,9 +66,8 @@ namespace MipsISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - assert(off == 0); emi = inst; } diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 38d8fd1a2..d990c3256 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -67,10 +67,8 @@ namespace SparcISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - assert(off == 0); - emi = inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 2e2c5b006..6de243c9c 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -85,6 +85,7 @@ Import('*') if env['TARGET_ISA'] == 'x86': + Source('emulenv.cc') Source('floatregfile.cc') Source('intregfile.cc') Source('miscregfile.cc') diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc new file mode 100644 index 000000000..e3f703cff --- /dev/null +++ b/src/arch/x86/emulenv.cc @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/emulenv.hh" +#include "base/misc.hh" + +using namespace X86ISA; + +void EmulEnv::doModRM(const ExtMachInst & machInst) +{ + assert(machInst.modRM.mod != 3); + //Use the SIB byte for addressing if the modrm byte calls for it. + if (machInst.modRM.rm == 4 && machInst.addrSize != 2) { + scale = 1 << machInst.sib.scale; + index = machInst.sib.index; + base = machInst.sib.base; + //In this special case, we don't use a base. The displacement also + //changes, but that's managed by the predecoder. + if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0) + base = NUM_INTREGS; + //In -this- special case, we don't use an index. + if (machInst.sib.index == INTREG_RSP) + index = NUM_INTREGS; + } else { + if (machInst.addrSize == 2) { + warn("I'm not really using 16 bit MODRM like I'm supposed to!\n"); + } else { + scale = 0; + base = machInst.modRM.rm; + if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) { + base = NUM_INTREGS; + if (machInst.mode.submode == SixtyFourBitMode) + base = NUM_INTREGS+7; + } + } + } +} + diff --git a/src/arch/x86/emulenv.hh b/src/arch/x86/emulenv.hh new file mode 100644 index 000000000..66c56fb79 --- /dev/null +++ b/src/arch/x86/emulenv.hh @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_EMULENV_HH__ +#define __ARCH_X86_EMULENV_HH__ + +#include "arch/x86/types.hh" +#include "arch/x86/intregs.hh" + +namespace X86ISA +{ + struct EmulEnv + { + RegIndex reg; + RegIndex regm; + uint8_t scale; + RegIndex index; + RegIndex base; + int dataSize; + int addressSize; + int stackSize; + + EmulEnv(RegIndex _reg, RegIndex _regm, + int _dataSize, int _addressSize, int _stackSize) : + reg(_reg), regm(_regm), + scale(0), index(NUM_INTREGS), + base(NUM_INTREGS), + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) + {;} + + void doModRM(const ExtMachInst & machInst); + }; +}; + +#endif // __ARCH_X86_TYPES_HH__ diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index fc2098716..1b5777f01 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -150,4 +150,4 @@ namespace X86ISA }; }; -#endif // __ARCH_X86_INTERRUPTS_HH__ +#endif // __ARCH_X86_INTREGS_HH__ diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index b72b2b16a..484f8160d 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -63,8 +63,14 @@ 0x00: decode OPCODE_OP_BOTTOM3 { 0x4: ADD(); 0x5: ADD(); - 0x6: push_ES(); - 0x7: pop_ES(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_ES(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_ES(); + } default: ADD(); } 0x01: decode OPCODE_OP_BOTTOM3 { @@ -74,7 +80,10 @@ 0x3: or_Gv_Ev(); 0x4: or_Al_Ib(); 0x5: or_rAX_Iz(); - 0x6: push_CS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_CS(); + } //Any time this is seen, it should generate a two byte opcode 0x7: M5InternalError::error( {{"Saw a one byte opcode whose value was 0x0F!"}}); @@ -86,8 +95,14 @@ 0x3: adc_Gv_Ev(); 0x4: adc_Al_Ib(); 0x5: adc_rAX_Iz(); - 0x6: push_SS(); - 0x7: pop_SS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_SS(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_SS(); + } } 0x03: decode OPCODE_OP_BOTTOM3 { 0x0: sbb_Eb_Gb(); @@ -96,8 +111,14 @@ 0x3: sbb_Gv_Ev(); 0x4: sbb_Al_Ib(); 0x5: sbb_rAX_Iz(); - 0x6: push_DS(); - 0x7: pop_DS(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: push_DS(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pop_DS(); + } } 0x04: decode OPCODE_OP_BOTTOM3 { 0x0: and_Eb_Gb(); @@ -108,7 +129,10 @@ 0x5: and_rAX_Iz(); 0x6: M5InternalError::error( {{"Tried to execute the ES segment override prefix!"}}); - 0x7: daa(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: daa(); + } } 0x05: decode OPCODE_OP_BOTTOM3 { 0x0: sub_Eb_Gb(); @@ -126,7 +150,10 @@ 0x5: Inst::XOR(rAx,Iz); 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); - 0x7: aaa(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aaa(); + } default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev]); @@ -140,53 +167,78 @@ 0x5: cmp_rAX_Iz(); 0x6: M5InternalError::error( {{"Tried to execute the DS segment override prefix!"}}); - 0x7: aas(); - } - 0x08: decode OPCODE_OP_BOTTOM3 { - 0x0: inc_eAX(); - 0x1: inc_eCX(); - 0x2: inc_eDX(); - 0x3: inc_eBX(); - 0x4: inc_eSP(); - 0x5: inc_eBP(); - 0x6: inc_eSI(); - 0x7: inc_eDI(); + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aas(); + } } - 0x09: decode OPCODE_OP_BOTTOM3 { - 0x0: dec_eAX(); - 0x1: dec_eCX(); - 0x2: dec_eDX(); - 0x3: dec_eBX(); - 0x4: dec_eSP(); - 0x5: dec_eBP(); - 0x6: dec_eSI(); - 0x7: dec_eDI(); + 0x08: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: decode OPCODE_OP_BOTTOM3 { + 0x0: inc_eAX(); + 0x1: inc_eCX(); + 0x2: inc_eDX(); + 0x3: inc_eBX(); + 0x4: inc_eSP(); + 0x5: inc_eBP(); + 0x6: inc_eSI(); + 0x7: inc_eDI(); + } } - 0x0A: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::PUSH(rAx); - 0x1: push_rCX(); - 0x2: push_rDX(); - 0x3: push_rBX(); - 0x4: Inst::PUSH(rSP); - 0x5: push_rBP(); - 0x6: push_rSI(); - 0x7: push_rDI(); + 0x09: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: decode OPCODE_OP_BOTTOM3 { + 0x0: dec_eAX(); + 0x1: dec_eCX(); + 0x2: dec_eDX(); + 0x3: dec_eBX(); + 0x4: dec_eSP(); + 0x5: dec_eBP(); + 0x6: dec_eSI(); + 0x7: dec_eDI(); + } } - 0x0B: decode OPCODE_OP_BOTTOM3 { - 0x0: pop_rAX(); - 0x1: pop_rCX(); - 0x2: pop_rDX(); - 0x3: pop_rBX(); - 0x4: pop_rSP(); - 0x5: pop_rBP(); - 0x6: Inst::POP(rSI); - 0x7: pop_rDI(); + format Inst { + 0x0A: decode OPCODE_OP_BOTTOM3 { + 0x0: PUSH(rAx); + 0x1: PUSH(rCx); + 0x2: PUSH(rDx); + 0x3: PUSH(rBx); + 0x4: PUSH(rSP); + 0x5: PUSH(rBP); + 0x6: PUSH(rSI); + 0x7: PUSH(rDI); + } + 0x0B: decode OPCODE_OP_BOTTOM3 { + 0x0: POP(rAx); + 0x1: POP(rCx); + 0x2: POP(rDx); + 0x3: POP(rBx); + 0x4: POP(rSP); + 0x5: POP(rBP); + 0x6: POP(rSI); + 0x7: POP(rDI); + } } 0x0C: decode OPCODE_OP_BOTTOM3 { - 0x0: pusha(); - 0x1: popa(); - 0x2: bound_Gv_Ma(); - 0x3: arpl_Ew_Gw(); + 0x0: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: pusha(); + } + 0x1: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: popa(); + } + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: bound_Gv_Ma(); + } + 0x3: decode MODE_SUBMODE { + 0x0: Inst::MOVSXD(Gv,Ed); + default: arpl_Ew_Gw(); + } 0x4: M5InternalError::error( {{"Tried to execute the FS segment override prefix!"}}); 0x5: M5InternalError::error( @@ -228,8 +280,21 @@ } 0x10: decode OPCODE_OP_BOTTOM3 { 0x0: group1_Eb_Ib(); - 0x1: group1_Ev_Iz(); - 0x2: group1_Eb_Ib(); + //0x1: group1_Ev_Iz(); + 0x1: decode MODRM_REG { + 0x0: add_Ev_Iz(); + 0x1: or_Ev_Ibz(); + 0x2: adc_Ev_Iz(); + 0x3: sbb_Ev_Iz(); + 0x4: Inst::AND(Ev,Iz); + 0x5: Inst::SUB(Ev,Iz); + 0x6: xor_Ev_Iz(); + 0x7: cmp_Ev_Iz(); + } + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: group1_Eb_Ib(); + } //0x3: group1_Ev_Ib(); 0x3: decode MODRM_REG { 0x0: add_Eb_Ib(); @@ -241,8 +306,8 @@ 0x6: xor_Eb_Ib(); 0x7: cmp_Eb_Ib(); } - 0x4: test_Eb_Gb(); - 0x5: test_Ev_Gv(); + 0x4: Inst::TEST(Eb,Gb); + 0x5: Inst::TEST(Ev,Gv); 0x6: xchg_Eb_Gb(); 0x7: xchg_Ev_Gv(); } @@ -250,14 +315,14 @@ 0x0: Inst::MOV(Eb,Gb); 0x1: Inst::MOV(Ev,Gv); 0x2: Inst::MOV(Gb,Eb); - 0x3: Inst::MOV(Gv,Eb); + 0x3: Inst::MOV(Gv,Ev); 0x4: mov_MwRv_Sw(); //What to do with this one? - 0x5: lea_Gv_M(); + 0x5: Inst::LEA(Gv,M); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev } 0x12: decode OPCODE_OP_BOTTOM3 { - 0x0: nop_or_pause(); //Check for repe prefix + default: nop_or_pause(); //Check for repe prefix 0x1: xchg_rCX_rAX(); 0x2: xchg_rDX_rAX(); 0x3: xchg_rVX_rAX(); @@ -269,12 +334,23 @@ 0x13: decode OPCODE_OP_BOTTOM3 { 0x0: cbw_or_cwde_or_cdqe_rAX(); 0x1: cwd_or_cdq_or_cqo_rAX_rDX(); - 0x2: call_Ap(); + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: call_Ap(); + } 0x3: fwait(); //aka wait 0x4: pushf_Fv(); 0x5: popf_Fv(); - 0x6: sahf(); - 0x7: lahf(); + //Both of these should be illegal only if CPUID.AHF64=0, + //according to sandpile.org + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: sahf(); + } + 0x7: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: lahf(); + } } 0x14: decode OPCODE_OP_BOTTOM3 { 0x0: mov_Al_Ob(); @@ -287,8 +363,8 @@ 0x7: cmps_Yv_Xv(); } 0x15: decode OPCODE_OP_BOTTOM3 { - 0x0: test_Al_Ib(); - 0x1: test_rAX_Iz(); + 0x0: Inst::TEST(rAl,Ib); + 0x1: Inst::TEST(rAX,Iz); 0x2: stos_Yb_Al(); 0x3: stos_Yv_rAX(); 0x4: lods_Al_Xb(); @@ -306,23 +382,31 @@ 0x6: mov_Dh_Ib(); 0x7: mov_Bh_Ib(); } - 0x17: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_rAX_Iv(); - 0x1: mov_rCX_Iv(); - 0x2: mov_rDX_Iv(); - 0x3: mov_rBX_Iv(); - 0x4: mov_rSP_Iv(); - 0x5: mov_rBP_Iv(); - 0x6: mov_rSI_Iv(); - 0x7: mov_rDI_Iv(); + format Inst { + 0x17: decode OPCODE_OP_BOTTOM3 { + 0x0: MOV(rAX,Iv); + 0x1: MOV(rCX,Iv); + 0x2: MOV(rDX,Iv); + 0x3: MOV(rBX,Iv); + 0x4: MOV(rSP,Iv); + 0x5: MOV(rBP,Iv); + 0x6: MOV(rSI,Iv); + 0x7: MOV(rDI,Iv); + } } 0x18: decode OPCODE_OP_BOTTOM3 { 0x0: group2_Eb_Ib(); 0x1: group2_Ev_Ib(); 0x2: ret_near_Iw(); 0x3: ret_near(); - 0x4: les_Gz_Mp(); - 0x5: lds_Gz_Mp(); + 0x4: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: les_Gz_Mp(); + } + 0x5: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: lds_Gz_Mp(); + } //0x6: group12_Eb_Ib(); 0x6: decode MODRM_REG { 0x0: Inst::MOV(Eb,Ib); @@ -339,7 +423,10 @@ 0x3: ret_far(); 0x4: int3(); 0x5: int_Ib(); - 0x6: into(); + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: into(); + } 0x7: iret(); } 0x1A: decode OPCODE_OP_BOTTOM3 { @@ -347,9 +434,18 @@ 0x1: group2_Ev_1(); 0x2: group2_Eb_Cl(); 0x3: group2_Ev_Cl(); - 0x4: aam_Ib(); - 0x5: aad_Ib(); - 0x6: salc(); + 0x4: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aam_Ib(); + } + 0x5: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: aad_Ib(); + } + 0x6: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: salc(); + } 0x7: xlat(); } 0x1B: decode OPCODE_OP_BOTTOM3 { @@ -373,9 +469,12 @@ 0x7: out_Ib_eAX(); } 0x1D: decode OPCODE_OP_BOTTOM3 { - 0x0: call_Jz(); + 0x0: Inst::CALL(Jz); 0x1: jmp_Jz(); - 0x2: jmp_Ap(); + 0x2: decode MODE_SUBMODE { + 0x0: This_should_be_an_illegal_instruction(); + default: jmp_Ap(); + } 0x3: jmp_Jb(); 0x4: in_Al_Dx(); 0x5: in_eAX_Dx(); diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 37b28fe64..97777f727 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -70,8 +70,8 @@ def format Inst(*opTypeSet) {{ def format MultiInst(switchVal, *opTypeSets) {{ switcher = {} for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets): - switcher[count] = (Name, opTypeSet, EmulEnv()) - blocks = doSplitDecode(specializeInst, switchVal, switcher) + switcher[count] = (specializeInst, Name, opTypeSet, EmulEnv()) + blocks = doSplitDecode(switchVal, switcher) (header_output, decoder_output, decode_block, exec_output) = blocks.makeList() }}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 8bb282150..3ef204850 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -96,7 +96,7 @@ output header {{ #include <sstream> #include <iostream> -#include "arch/x86/faults.hh" +#include "arch/x86/emulenv.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regfile.hh" #include "arch/x86/types.hh" @@ -104,10 +104,12 @@ output header {{ #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" // some constructors use MemReq flags +#include "sim/faults.hh" }}; output decoder {{ - +#include "arch/x86/faults.hh" +#include "arch/x86/segmentregs.hh" #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py index 283152f30..809b9ac7c 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -53,7 +53,27 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop SUB_R_I +{ + subi reg, reg, imm +}; + +def macroop SUB_M_I +{ + ld t1, ds, [scale, index, base], disp + subi t1, t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop SUB_P_I +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + subi t1, t1, imm + st t1, ds, [scale, index, base], disp +}; +''' #let {{ # class ADC(Inst): # "Adc ^0 ^0 ^1" diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py index b4d1cf9b8..89d406912 100644 --- a/src/arch/x86/isa/insts/compare_and_test/test.py +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -53,8 +53,43 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class TEST(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop TEST_M_R +{ + ld t1, ds, [scale, index, base], disp + and t0, t1, reg +}; + +def macroop TEST_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + and t0, t1, reg +}; + +def macroop TEST_R_R +{ + and t0, reg, regm +}; + +def macroop TEST_M_I +{ + ld t1, ds, [scale, index, base], disp + limm t2, imm + and t0, t1, t2 +}; + +def macroop TEST_P_I +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + limm t2, imm + and t0, t1, t2 +}; + +def macroop TEST_R_I +{ + limm t1, imm + and t0, reg, t1 +}; +''' diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py index 231db6e40..1372f7dba 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -53,7 +53,19 @@ # # Authors: Gabe Black -microcode = "" +microcode = ''' +def macroop CALL_I +{ + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env oszIn64Override + + limm t2, imm + rdip t1 + subi "INTREG_RSP", "INTREG_RSP", dsz + st t1, ss, [0, t0, "INTREG_RSP"] + wrip t1, t2 +}; +''' #let {{ # class CALL(Inst): # "GenFault ${new UnimpInstFault}" diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py index ff4af0af4..c85dd7cc4 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -55,24 +55,55 @@ microcode = ''' def macroop MOV_R_R { - mov "env.reg", "env.reg", "env.regm" + mov reg, reg, regm }; def macroop MOV_M_R { - #Do a store to put the register operand into memory + st reg, ds, [scale, index, base], disp +}; + +def macroop MOV_P_R { + rdip t7 + st reg, ds, [scale, index, base], disp }; def macroop MOV_R_M { - #Do a load to fill the register operand from memory + ld reg, ds, [scale, index, base], disp +}; + +def macroop MOV_R_P { + rdip t7 + ld reg, ds, [scale, index, base], disp }; def macroop MOV_R_I { - limm "env.reg", "IMMEDIATE" + limm reg, imm }; def macroop MOV_M_I { - limm "env.reg", "IMMEDIATE" - #Do a store to put the register operand into memory + limm t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop MOV_P_I { + rdip t7 + limm t1, imm + st t1, ds, [scale, index, base], disp +}; + +def macroop MOVSXD_R_R { + sext reg, regm, dsz +}; + +def macroop MOVSXD_R_M { + ld t1, ds, [scale, index, base], disp + sext reg, t1, dsz +}; + +def macroop MOVSXD_R_P { + rdip t7 + ld t1, ds, [scale, index, base], disp + sext reg, t1, dsz }; ''' #let {{ diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py index 50b690354..ca2443752 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -55,34 +55,26 @@ microcode = ''' def macroop POP_R { - # Make the default data size of pops 64 bits in 64 bit mode - .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + .adjust_env oszIn64Override - ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] - addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" + ld reg, ss, [0, t0, "INTREG_RSP"] + addi "INTREG_RSP", "INTREG_RSP", dsz }; def macroop PUSH_R { - # Make the default data size of pops 64 bits in 64 bit mode - .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + .adjust_env oszIn64Override - subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" - st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] + subi "INTREG_RSP", "INTREG_RSP", dsz + st reg, ss, [0, t0, "INTREG_RSP"] }; ''' #let {{ -# class POP(Inst): -# "GenFault ${new UnimpInstFault}" -# class POPA(Inst): -# "GenFault ${new UnimpInstFault}" # class POPA(Inst): # "GenFault ${new UnimpInstFault}" # class POPAD(Inst): # "GenFault ${new UnimpInstFault}" -# class PUSH(Inst): -# "GenFault ${new UnimpInstFault}" # class PUSHA(Inst): # "GenFault ${new UnimpInstFault}" # class PUSHAD(Inst): diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py index dab6960b1..dcaf9778e 100644 --- a/src/arch/x86/isa/insts/load_effective_address.py +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -53,8 +53,13 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class LEA(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +def macroop LEA_R_M { + lea reg, ds, [scale, index, base], disp +}; + +def macroop LEA_R_P { + rdip t7 + lea reg, ds, [scale, index, base], disp +}; +''' diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index 824c75053..2fd369d60 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -56,56 +56,72 @@ microcode = ''' def macroop XOR_R_R { - xor "env.reg", "env.reg", "env.regm" + xor reg, reg, regm }; def macroop XOR_R_I { - limm "NUM_INTREGS+1", "IMMEDIATE" - xor "env.reg", "env.reg", "NUM_INTREGS+1" + limm t1, imm + xor reg, reg, t1 }; def macroop XOR_M_R { - #Do a load to get one of the sources - xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg" - #Do a store to write the destination + ld t1, ds, [scale, index, base], disp + xor t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop XOR_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + xor t1, t1, reg + st t1, ds, [scale, index, base], disp }; def macroop XOR_R_M { - #Do a load to get one of the sources - xor "env.reg", "env.reg", "NUM_INTREGS+1" + ld t1, ds, [scale, index, base], disp + xor reg, reg, t1 +}; + +def macroop XOR_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + xor reg, reg, t1 }; def macroop AND_R_I { - limm "NUM_INTREGS+1", "IMMEDIATE" - and "env.reg", "env.reg", "NUM_INTREGS+1" + limm t1, imm + and reg, reg, t1 }; def macroop AND_M_I { - #Do a load to get one of the sources - limm "NUM_INTREGS+1", "IMMEDIATE" - and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2" - #Do a store to write the destination + ld t2, ds, [scale, index, base], disp + limm t1, imm + and t2, t2, t1 + st t2, ds, [scale, index, base], disp +}; + +def macroop AND_P_I +{ + rdip t7 + ld t2, ds, [scale, index, base], disp + limm t1, imm + and t2, t2, t1 + st t2, ds, [scale, index, base], disp }; ''' #let {{ #microcodeString = ''' -# def macroop AND -# { -# And reg reg regm -# }; # def macroop OR # { # Or reg reg regm # }; -# def macroop XOR -# { -# Xor reg reg regm -# }; # def macroop NOT # { # Xor reg reg "0xFFFFFFFFFFFFFFFFULL" diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 0cc818409..8453a4fe9 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -111,6 +111,12 @@ output header {{ }; }}; +////////////////////////////////////////////////////////////////////////////// +// +// X86 specific +// +////////////////////////////////////////////////////////////////////////////// + // Basic instruction class declaration template. def template MacroDeclare {{ namespace X86Macroop @@ -122,17 +128,19 @@ def template MacroDeclare {{ { public: // Constructor. - %(class_name)s(ExtMachInst machInst, EmulEnv env); + %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv env); }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + inline X86Macroop::%(class_name)s::%(class_name)s( + ExtMachInst machInst, EmulEnv env) : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { %(adjust_env)s; + %(do_modrm)s; %(constructor)s; //alloc_microops is the code that sets up the microops //array in the parent class. @@ -140,11 +148,6 @@ def template MacroConstructor {{ } }}; -////////////////////////////////////////////////////////////////////////////// -// -// X86 specific -// - let {{ from micro_asm import Combinational_Macroop, Rom_Macroop class X86Macroop(Combinational_Macroop): @@ -157,6 +160,7 @@ let {{ } self.declared = False self.adjust_env = "" + self.doModRM = "" def getAllocator(self, env): return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): @@ -180,31 +184,11 @@ let {{ iop = InstObjParams(self.name, self.name, "Macroop", {"code" : "", "num_microops" : numMicroops, "alloc_microops" : allocMicroops, - "adjust_env" : self.adjust_env}) + "adjust_env" : self.adjust_env, + "do_modrm" : self.doModRM}) return MacroConstructor.subst(iop); }}; -output header {{ - struct EmulEnv - { - X86ISA::RegIndex reg; - X86ISA::RegIndex regm; - uint8_t scale; - X86ISA::RegIndex index; - X86ISA::RegIndex base; - int dataSize; - int addressSize; - int stackSize; - - EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, - int _dataSize, int _addressSize, int _stackSize) : - reg(_reg), regm(_regm), - dataSize(_dataSize), addressSize(_addressSize), - stackSize(_stackSize) - {;} - }; -}}; - let {{ class EmulEnv(object): def __init__(self): @@ -215,6 +199,8 @@ let {{ self.addressSize = "ADDRSIZE" self.dataSize = "OPSIZE" self.stackSize = "STACKSIZE" + self.doModRM = False + def getAllocator(self): return '''EmulEnv(%(reg)s, %(regm)s, @@ -234,12 +220,15 @@ let {{ }}; let {{ + doModRMString = "env.doModRM(machInst);\n" def genMacroop(Name, env): blocks = OutputBlocks() if not macroopDict.has_key(Name): raise Exception, "Unrecognized instruction: %s" % Name macroop = macroopDict[Name] if not macroop.declared: + if env.doModRM: + macroop.doModRM = doModRMString blocks.header_output = macroop.getDeclaration() blocks.decoder_output = macroop.getDefinition() macroop.declared = True diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index fde430691..4e06f4391 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -68,9 +68,37 @@ let {{ import sys sys.path[0:0] = ["src/arch/x86/isa/"] from insts import microcode - print microcode + # print microcode from micro_asm import MicroAssembler, Rom_Macroop, Rom mainRom = Rom('main ROM') assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + # Add in symbols for the microcode registers + for num in range(15): + assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num + # Add in symbols for the segment descriptor registers + for letter in ("C", "D", "E", "F", "G", "S"): + assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter + # Miscellaneous symbols + symbols = { + "reg" : "env.reg", + "regm" : "env.regm", + "imm" : "IMMEDIATE", + "disp" : "DISPLACEMENT", + "scale" : "env.scale", + "index" : "env.index", + "base" : "env.base", + "dsz" : "env.dataSize", + "osz" : "env.operandSize", + "ssz" : "env.stackSize" + } + assembler.symbols.update(symbols) + + # Code literal which forces a default 64 bit operand size in 64 bit mode. + assembler.symbols["oszIn64Override"] = ''' + if (machInst.mode.submode == SixtyFourBitMode && + env.dataSize == 4) + env.dataSize = 8; + ''' + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 38b690e6a..fbff899a0 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -59,9 +59,6 @@ // ////////////////////////////////////////////////////////////////////////// - -// Load templates - output header {{ /** * Base class for load and store ops @@ -119,6 +116,58 @@ output decoder {{ } }}; +// LEA template + +def template MicroLeaExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroLeaDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(BasicExecDeclare)s + }; +}}; + +// Load templates + def template MicroLoadExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -411,13 +460,27 @@ let {{ exec_output += MicroStoreCompleteAcc.subst(iop) class StoreOp(LdStOp): - def __init__(self, data, addr, segment): - super(LoadOp, self).__init__(data, addr, segment) + def __init__(self, data, segment, addr, disp = 0): + super(LoadOp, self).__init__(data, segment, addr, disp) self.className = Name self.mnemonic = name microopClasses[name] = StoreOp defineMicroLoadOp('St', 'Mem = Data;') + + iop = InstObjParams("lea", "Lea", 'LdStOp', + {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA}) + header_output += MicroLeaDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLeaExecute.subst(iop) + + class LeaOp(LdStOp): + def __init__(self, data, segment, addr, disp = 0): + super(LeaOp, self).__init__(data, segment, addr, disp) + self.className = "Lea" + self.mnemonic = "lea" + + microopClasses["lea"] = LeaOp }}; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index d5fb25cb5..65b75fab8 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -162,6 +162,7 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; %(code)s; + %(flag_code)s; //Write the resulting state to the execution context if(fault == NoFault) @@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; %(code)s; + %(flag_code)s; //Write the resulting state to the execution context if(fault == NoFault) @@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{ let {{ class RegOp(X86Microop): - def __init__(self, dest, src1, src2): + def __init__(self, dest, src1, src2, setStatus): self.dest = dest self.src1 = src1 self.src2 = src2 - self.setStatus = False + self.setStatus = setStatus self.dataSize = "env.dataSize" self.ext = 0 @@ -326,11 +328,11 @@ let {{ return allocator class RegOpImm(X86Microop): - def __init__(self, dest, src1, imm8): + def __init__(self, dest, src1, imm8, setStatus): self.dest = dest self.src1 = src1 self.imm8 = imm8 - self.setStatus = False + self.setStatus = setStatus self.dataSize = "env.dataSize" self.ext = 0 @@ -356,11 +358,22 @@ let {{ decoder_output = "" exec_output = "" - def defineMicroRegOp(mnemonic, code): + def setUpMicroRegOp(name, Name, base, code, child, flagCode): global header_output global decoder_output global exec_output global microopClasses + + iop = InstObjParams(name, Name, base, + {"code" : code, + "flag_code" : flagCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + microopClasses[name] = child + + def defineMicroRegOp(mnemonic, code, flagCode): Name = mnemonic name = mnemonic.lower() @@ -371,43 +384,96 @@ let {{ regCode = matcher.sub("SrcReg2", code) immCode = matcher.sub("imm8", code) - # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) - header_output += MicroRegOpDeclare.subst(iop) - decoder_output += MicroRegOpConstructor.subst(iop) - exec_output += MicroRegOpExecute.subst(iop) - + # Build the all register version of this micro op class RegOpChild(RegOp): - def __init__(self, dest, src1, src2): - super(RegOpChild, self).__init__(dest, src1, src2) + def __init__(self, dest, src1, src2, setStatus=False): + super(RegOpChild, self).__init__(dest, src1, src2, setStatus) self.className = Name self.mnemonic = name - microopClasses[name] = RegOpChild + setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode); + + # Build the immediate version of this micro op + class RegOpChildImm(RegOpImm): + def __init__(self, dest, src1, src2, setStatus=False): + super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode); - # Build up the immediate version of this micro op - iop = InstObjParams(name + "i", Name, - 'RegOpImm', {"code" : immCode}) - header_output += MicroRegOpImmDeclare.subst(iop) - decoder_output += MicroRegOpImmConstructor.subst(iop) - exec_output += MicroRegOpImmExecute.subst(iop) + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "") + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "") + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "") + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "") + + # This has it's own function because Wr ops have implicit destinations + def defineMicroRegOpWr(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() - class RegOpImmChild(RegOpImm): - def __init__(self, dest, src1, imm): - super(RegOpImmChild, self).__init__(dest, src1, imm) + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build the all register version of this micro op + class RegOpChild(RegOp): + def __init__(self, src1, src2): + super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False) + self.className = Name + self.mnemonic = name + + setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, ""); + + # Build the immediate version of this micro op + class RegOpChildImm(RegOpImm): + def __init__(self, src1, src2): + super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False) self.className = Name + "Imm" self.mnemonic = name + "i" - microopClasses[name + "i"] = RegOpImmChild + setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, ""); + + defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') + + # This has it's own function because Rd ops don't always have two parameters + def defineMicroRegOpRd(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() + + class RegOpChild(RegOp): + def __init__(self, dest, src1 = "NUM_INTREGS"): + super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False) + self.className = Name + self.mnemonic = name + + setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, ""); + + defineMicroRegOpRd('Rdip', 'DestReg = RIP') + + def defineMicroRegOpImm(mnemonic, code): + Name = mnemonic + name = mnemonic.lower() + + class RegOpChild(RegOpImm): + def __init__(self, dest, src1, src2): + super(RegOpChild, self).__init__(dest, src1, src2, False) + self.className = Name + self.mnemonic = name - defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF - defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') - defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF - defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF - defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') - defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF - defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') - defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg - defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, ""); + defineMicroRegOpImm('Sext', ''' + IntReg val = SrcReg1; + int sign_bit = bits(val, imm8-1, imm8-1); + val = sign_bit ? (val | ~mask(imm8)) : val; + DestReg = merge(DestReg, val, dataSize);''') }}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 96fdf1c5e..b56223390 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -59,67 +59,63 @@ // ////////////////////////////////////////////////////////////////////////// -def template MicroFaultExecute {{ - Fault %(class_name)s ::execute(%(CPU_exec_context)s *xc, - Trace::InstRecord *traceData) const - { - //Return the fault we were constructed with - return fault; - } -}}; - -def template MicroFaultDeclare {{ - class %(class_name)s : public X86MicroopBase +output header {{ + class MicroFault : public X86MicroopBase { protected: Fault fault; void buildMe(); public: - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, + MicroFault(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, Fault _fault); - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, + MicroFault(ExtMachInst _machInst, const char * instMnem, Fault _fault); %(BasicExecDeclare)s }; }}; -def template MicroFaultConstructor {{ - - inline void %(class_name)s::buildMe() - { - %(constructor)s; - } +output decoder {{ + Fault MicroFault::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Return the fault we were constructed with + return fault; + } +}}; - inline %(class_name)s::%(class_name)s( +output decoder {{ + inline MicroFault::MicroFault( ExtMachInst machInst, const char * instMnem, Fault _fault) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - false, false, false, false, %(op_class)s), fault(_fault) + X86MicroopBase(machInst, "fault", instMnem, + false, false, false, false, No_OpClass), fault(_fault) { - buildMe(); } - inline %(class_name)s::%(class_name)s( + inline MicroFault::MicroFault( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, Fault _fault) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - isMicro, isDelayed, isFirst, isLast, %(op_class)s), + X86MicroopBase(machInst, "fault", instMnem, + isMicro, isDelayed, isFirst, isLast, No_OpClass), fault(_fault) { - buildMe(); } }}; let {{ - # This microop takes in a single parameter, a fault to return. - iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) - header_output += MicroFaultDeclare.subst(iop) - decoder_output += MicroFaultConstructor.subst(iop) - exec_output += MicroFaultExecute.subst(iop) + class Fault(X86Microop): + def __init__(self, fault): + self.fault = fault + + def getAllocator(self, *microFlags): + allocator = '''new MicroFault(machInst, mnemonic + %(flags)s, %(fault)s)''' % { + "flags" : self.microFlagsText(microFlags), + "fault" : self.fault} + return allocator + microopClasses["fault"] = Fault }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index bb2be47d9..3183f32ba 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -64,18 +64,18 @@ let {{ # This code builds up a decode block which decodes based on switchval. # vals is a dict which matches case values with what should be decoded to. - # builder is called on the exploded contents of "vals" values to generate - # whatever code should be used. - def doSplitDecode(builder, switchVal, vals, default = None): + # Each element of the dict is a list containing a function and then the + # arguments to pass to it. + def doSplitDecode(switchVal, vals, default = None): blocks = OutputBlocks() blocks.decode_block = 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - new_blocks = builder(*todo) + new_blocks = todo[0](*todo[1:]) new_blocks.decode_block = \ '\tcase %s: %s\n' % (val, new_blocks.decode_block) blocks.append(new_blocks) if default: - new_blocks = builder(*default) + new_blocks = default[0](*default[1:]) new_blocks.decode_block = \ '\tdefault: %s\n' % new_blocks.decode_block blocks.append(new_blocks) @@ -84,8 +84,29 @@ let {{ }}; let {{ + def doRipRelativeDecode(Name, opTypes, env): + # print "RIPing %s with opTypes %s" % (Name, opTypes) + normBlocks = specializeInst(Name + "_M", copy.copy(opTypes), copy.copy(env)) + ripBlocks = specializeInst(Name + "_P", copy.copy(opTypes), copy.copy(env)) + + blocks = OutputBlocks() + blocks.append(normBlocks) + blocks.append(ripBlocks) + + blocks.decode_block = ''' + if(machInst.modRM.mod == 0 && + machInst.modRM.rm == 5 && + machInst.mode.submode == SixtyFourBitMode) + { %s } + else + { %s }''' % \ + (ripBlocks.decode_block, normBlocks.decode_block) + return blocks +}}; + +let {{ class OpType(object): - parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))") + parser = re.compile(r"(?P<tag>[A-Z]+)(?P<size>[a-z]*)|(r(?P<reg>[A-Z0-9]+)(?P<rsize>[a-z]*))") def __init__(self, opTypeString): match = OpType.parser.search(opTypeString) if match == None: @@ -105,14 +126,15 @@ let {{ while len(opTypes): # Parse the operand type string we're working with opType = OpType(opTypes[0]) + opTypes.pop(0) if opType.reg: #Figure out what to do with fixed register operands #This is the index to use, so we should stick it some place. if opType.reg in ("A", "B", "C", "D"): - env.addReg("INTREG_R%sX" % opType.reg) + env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg) else: - env.addReg("INTREG_R%s" % opType.reg) + env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg) if opType.size: if opType.rsize in ("l", "h", "b"): print "byte" @@ -121,6 +143,11 @@ let {{ else: print "Didn't recognize fixed register size %s!" % opType.rsize Name += "_R" + elif opType.tag == "M": + # This refers to memory. The macroop constructor sets up modrm + # addressing. Non memory modrm settings should cause an error. + Name += "_M" + env.doModRM = True elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): @@ -130,39 +157,24 @@ let {{ elif opType.tag in ("E", "Q", "W"): # This might refer to memory or to a register. We need to # divide it up farther. - regTypes = copy.copy(opTypes) - regTypes.pop(0) regEnv = copy.copy(env) regEnv.addReg(ModRMRMIndex) - regName = Name + "_R" - # This needs to refer to memory, but we'll fill in the details - # later. It needs to take into account unaligned memory - # addresses. - memTypes = copy.copy(opTypes) - memTypes.pop(0) + # This refers to memory. The macroop constructor should set up + # modrm addressing. memEnv = copy.copy(env) - memName = Name + "_M" - print "%0" - return doSplitDecode(specializeInst, "MODRM_MOD", - {"3" : (regName, regTypes, regEnv)}, - (memName, memTypes, memEnv)) + memEnv.doModRM = True + return doSplitDecode("MODRM_MOD", + {"3" : (specializeInst, Name + "_R", copy.copy(opTypes), regEnv)}, + (doRipRelativeDecode, Name, copy.copy(opTypes), memEnv)) elif opType.tag in ("I", "J"): # Immediates Name += "_I" - elif opType.tag == "M": - # This needs to refer to memory, but we'll fill in the details - # later. It needs to take into account unaligned memory - # addresses. - print "%0" - Name += "_M" elif opType.tag in ("PR", "R", "VR"): - # There should probably be a check here to verify that mod - # is equal to 11b + # Non register modrm settings should cause an error env.addReg(ModRMRMIndex) Name += "_R" else: raise Exception, "Unrecognized tag %s." % opType.tag - opTypes.pop(0) # Generate code to return a macroop of the given name which will # operate in the "emulation environment" env diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 3ed18aeb2..49f76699b 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -264,31 +264,30 @@ namespace X86ISA Predecoder::State Predecoder::doModRMState(uint8_t nextByte) { State nextState = ErrorState; - emi.modRM = nextByte; + ModRM modRM; + modRM = nextByte; DPRINTF(Predecoder, "Found modrm byte %#x.\n", nextByte); if (0) {//FIXME in 16 bit mode //figure out 16 bit displacement size - if(nextByte & 0xC7 == 0x06 || - nextByte & 0xC0 == 0x80) + if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2) displacementSize = 2; - else if(nextByte & 0xC0 == 0x40) + else if(modRM.mod == 1) displacementSize = 1; else displacementSize = 0; } else { //figure out 32/64 bit displacement size - if(nextByte & 0xC6 == 0x04 || - nextByte & 0xC0 == 0x80) + if(modRM.mod == 0 && (modRM.rm == 4 || modRM.rm == 5) + || modRM.mod == 2) displacementSize = 4; - else if(nextByte & 0xC0 == 0x40) + else if(modRM.mod == 1) displacementSize = 1; else displacementSize = 0; } //If there's an SIB, get that next. //There is no SIB in 16 bit mode. - if(nextByte & 0x7 == 4 && - nextByte & 0xC0 != 0xC0) { + if(modRM.rm == 4 && modRM.mod != 3) { // && in 32/64 bit mode) nextState = SIBState; } else if(displacementSize) { @@ -301,6 +300,7 @@ namespace X86ISA } //The ModRM byte is consumed no matter what consumeByte(); + emi.modRM = modRM; return nextState; } diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 3c858f061..f34b66364 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -195,12 +195,12 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, MachInst data) { + DPRINTF(Predecoder, "Getting more bytes.\n"); basePC = fetchPC; - offset = off; + offset = (fetchPC >= pc) ? 0 : pc - fetchPC; fetchChunk = data; - assert(off < sizeof(MachInst)); outOfBytes = false; process(); } diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index af7494598..7deb54945 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -268,7 +268,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) int argv_array_size = intSize * (argv.size() + 1); int argc_size = intSize; - int window_save_size = intSize * 16; int space_needed = mysterious_size + @@ -276,8 +275,7 @@ X86LiveProcess::argsInit(int intSize, int pageSize) aux_array_size + envp_array_size + argv_array_size + - argc_size + - window_save_size; + argc_size; stack_min = stack_base - space_needed; stack_min &= alignmentMask; @@ -296,10 +294,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) Addr envp_array_base = auxv_array_base - envp_array_size; Addr argv_array_base = envp_array_base - argv_array_size; Addr argc_base = argv_array_base - argc_size; -#ifndef NDEBUG - // only used in DPRINTF - Addr window_save_base = argc_base - window_save_size; -#endif DPRINTF(X86, "The addresses of items on the initial stack:\n"); DPRINTF(X86, "0x%x - file name\n", file_name_base); @@ -309,7 +303,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize) DPRINTF(X86, "0x%x - envp array\n", envp_array_base); DPRINTF(X86, "0x%x - argv array\n", argv_array_base); DPRINTF(X86, "0x%x - argc \n", argc_base); - DPRINTF(X86, "0x%x - window save\n", window_save_base); DPRINTF(X86, "0x%x - stack min\n", stack_min); // write contents to stack diff --git a/src/arch/x86/segmentregs.hh b/src/arch/x86/segmentregs.hh new file mode 100644 index 000000000..9fd9bcb0e --- /dev/null +++ b/src/arch/x86/segmentregs.hh @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_SEGMENTREGS_HH__ +#define __ARCH_X86_SEGMENTREGS_HH__ + +namespace X86ISA +{ + enum SegmentRegIndex + { + SEGMENT_REG_ES, + SEGMENT_REG_CS, + SEGMENT_REG_SS, + SEGMENT_REG_DS, + SEGMENT_REG_FS, + SEGMENT_REG_GS, + + NUM_SEGMENTREGS + }; +}; + +#endif // __ARCH_X86_SEGMENTREGS_HH__ diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 298dff80b..61ab2bac9 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -160,7 +160,7 @@ namespace X86ISA } opcode; //Modifier bytes ModRM modRM; - uint8_t sib; + Sib sib; //Immediate fields uint64_t immediate; uint64_t displacement; diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 078ae1283..f86313da0 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -269,12 +269,10 @@ Tick BaseCPU::nextCycle(Tick begin_tick) { Tick next_tick = begin_tick; - next_tick -= (next_tick % clock); + if (next_tick % clock != 0) + next_tick = next_tick - (next_tick % clock) + clock; next_tick += phase; - while (next_tick < curTick) - next_tick += clock; - assert(next_tick >= curTick); return next_tick; } diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 9b87f2e8a..85df19348 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -650,7 +650,7 @@ Trace::InstRecord::dump() << endl; predecoder.setTC(thread); - predecoder.moreBytes(m5Pc, m5Pc, 0, + predecoder.moreBytes(m5Pc, m5Pc, shared_data->instruction); assert(predecoder.extMachInstReady()); diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index e031faefa..e691cfe5d 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU): checker.itb = Parent.itb checker.dtb = Parent.dtb - cachePorts = Param.Unsigned("Cache Ports") + cachePorts = Param.Unsigned(200, "Cache Ports") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") _mem_ports = ['icache_port', 'dcache_port'] @@ -137,15 +137,15 @@ class DerivO3CPU(BaseCPU): function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Cycle to start function trace") - smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") - smtFetchPolicy = Param.String("SMT Fetch policy") - smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") - smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") - smtIQPolicy = Param.String("SMT IQ Sharing Policy") - smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") - smtROBPolicy = Param.String("SMT ROB Sharing Policy") - smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") - smtCommitPolicy = Param.String("SMT Commit Policy") + smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") + smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") + smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") + smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") + smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") + smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") def addPrivateSplitL1Caches(self, ic, dc): BaseCPU.addPrivateSplitL1Caches(self, ic, dc) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 8e4c625df..6a3eb9c43 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -204,19 +204,17 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) _status = Idle; } - checker = NULL; - - if (params->checker) { #if USE_CHECKER + if (params->checker) { BaseCPU *temp_checker = params->checker; checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); #if FULL_SYSTEM checker->setSystem(params->system); #endif -#else - panic("Checker enabled but not compiled in!"); -#endif // USE_CHECKER + } else { + checker = NULL; } +#endif // USE_CHECKER #if !FULL_SYSTEM thread.resize(number_of_threads); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index bff78bf9e..84a7c8673 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -42,6 +42,7 @@ #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" +#include "config/use_checker.hh" #include "cpu/activity.hh" #include "cpu/base.hh" #include "cpu/simple_thread.hh" @@ -628,11 +629,13 @@ class FullO3CPU : public BaseO3CPU /** The global sequence number counter. */ InstSeqNum globalSeqNum;//[Impl::MaxThreads]; +#if USE_CHECKER /** Pointer to the checker, which can dynamically verify * instruction results at run time. This can be set to NULL if it * is not being used. */ Checker<DynInstPtr> *checker; +#endif #if FULL_SYSTEM /** Pointer to the system. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 857a08629..01e9b5b31 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1117,7 +1117,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) (&cacheData[tid][offset])); predecoder.setTC(cpu->thread[tid]->getTC()); - predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); + predecoder.moreBytes(fetch_PC, fetch_PC, inst); ext_inst = predecoder.getExtMachInst(); staticInst = StaticInstPtr(ext_inst, fetch_PC); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index ea1c7d87f..03ff1282b 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -521,15 +521,15 @@ AtomicSimpleCPU::tick() dcache_access = false; // assume no dcache access //Fetch more instruction memory if necessary - if(predecoder.needMoreBytes()) - { + //if(predecoder.needMoreBytes()) + //{ icache_access = true; ifetch_pkt->reinitFromRequest(); icache_latency = icachePort.sendAtomic(ifetch_pkt); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. - } + //} preExecute(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index b7f60522f..9285aa7b5 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute() //This should go away once the constructor can be set up properly predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. - if(predecoder.needMoreBytes()) - predecoder.moreBytes(thread->readPC(), - (thread->readPC() & PCMask) + fetchOffset, 0, inst); - else - predecoder.process(); + Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; + //if(predecoder.needMoreBytes()) + predecoder.moreBytes(thread->readPC(), fetchPC, inst); + //else + // predecoder.process(); //If an instruction is ready, decode it. Otherwise, we'll have to //fetch beyond the MachInst at the current pc. diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index e81862a96..587087640 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -64,7 +64,8 @@ class EtherDump(SimObject): class IGbE(PciDevice): type = 'IGbE' - hardware_address = Param.String("Ethernet Hardware Address") + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") @@ -100,9 +101,9 @@ class IGbEInt(EtherInt): type = 'IGbEInt' device = Param.IGbE("Ethernet device of this interface") - - class EtherDevBase(PciDevice): + type = 'EtherDevBase' + abstract = True hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 13e545064..d818a25ea 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -115,11 +115,14 @@ void Bus::occupyBus(PacketPtr pkt) //Bring tickNextIdle up to the present tick //There is some potential ambiguity where a cycle starts, which might make //a difference when devices are acting right around a cycle boundary. Using - //a < allows things which happen exactly on a cycle boundary to take up only - //the following cycle. Anthing that happens later will have to "wait" for - //the end of that cycle, and then start using the bus after that. - while (tickNextIdle < curTick) - tickNextIdle += clock; + //a < allows things which happen exactly on a cycle boundary to take up + //only the following cycle. Anything that happens later will have to "wait" + //for the end of that cycle, and then start using the bus after that. + if (tickNextIdle < curTick) { + tickNextIdle = curTick; + if (tickNextIdle % clock != 0) + tickNextIdle = curTick - (curTick % clock) + clock; + } // The packet will be sent. Figure out how long it occupies the bus, and // how much of that time is for the first "word", aka bus width. @@ -132,10 +135,9 @@ void Bus::occupyBus(PacketPtr pkt) // We're using the "adding instead of dividing" trick again here if (pkt->hasData()) { int dataSize = pkt->getSize(); - for (int transmitted = 0; transmitted < dataSize; - transmitted += width) { + numCycles += dataSize/width; + if (dataSize % width) numCycles++; - } } else { // If the packet didn't have data, it must have been a response. // Those use the bus for one cycle to send their data. diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 32f3f0174..55b68f81f 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -90,3 +90,4 @@ class BaseCache(MemObject): "Only prefetch on data not on instruction accesses") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") + addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes") diff --git a/src/mem/packet.hh b/src/mem/packet.hh index c1e6a1e7f..fb077901e 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -43,6 +43,7 @@ #include <bitset> #include "base/compiler.hh" +#include "base/fast_alloc.hh" #include "base/misc.hh" #include "mem/request.hh" #include "sim/host.hh" @@ -182,7 +183,7 @@ class MemCmd * ultimate destination and back, possibly being conveyed by several * different Packets along the way.) */ -class Packet +class Packet : public FastAlloc { public: @@ -257,7 +258,7 @@ class Packet /** A virtual base opaque structure used to hold coherence-related * state. A specific subclass would be derived from this to * carry state specific to a particular coherence protocol. */ - class CoherenceState { + class CoherenceState : public FastAlloc { public: virtual ~CoherenceState() {} }; @@ -274,7 +275,7 @@ class Packet * needed to process it. A specific subclass would be derived * from this to carry state specific to a particular sending * device. */ - class SenderState { + class SenderState : public FastAlloc { public: virtual ~SenderState() {} }; diff --git a/src/mem/request.hh b/src/mem/request.hh index d2ebc91d3..e08593f0d 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -39,6 +39,7 @@ #ifndef __MEM_REQUEST_HH__ #define __MEM_REQUEST_HH__ +#include "base/fast_alloc.hh" #include "sim/host.hh" #include "sim/core.hh" @@ -76,7 +77,7 @@ const uint32_t MEM_SWAP = 0x100000; const uint32_t MEM_SWAP_COND = 0x200000; -class Request +class Request : public FastAlloc { private: /** @@ -153,6 +154,8 @@ class Request setVirt(_asid, _vaddr, _size, _flags, _pc); } + ~Request() {} // for FastAlloc + /** * Set up CPU and thread numbers. */ void setThreadContext(int _cpuNum, int _threadNum) diff --git a/src/sim/Process.py b/src/sim/Process.py index 16be65fd4..34ff6c394 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -40,7 +40,7 @@ class LiveProcess(Process): type = 'LiveProcess' executable = Param.String('', "executable (overrides cmd[0] if set)") cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") + env = VectorParam.String([], "environment settings") cwd = Param.String('', "current working directory") input = Param.String('cin', "filename for stdin") uid = Param.Int(100, 'user id') diff --git a/src/sim/System.py b/src/sim/System.py index b37e385c1..3f4c57f0c 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -39,6 +39,7 @@ class System(SimObject): physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") if build_env['FULL_SYSTEM']: + abstract = True boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, "boot processor frequency") init_param = Param.UInt64(0, "numerical value to pass into simulator") diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 033bc257f..3458060ce 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 110028 # Simulator instruction rate (inst/s) -host_seconds 573.73 # Real time elapsed on the host -host_tick_rate 3259967057 # Simulator tick rate (ticks/s) +host_inst_rate 1418499 # Simulator instruction rate (inst/s) +host_seconds 44.50 # Real time elapsed on the host +host_tick_rate 42028043491 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63125943 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335097000 # Number of ticks simulated +sim_ticks 1870335101500 # Number of ticks simulated system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.ReadReq_hits 7464198 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185482 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699743 # number of ReadReq misses system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits 5646722 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses 286674 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks. system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -26,10 +26,10 @@ system.cpu0.dcache.cache_copies 0 # nu system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits 13110920 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate 0.131574 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986417 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -41,10 +41,10 @@ system.cpu0.dcache.overall_accesses 15097337 # nu system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_hits 13110920 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_miss_rate 0.131574 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986417 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -61,7 +61,7 @@ system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699743 # read misses to invalid blocks system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks @@ -69,7 +69,7 @@ system.cpu0.dcache.protocol.snoop_inv_owned 0 # system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks -system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_owned 121 # read snoops on owned blocks system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks @@ -83,14 +83,14 @@ system.cpu0.dcache.protocol.snoop_writeinv_modified 0 system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282338 # write misses to invalid blocks system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks -system.cpu0.dcache.replacements 1978969 # number of replacements -system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1978980 # number of replacements +system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 0 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses @@ -161,7 +161,7 @@ system.cpu0.icache.protocol.snoop_inv_invalid 0 system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25832 # read snoops on exclusive blocks system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks @@ -225,8 +225,8 @@ system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # nu system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks 1870334894000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125122500 99.08% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl @@ -246,7 +246,7 @@ system.cpu0.kern.mode_switch_good <err: div-0> # fr system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377894000 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3762 # number of times the context was actually changed @@ -348,7 +348,7 @@ system.cpu1.dcache.protocol.snoop_inv_shared 0 system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks -system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_shared 61772 # read snoops on shared blocks system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks @@ -369,7 +369,7 @@ system.cpu1.dcache.sampled_refs 62660 # Sa system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 0 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations @@ -439,7 +439,7 @@ system.cpu1.icache.protocol.snoop_inv_invalid 0 system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17317 # read snoops on exclusive blocks system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks @@ -463,7 +463,7 @@ system.cpu1.icache.sampled_refs 103609 # Sa system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.warmup_cycle 1868932669000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.itb.accesses 1469938 # ITB accesses @@ -501,8 +501,8 @@ system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # nu system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks 1870124006000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122587500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl @@ -520,9 +520,9 @@ system.cpu1.kern.mode_switch_good 1.608089 # fr system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002156500 99.90% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed @@ -558,30 +558,30 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181108 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408619 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1782852 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782863 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345538 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 941303 # number of ReadReq misses -system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.Writeback_accesses 427634 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427634 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.avg_refs 2.242879 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_accesses 2724166 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_hits 1782863 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_miss_rate 0.345538 # miss rate for demand accesses system.l2c.demand_misses 941303 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles @@ -590,13 +590,13 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_accesses 3151800 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_hits 2210497 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_miss_rate 0.298656 # miss rate for overall accesses system.l2c.overall_misses 941303 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles @@ -616,8 +616,8 @@ system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 system.l2c.replacements 1000779 # number of replacements system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use -system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.tagsinuse 65517.575356 # Cycle average of tags in use +system.l2c.total_refs 2391266 # Total number of references to valid blocks. system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a2ea188c7..722437701 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,23 +1,23 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 109117 # Simulator instruction rate (inst/s) -host_seconds 549.94 # Real time elapsed on the host -host_tick_rate 3324672454 # Simulator tick rate (ticks/s) +host_inst_rate 1403977 # Simulator instruction rate (inst/s) +host_seconds 42.74 # Real time elapsed on the host +host_tick_rate 42777462102 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60007317 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated -sim_ticks 1828355481500 # Number of ticks simulated +sim_ticks 1828355486000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked @@ -26,10 +26,10 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses @@ -41,10 +41,10 @@ system.cpu.dcache.overall_accesses 16072780 # nu system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_hits 14029591 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_misses 2043189 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses @@ -61,7 +61,7 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks @@ -86,11 +86,11 @@ system.cpu.dcache.protocol.swpf_invalid 0 # so system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks -system.cpu.dcache.replacements 2042663 # number of replacements -system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2042664 # number of replacements +system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use -system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses @@ -222,8 +222,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl @@ -243,7 +243,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -296,24 +296,24 @@ system.l2c.ReadExReq_accesses 304342 # nu system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717828 # number of ReadReq hits system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses system.l2c.ReadReq_misses 941044 # number of ReadReq misses system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 428885 # number of Writeback hits system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.avg_refs 2.205901 # Average number of references to valid blocks. system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_hits 1717828 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses system.l2c.demand_misses 941044 # number of demand (read+write) misses @@ -324,11 +324,11 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_hits 2146713 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses system.l2c.overall_misses 941044 # number of overall misses @@ -351,7 +351,7 @@ system.l2c.replacements 992432 # nu system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use -system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.total_refs 2333446 # Total number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post |