diff options
-rw-r--r-- | arch/alpha/isa_desc | 8 | ||||
-rw-r--r-- | arch/alpha/isa_traits.hh | 7 | ||||
-rw-r--r-- | base/inifile.cc | 7 | ||||
-rw-r--r-- | cpu/base_cpu.hh | 3 | ||||
-rw-r--r-- | cpu/exec_context.hh | 13 | ||||
-rw-r--r-- | cpu/exetrace.hh | 13 | ||||
-rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 4 | ||||
-rwxr-xr-x | util/sort-includes | 91 |
8 files changed, 108 insertions, 38 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index e9b93a895..b5536525d 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() { 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }}, {{ uint64_t tmp = Mem_write_result; + // see stq_c Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }}, {{ uint64_t tmp = Mem_write_result; + // If the write operation returns 0 or 1, then + // this was a conventional store conditional, + // and the value indicates the success/failure + // of the operation. If another value is + // returned, then this was a Turbolaser + // mailbox access, and we don't update the + // result register at all. Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); } diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 6b78722ad..5e2dac9f3 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -168,13 +168,6 @@ class AlphaISA ITOUCH_ANNOTE = 0xffffffff, }; -#if 0 - static inline Addr - extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) { - return(0); - } -#endif - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { panic("register classification not implemented"); return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); diff --git a/base/inifile.cc b/base/inifile.cc index 92d88c09b..d5436fba8 100644 --- a/base/inifile.cc +++ b/base/inifile.cc @@ -400,16 +400,9 @@ IniFile::printUnreferenced() } } else { -#if 0 - if (section->findEntry("unref_entries_ok") == NULL) { - bool unrefEntries = section->printUnreferenced(sectionName); - unref = unref || unrefEntries; - } -#else if (section->printUnreferenced(sectionName)) { unref = true; } -#endif } } diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index 5946ced2f..e5d9df6de 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -120,9 +120,6 @@ class BaseCPU : public SimObject System *system; #endif - virtual bool filterThisInstructionPrefetch(int thread_number, - short asid, Addr prefetchTarget) const { return true; } - /** * Return pointer to CPU's branch predictor (NULL if none). * @return Branch predictor pointer. diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index ddfc53684..4a2688f1c 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -218,7 +218,7 @@ class ExecContext cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { - // Don't update result register (see machine.def) + // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { @@ -239,12 +239,11 @@ class ExecContext } } - // Need to clear any locked flags on other proccessors for this - // address - // Only do this for succsful Store Conditionals and all other - // stores (WH64?) - // Unsuccesful Store Conditionals would have returned above, - // and wouldn't fall through + // Need to clear any locked flags on other proccessors for + // this address. Only do this for succsful Store Conditionals + // and all other stores (WH64?). Unsuccessful Store + // Conditionals would have returned above, and wouldn't fall + // through. for (int i = 0; i < system->xcvec.size(); i++){ cregs = &system->xcvec[i]->regs.miscRegs; if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh index 8e2ea6221..d05dbe0cd 100644 --- a/cpu/exetrace.hh +++ b/cpu/exetrace.hh @@ -43,19 +43,6 @@ class BaseCPU; namespace Trace { -#if 0 - static const FlagVec ALL = ULL(0x1); - static const FlagVec FULL = ULL(0x2); - static const FlagVec SYMBOLS = ULL(0x4); - static const FlagVec EXTENDED = ULL(0x8); - static const FlagVec BRANCH_TAKEN = ULL(0x10); - static const FlagVec BRANCH_NOTTAKEN = ULL(0x20); - static const FlagVec CALLPAL = ULL(0x40); - static const FlagVec SPECULATIVE = ULL(0x100); - static const FlagVec OMIT_COUNT = ULL(0x200); - static const FlagVec INCLUDE_THREAD_NUM = ULL(0x400); -#endif - class InstRecord : public Record { protected: diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 28009b7f0..20790bfb6 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -192,8 +192,10 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process, memReq = new MemReq(); memReq->xc = xc; memReq->asid = 0; + memReq->data = new uint8_t[64]; numInst = 0; + numLoad = 0; last_idle = 0; lastIcacheStall = 0; lastDcacheStall = 0; @@ -406,7 +408,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (fault == No_Fault && dcacheInterface) { memReq->cmd = Write; - memReq->data = (uint8_t *)&data; + memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; memReq->flags &= ~UNCACHEABLE; diff --git a/util/sort-includes b/util/sort-includes new file mode 100755 index 000000000..8ae40be52 --- /dev/null +++ b/util/sort-includes @@ -0,0 +1,91 @@ +#! /usr/bin/env perl +# Copyright (c) 2003 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +open (FOO, "<$ARGV[0]") or die; + +# Suck in everything before the first include +# (line-by-line into @before list). +while (($_ = <FOO>) && !/^#include/) { + push @before, $_; +} + +#print join("", @before); +#print "##########################\n"; + +# Suck in include lines into @includes list. +# Skip blank lines (keep processing, but don't put in @includes). +# End on first non-blank, non-include line. +# Note that this means that files with comments or #ifdefs +# interspersed among their #includes will only get the initial +# set of #includes sorted. +do { + push @includes, $_ unless /^\s*$/; +} while (($_ = <FOO>) && /^#include|^\s*$/); + +# Now sort the includes. This simple ordering function +# puts system includes first, followed by non-system includes. +# Within each group the sort is alphabetical. +# We may want something a little more sophisticated. +# Personally, I'd like to see something like: +# <sys/*.h> - header files from sys subdir +# <*.h> - other system headers +# <*> - STL headers +# "base/*" - M5 base headers +# "sim/*" - M5 sim headers +# "*" - other M5 headers +# ...but I didn't have the energy to code that up. +sub sortorder { + my $sysa = ($a =~ /<.*>/); + my $sysb = ($b =~ /<.*>/); + return -1 if ($sysa && !$sysb); + return 1 if ($sysb && !$sysa); + return $a cmp $b; +} + +@includes = sort sortorder @includes; +#print join("", @includes); +#print "##########################\n"; + +# Put everything after the includes in the @after list. +do { + push @after, $_; + if (/^#include/) { + print "$ARGV[0]: "; + print $after[0]; + exit 0; + } +} while ($_ = <FOO>); + +#print join("", @after); +#print "##########################\n"; + +# Print out the file with sorted includes. + +print join("", @before, @includes, @after); + |