diff options
| -rw-r--r-- | src/arch/arm/isa.cc | 5 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 67062be41..87203c3f0 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -173,11 +173,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) cpsr.t = pc.thumb() ? 1 : 0; return cpsr; } - if (misc_reg >= MISCREG_CP15_UNIMP_START && - misc_reg < MISCREG_CP15_END) { + if (misc_reg >= MISCREG_CP15_UNIMP_START) panic("Unimplemented CP15 register %s read.\n", miscRegName[misc_reg]); - } + switch (misc_reg) { case MISCREG_CLIDR: warn_once("The clidr register always reports 0 caches.\n"); diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 2d47c286f..c2003fe6d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -180,6 +180,10 @@ let {{ // Read/write, priveleged only. default: + if (miscReg >= MISCREG_CP15_UNIMP_START) + return new FailUnimplemented(csprintf("%s %s", + isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(), + machInst); if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); } else { |