diff options
134 files changed, 57450 insertions, 1341 deletions
diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc index f7fd92c15..fd8f781e4 100644 --- a/src/arch/alpha/vtophys.cc +++ b/src/arch/alpha/vtophys.cc @@ -141,12 +141,12 @@ void AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; + char *start = dst; VirtualPort *vp = tc->getVirtPort(tc); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); - len++; - } while (len < maxlen && dst[len] != 0 ); + } while (len < maxlen && start[len++] != 0 ); tc->delVirtPort(vp); dst[len] = 0; diff --git a/src/base/traceflags.py b/src/base/traceflags.py index f871ce35f..757c9e7b7 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -94,6 +94,7 @@ baseFlags = [ 'Flow', 'FreeList', 'FullCPU', + 'FunctionalAccess', 'GDBAcc', 'GDBExtra', 'GDBMisc', @@ -122,6 +123,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'MemoryAccess', 'O3CPU', 'OzoneCPU', 'OzoneLSQ', diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index f42f0f8e2..024cd7e41 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -360,7 +360,11 @@ MemTest::tick() //For now we only allow one outstanding request per addreess per tester //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. - if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return; + if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { + delete result; + delete req; + return; + } else outstandingAddrs.insert(paddr); // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin @@ -395,7 +399,12 @@ MemTest::tick() //For now we only allow one outstanding request per addreess per tester //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. - if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return; + if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { + delete [] result; + delete req; + return; + } + else outstandingAddrs.insert(paddr); /* diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 072580af7..147c670de 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1285,8 +1285,8 @@ template<class Impl> void DefaultFetch<Impl>::recvRetry() { - assert(cacheBlocked); if (retryPkt != NULL) { + assert(cacheBlocked); assert(retryTid != -1); assert(fetchStatus[retryTid] == IcacheWaitRetry); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 490be20ae..fe421ae6c 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -182,9 +182,9 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) void AtomicSimpleCPU::resume() { - assert(system->getMemoryMode() == System::Atomic); changeState(SimObject::Running); if (thread->status() == ThreadContext::Active) { + assert(system->getMemoryMode() == System::Atomic); if (!tickEvent.scheduled()) tickEvent.schedule(curTick); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 33f673cbc..ad5c0e5d6 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -147,6 +147,8 @@ void TimingSimpleCPU::resume() { if (_status != SwitchedOut && _status != Idle) { + assert(system->getMemoryMode() == System::Timing); + // Delete the old event if it existed. if (fetchEvent) { if (fetchEvent->scheduled()) @@ -160,7 +162,6 @@ TimingSimpleCPU::resume() fetchEvent->schedule(curTick); } - assert(system->getMemoryMode() == System::Timing); changeState(SimObject::Running); previousTick = curTick; } diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 75ffed0d2..b11b6de58 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -320,7 +320,7 @@ Bus::functionalSnoop(Packet *pkt) { std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); - while (!ports.empty()) + while (!ports.empty() && pkt->result != Packet::Success) { interfaces[ports.back()]->sendFunctional(pkt); ports.pop_back(); @@ -367,7 +367,10 @@ Bus::recvFunctional(Packet *pkt) pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); functionalSnoop(pkt); - findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt); + + // If the snooping found what we were looking for, we're done. + if (pkt->result != Packet::Success) + findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt); } /** Function called by the port when the bus is receiving a status change.*/ diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 71ea58416..3f7a52fab 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -107,6 +107,42 @@ BaseCache::CachePort::recvAtomic(Packet *pkt) void BaseCache::CachePort::recvFunctional(Packet *pkt) { + //Check storage here first + list<Packet *>::iterator i = drainList.begin(); + list<Packet *>::iterator end = drainList.end(); + for (; i != end; ++i) { + Packet * target = *i; + // If the target contains data, and it overlaps the + // probed request, need to update data + if (target->intersect(pkt)) { + uint8_t* pkt_data; + uint8_t* write_data; + int data_size; + if (target->getAddr() < pkt->getAddr()) { + int offset = pkt->getAddr() - target->getAddr(); + pkt_data = pkt->getPtr<uint8_t>(); + write_data = target->getPtr<uint8_t>() + offset; + data_size = target->getSize() - offset; + assert(data_size > 0); + if (data_size > pkt->getSize()) + data_size = pkt->getSize(); + } else { + int offset = target->getAddr() - pkt->getAddr(); + pkt_data = pkt->getPtr<uint8_t>() + offset; + write_data = target->getPtr<uint8_t>(); + data_size = pkt->getSize() - offset; + assert(data_size > pkt->getSize()); + if (data_size > target->getSize()) + data_size = target->getSize(); + } + + if (pkt->isWrite()) { + memcpy(pkt_data, write_data, data_size); + } else { + memcpy(write_data, pkt_data, data_size); + } + } + } cache->doFunctionalAccess(pkt, isCpuSide); } @@ -153,7 +189,6 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - pkt = NULL; BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); reqCpu->schedule(curTick + 1); } @@ -166,12 +201,13 @@ BaseCache::CachePort::recvRetry() pkt = cshrRetry; bool success = sendTiming(pkt); waitingOnRetry = !success; - if (success && cache->doSlaveRequest()) + if (success) { - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); - reqCpu->schedule(curTick + 1); + if (cache->doSlaveRequest()) { + //Still more to issue, rerequest in 1 cycle + BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this); + reqCpu->schedule(curTick + 1); + } cshrRetry = NULL; } } @@ -269,20 +305,28 @@ BaseCache::CacheEvent::process() } else { - assert(cachePort->cache->doSlaveRequest()); //CSHR - pkt = cachePort->cache->getCoherencePacket(); + if (!cachePort->cshrRetry) { + assert(cachePort->cache->doSlaveRequest()); + pkt = cachePort->cache->getCoherencePacket(); + } + else { + pkt = cachePort->cshrRetry; + } bool success = cachePort->sendTiming(pkt); if (!success) { //Need to send on a retry cachePort->cshrRetry = pkt; cachePort->waitingOnRetry = true; } - else if (cachePort->cache->doSlaveRequest()) + else { - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); + cachePort->cshrRetry = NULL; + if (cachePort->cache->doSlaveRequest()) { + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + this->schedule(curTick+1); + } } } return; diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 563b1ca8b..455e13d9c 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -212,10 +212,6 @@ class BaseCache : public MemObject protected: - /** True if this cache is connected to the CPU. */ - bool topLevelCache; - - /** Stores time the cache blocked for statistics. */ Tick blockedCycle; @@ -337,7 +333,7 @@ class BaseCache : public MemObject */ BaseCache(const std::string &name, Params ¶ms) : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0), - slaveRequests(0), topLevelCache(false), blkSize(params.blkSize), + slaveRequests(0), blkSize(params.blkSize), missCount(params.maxMisses) { //Start ports at null if more than one is created we should panic @@ -358,15 +354,6 @@ class BaseCache : public MemObject } /** - * Returns true if this cache is connect to the CPU. - * @return True if this is a L1 cache. - */ - bool isTopLevel() - { - return topLevelCache; - } - - /** * Returns true if the cache is blocked for accesses. */ bool isBlocked() @@ -561,8 +548,6 @@ class BaseCache : public MemObject */ void respondToSnoop(Packet *pkt, Tick time) { -// assert("Implement\n" && 0); -// mi->respond(pkt,curTick + hitLatency); assert (pkt->needsResponse()); CacheEvent *reqMem = new CacheEvent(memSidePort, pkt); reqMem->schedule(time); @@ -585,15 +570,7 @@ class BaseCache : public MemObject { //This is where snoops get updated AddrRangeList dummy; -// if (!topLevelCache) -// { - cpuSidePort->getPeerAddressRanges(dummy, snoop); -// } -// else -// { -// snoop.push_back(RangeSize(0,-1)); -// } - + cpuSidePort->getPeerAddressRanges(dummy, snoop); return; } } diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index a75c9611d..078c82d82 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -38,8 +38,6 @@ #include "sim/root.hh" // for Tick #include "arch/isa_traits.hh" // for Addr -#include <iostream> - /** * Cache block status bit assignments */ @@ -180,21 +178,4 @@ class CacheBlk }; -/** - * Output a CacheBlk to the given ostream. - * @param out The stream for the output. - * @param blk The cache block to print. - * - * @return The output stream. - */ -inline std::ostream & -operator<<(std::ostream &out, const CacheBlk &blk) -{ - out << std::hex << std::endl; - out << " Tag: " << blk.tag << std::endl; - out << " Status: " << blk.status << std::endl; - - return(out << std::dec); -} - #endif //__CACHE_BLK_HH__ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index a68418f24..9db79b843 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -151,12 +151,7 @@ Cache(const std::string &_name, doCopy(params.doCopy), blockOnCopy(params.blockOnCopy), hitLatency(params.hitLatency) { -//FIX BUS POINTERS -// if (params.in == NULL) { - topLevelCache = true; -// } -//PLEASE FIX THIS, BUS SIZES NOT BEING USED - tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/); + tags->setCache(this); tags->setPrefetcher(prefetcher); missQueue->setCache(this); missQueue->setPrefetcher(prefetcher); @@ -389,10 +384,15 @@ template<class TagStore, class Buffering, class Coherence> void Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) { + if (pkt->req->isUncacheable()) { + //Can't get a hit on an uncacheable address + //Revisit this for multi level coherence + return; + } Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); MSHR *mshr = missQueue->findMSHR(blk_addr); - if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req + if (coherence->hasProtocol()) { //@todo Move this into handle bus req //If we find an mshr, and it is in service, we need to NACK or invalidate if (mshr) { if (mshr->inService) { diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 5ab706269..0efe393f9 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -68,14 +68,12 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr, if (pkt->isInvalidate()) { DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n", pkt->getAddr(), blk); - if (!cache->isTopLevel()) { - // Forward to other caches - Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); - cshrs.allocate(tmp); - cache->setSlaveRequest(Request_Coherence, curTick); - if (cshrs.isFull()) { - cache->setBlockedForSnoop(Blocked_Coherence); - } + // Forward to other caches + Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + cshrs.allocate(tmp); + cache->setSlaveRequest(Request_Coherence, curTick); + if (cshrs.isFull()) { + cache->setBlockedForSnoop(Blocked_Coherence); } } else { if (blk) { diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index c7b0e0890..c23b542f5 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher) MSHR* MissQueue::allocateMiss(Packet * &pkt, int size, Tick time) { - MSHR* mshr = mq.allocate(pkt, blkSize); + MSHR* mshr = mq.allocate(pkt, size); mshr->order = order++; if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) { // Mark this as a cache line fill diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 4758fda89..64c65dcca 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -34,8 +34,11 @@ * Definition of the Packet Class, a packet is a transaction occuring * between a single level of the memory heirarchy (ie L1->L2). */ + +#include <iostream> #include "base/misc.hh" #include "mem/packet.hh" +#include "base/trace.hh" static const std::string ReadReqString("ReadReq"); static const std::string WriteReqString("WriteReq"); @@ -139,5 +142,93 @@ Packet::intersect(Packet *p) bool fixPacket(Packet *func, Packet *timing) { - panic("Need to implement!"); + Addr funcStart = func->getAddr(); + Addr funcEnd = func->getAddr() + func->getSize() - 1; + Addr timingStart = timing->getAddr(); + Addr timingEnd = timing->getAddr() + timing->getSize() - 1; + + assert(!(funcStart > timingEnd || timingStart < funcEnd)); + + if (DTRACE(FunctionalAccess)) { + DebugOut() << func; + DebugOut() << timing; + } + + // this packet can't solve our problem, continue on + if (!timing->hasData()) + return true; + + if (func->isRead()) { + if (funcStart >= timingStart && funcEnd <= timingEnd) { + func->allocate(); + memcpy(func->getPtr<uint8_t>(), timing->getPtr<uint8_t>() + + funcStart - timingStart, func->getSize()); + func->result = Packet::Success; + return false; + } else { + // In this case the timing packet only partially satisfies the + // requset, so we would need more information to make this work. + // Like bytes valid in the packet or something, so the request could + // continue and get this bit of possibly newer data along with the + // older data not written to yet. + panic("Timing packet only partially satisfies the functional" + "request. Now what?"); + } + } else if (func->isWrite()) { + if (funcStart >= timingStart) { + memcpy(timing->getPtr<uint8_t>() + (funcStart - timingStart), + func->getPtr<uint8_t>(), + funcStart - std::min(funcEnd, timingEnd)); + } else { // timingStart > funcStart + memcpy(timing->getPtr<uint8_t>(), + func->getPtr<uint8_t>() + (timingStart - funcStart), + timingStart - std::min(funcEnd, timingEnd)); + } + // we always want to keep going with a write + return true; + } else + panic("Don't know how to handle command type %#x\n", + func->cmdToIndex()); + +} + + +std::ostream & +operator<<(std::ostream &o, const Packet &p) +{ + + o << "[0x"; + o.setf(std::ios_base::hex, std::ios_base::showbase); + o << p.getAddr(); + o.unsetf(std::ios_base::hex| std::ios_base::showbase); + o << ":"; + o.setf(std::ios_base::hex, std::ios_base::showbase); + o << p.getAddr() + p.getSize() - 1 << "] "; + o.unsetf(std::ios_base::hex| std::ios_base::showbase); + + if (p.result == Packet::Success) + o << "Successful "; + if (p.result == Packet::BadAddress) + o << "BadAddress "; + if (p.result == Packet::Nacked) + o << "Nacked "; + if (p.result == Packet::Unknown) + o << "Inflight "; + + if (p.isRead()) + o << "Read "; + if (p.isWrite()) + o << "Read "; + if (p.isInvalidate()) + o << "Read "; + if (p.isRequest()) + o << "Request "; + if (p.isResponse()) + o << "Response "; + if (p.hasData()) + o << "w/Data "; + + o << std::endl; + return o; } + diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 7ede48bfd..48b32ec47 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -171,17 +171,17 @@ class Packet // as well. enum CommandAttribute { - IsRead = 1 << 0, - IsWrite = 1 << 1, - IsPrefetch = 1 << 2, - IsInvalidate = 1 << 3, - IsRequest = 1 << 4, - IsResponse = 1 << 5, - NeedsResponse = 1 << 6, + IsRead = 1 << 0, + IsWrite = 1 << 1, + IsPrefetch = 1 << 2, + IsInvalidate = 1 << 3, + IsRequest = 1 << 4, + IsResponse = 1 << 5, + NeedsResponse = 1 << 6, IsSWPrefetch = 1 << 7, IsHWPrefetch = 1 << 8, IsUpgrade = 1 << 9, - HasData = 1 << 10 + HasData = 1 << 10 }; public: @@ -189,18 +189,18 @@ class Packet enum Command { InvalidCmd = 0, - ReadReq = IsRead | IsRequest | NeedsResponse, - WriteReq = IsWrite | IsRequest | NeedsResponse | HasData, - WriteReqNoAck = IsWrite | IsRequest | HasData, - ReadResp = IsRead | IsResponse | NeedsResponse | HasData, - WriteResp = IsWrite | IsResponse | NeedsResponse, + ReadReq = IsRead | IsRequest | NeedsResponse, + WriteReq = IsWrite | IsRequest | NeedsResponse | HasData, + WriteReqNoAck = IsWrite | IsRequest | HasData, + ReadResp = IsRead | IsResponse | NeedsResponse | HasData, + WriteResp = IsWrite | IsResponse | NeedsResponse, Writeback = IsWrite | IsRequest | HasData, SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse, HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse, SoftPFResp = IsRead | IsResponse | IsSWPrefetch | NeedsResponse | HasData, HardPFResp = IsRead | IsResponse | IsHWPrefetch - | NeedsResponse | HasData, + | NeedsResponse | HasData, InvalidateReq = IsInvalidate | IsRequest, WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest | HasData, UpgradeReq = IsInvalidate | IsRequest | IsUpgrade, @@ -222,17 +222,17 @@ class Packet /** The command field of the packet. */ Command cmd; - bool isRead() { return (cmd & IsRead) != 0; } - bool isWrite() { return (cmd & IsWrite) != 0; } - bool isRequest() { return (cmd & IsRequest) != 0; } - bool isResponse() { return (cmd & IsResponse) != 0; } - bool needsResponse() { return (cmd & NeedsResponse) != 0; } - bool isInvalidate() { return (cmd & IsInvalidate) != 0; } - bool hasData() { return (cmd & HasData) != 0; } + bool isRead() const { return (cmd & IsRead) != 0; } + bool isWrite() const { return (cmd & IsWrite) != 0; } + bool isRequest() const { return (cmd & IsRequest) != 0; } + bool isResponse() const { return (cmd & IsResponse) != 0; } + bool needsResponse() const { return (cmd & NeedsResponse) != 0; } + bool isInvalidate() const { return (cmd & IsInvalidate) != 0; } + bool hasData() const { return (cmd & HasData) != 0; } - bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; } - bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; } - bool isCompressed() { return (flags & COMPRESSED) != 0; } + bool isCacheFill() const { return (flags & CACHE_LINE_FILL) != 0; } + bool isNoAllocate() const { return (flags & NO_ALLOCATE) != 0; } + bool isCompressed() const { return (flags & COMPRESSED) != 0; } bool nic_pkt() { assert("Unimplemented\n" && 0); return false; } @@ -401,5 +401,14 @@ class Packet bool intersect(Packet *p); }; + +/** This function given a functional packet and a timing packet either satisfies + * the timing packet, or updates the timing packet to reflect the updated state + * in the timing packet. It returns if the functional packet should continue to + * traverse the memory hierarchy or not. + */ bool fixPacket(Packet *func, Packet *timing); + +std::ostream & operator<<(std::ostream &o, const Packet &p); + #endif //__MEM_PACKET_HH diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 7303f278e..f5a0ade15 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -201,12 +201,16 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) if (pkt->req->isLocked()) { trackLoadLocked(pkt->req); } + DPRINTF(MemoryAccess, "Performing Read of size %i on address 0x%x\n", + pkt->getSize(), pkt->getAddr()); memcpy(pkt->getPtr<uint8_t>(), pmemAddr + pkt->getAddr() - params()->addrRange.start, pkt->getSize()); } else if (pkt->isWrite()) { if (writeOK(pkt->req)) { + DPRINTF(MemoryAccess, "Performing Write of size %i on address 0x%x\n", + pkt->getSize(), pkt->getAddr()); memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start, pkt->getPtr<uint8_t>(), pkt->getSize()); } diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 456878d0a..21907c0ca 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -33,8 +33,22 @@ void SimpleTimingPort::recvFunctional(Packet *pkt) { - // just do an atomic access and throw away the returned latency - recvAtomic(pkt); + //First check queued events + std::list<Packet *>::iterator i = transmitList.begin(); + std::list<Packet *>::iterator end = transmitList.end(); + bool cont = true; + + while (i != end && cont) { + Packet * target = *i; + // If the target contains data, and it overlaps the + // probed request, need to update data + if (target->intersect(pkt)) + fixPacket(pkt, target); + + } + //Then just do an atomic access and throw away the returned latency + if (cont) + recvAtomic(pkt); } bool diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index a0d66e643..716f584b0 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -726,7 +726,12 @@ class SimObject(object): child.resume() def changeTiming(self, mode): - if isinstance(self, System): + if isinstance(self, m5.objects.System): + # i don't know if there's a better way to do this - calling + # setMemoryMode directly from self._ccObject results in calling + # SimObject::setMemoryMode, not the System::setMemoryMode +## system_ptr = cc_main.convertToSystemPtr(self._ccObject) +## system_ptr.setMemoryMode(mode) self._ccObject.setMemoryMode(mode) for child in self._children.itervalues(): child.changeTiming(mode) diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 5717b49b6..03e0508fb 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -144,7 +144,7 @@ def restoreCheckpoint(root, dir): resume(root) def changeToAtomic(system): - if not isinstance(system, objects.Root) and not isinstance(system, System): + if not isinstance(system, objects.Root) and not isinstance(system, objects.System): raise TypeError, "Object is not a root or system object. Checkpoint must be " "called on a root object." doDrain(system) @@ -153,7 +153,7 @@ def changeToAtomic(system): resume(system) def changeToTiming(system): - if not isinstance(system, objects.Root) and not isinstance(system, System): + if not isinstance(system, objects.Root) and not isinstance(system, objects.System): raise TypeError, "Object is not a root or system object. Checkpoint must be " "called on a root object." doDrain(system) @@ -162,6 +162,7 @@ def changeToTiming(system): resume(system) def switchCpus(cpuList): + print "switching cpus" if not isinstance(cpuList, list): raise RuntimeError, "Must pass a list to this function" for i in cpuList: @@ -189,9 +190,9 @@ def switchCpus(cpuList): cc_main.cleanupCountedDrain(drain_event) # Now all of the CPUs are ready to be switched out for old_cpu in old_cpus: + print "switching" old_cpu._ccObject.switchOut() index = 0 - print "Switching CPUs" for new_cpu in new_cpus: new_cpu.takeOverFrom(old_cpus[index]) new_cpu._ccObject.resume() diff --git a/src/sim/main.cc b/src/sim/main.cc index 874d0ac85..8bb0d7aaa 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -66,6 +66,7 @@ #include "sim/sim_events.hh" #include "sim/sim_exit.hh" #include "sim/sim_object.hh" +#include "sim/system.hh" #include "sim/stat_control.hh" #include "sim/stats.hh" #include "sim/root.hh" @@ -440,6 +441,17 @@ convertToBaseCPUPtr(SimObject *obj) return ptr; } +System * +convertToSystemPtr(SimObject *obj) +{ + System *ptr = dynamic_cast<System *>(obj); + + if (ptr == NULL) + warn("Casting to System pointer failed"); + return ptr; +} + + /** * Do C++ simulator exit processing. Exported to SWIG to be invoked * when simulator terminates via Python's atexit mechanism. diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh index 38f2bdd23..32807b69d 100644 --- a/src/sim/sim_object.hh +++ b/src/sim/sim_object.hh @@ -64,6 +64,13 @@ class SimObject : public Serializable, protected StartupCallback Draining, Drained }; + + enum MemoryMode { + Invalid=0, + Atomic, + Timing + }; + private: State state; diff --git a/src/sim/system.hh b/src/sim/system.hh index 3ab1d81f2..827fe5c78 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -62,22 +62,16 @@ class RemoteGDB; class System : public SimObject { public: - enum MemoryMode { - Invalid=0, - Atomic, - Timing - }; static const char *MemoryModeStrings[3]; - - MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; } + SimObject::MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; } /** Change the memory mode of the system. This should only be called by the * python!! * @param mode Mode to change to (atomic/timing) */ - void setMemoryMode(MemoryMode mode); + void setMemoryMode(SimObject::MemoryMode mode); PhysicalMemory *physmem; PCEventQueue pcEventQueue; @@ -126,7 +120,7 @@ class System : public SimObject protected: - MemoryMode memoryMode; + SimObject::MemoryMode memoryMode; #if FULL_SYSTEM /** @@ -173,7 +167,7 @@ class System : public SimObject { std::string name; PhysicalMemory *physmem; - MemoryMode mem_mode; + SimObject::MemoryMode mem_mode; #if FULL_SYSTEM Tick boot_cpu_frequency; diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 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+system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 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82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/00.gzip/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/00.gzip/test.py b/tests/long/00.gzip/test.py new file mode 100644 index 000000000..7a74a0b0a --- /dev/null +++ b/tests/long/00.gzip/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'gzip smred.log 1', + executable = binpath('gzip')) diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py new file mode 100644 index 000000000..af2536c7e --- /dev/null +++ b/tests/long/10.mcf/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'mcf lgred.in', + executable = binpath('mcf')) diff --git a/tests/long/20.parser/test.py b/tests/long/20.parser/test.py new file mode 100644 index 000000000..0b142db25 --- /dev/null +++ b/tests/long/20.parser/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'parser 2.1.dict -batch < lgred.in', + executable = binpath('parser')) diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 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+system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/30.eon/test.py b/tests/long/30.eon/test.py new file mode 100644 index 000000000..b9f0c2b51 --- /dev/null +++ b/tests/long/30.eon/test.py @@ -0,0 +1,29 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook',executable = binpath('eon')) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/40.perlbmk/test.py b/tests/long/40.perlbmk/test.py new file mode 100644 index 000000000..b5cd17251 --- /dev/null +++ b/tests/long/40.perlbmk/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'perlbmk -I./lib lgred.makerand.pl', + executable = binpath('perlbmk')) diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 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+system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 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82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/50.vortex/test.py b/tests/long/50.vortex/test.py new file mode 100644 index 000000000..f531b8ac8 --- /dev/null +++ b/tests/long/50.vortex/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'vortex smred.raw', + executable = binpath('vortex')) diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/60.bzip2/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/60.bzip2/test.py b/tests/long/60.bzip2/test.py new file mode 100644 index 000000000..3f16efa09 --- /dev/null +++ b/tests/long/60.bzip2/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'bzip2 lgred.source', + executable = binpath('bzip2')) diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 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+system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 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82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-atomic/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini new file mode 100644 index 000000000..c3a59fbce --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.ini @@ -0,0 +1,417 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt new file mode 100644 index 000000000..5d4f9235a --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout new file mode 100644 index 000000000..fbb329a2f --- /dev/null +++ b/tests/long/70.twolf/ref/alpha/linux/simple-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py new file mode 100644 index 000000000..4ec7a3d03 --- /dev/null +++ b/tests/long/70.twolf/test.py @@ -0,0 +1,30 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +root.system.cpu.workload = LiveProcess(cmd = 'twolf smred/smred', + executable = binpath('twolf')) diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 59cda42d9..608fb0be9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1936 # Number of BTB lookups -global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted -global.BPredUnit.lookups 2254 # Number of BP lookups -global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 46995 # Simulator instruction rate (inst/s) -host_mem_usage 160420 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 57256 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 682 # Number of BTB hits +global.BPredUnit.BTBLookups 2437 # Number of BTB lookups +global.BPredUnit.RASInCorrect 76 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1570 # Number of conditional branches predicted +global.BPredUnit.lookups 5322 # Number of BP lookups +global.BPredUnit.usedRAS 2820 # Number of times the RAS was used to get a target. +host_inst_rate 1288 # Simulator instruction rate (inst/s) +host_mem_usage 180572 # Number of bytes of host memory used +host_seconds 4.37 # Real time elapsed on the host +host_tick_rate 322418 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 27 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 144 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 3819 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3727 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6868 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 1408131 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6115 +system.cpu.commit.COM:committed_per_cycle.samples 58722 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6390.84% - 1 1063 1738.35% - 2 389 636.14% - 3 210 343.42% - 4 152 248.57% - 5 94 153.72% - 6 76 124.28% - 7 149 243.66% - 8 74 121.01% + 0 56096 9552.81% + 1 1495 254.59% + 2 457 77.82% + 3 225 38.32% + 4 133 22.65% + 5 92 15.67% + 6 98 16.69% + 7 32 5.45% + 8 94 16.01% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 374 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13826 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses +system.cpu.cpi 250.423439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 250.423439 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6940.988166 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6843.030303 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1173027 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.105823 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 677460 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.061991 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5305.074803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5141.328767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 558 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1347489 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.312808 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 254 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 181 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 375317 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets 3389.604651 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.546512 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 43 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 145753 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses -system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2409 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5958.666667 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1986 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2520516 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.175592 # miss rate for demand accesses +system.cpu.dcache.demand_misses 423 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 251 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1052777 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071399 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 172 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2040 # number of overall hits -system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses -system.cpu.dcache.overall_misses 308 # number of overall misses -system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses +system.cpu.dcache.overall_accesses 2409 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5958.666667 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 6120.796512 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 1986 # number of overall hits +system.cpu.dcache.overall_miss_latency 2520516 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.175592 # miss rate for overall accesses +system.cpu.dcache.overall_misses 423 # number of overall misses +system.cpu.dcache.overall_mshr_hits 251 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1052777 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071399 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,91 +119,91 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use -system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 101.103948 # Cycle average of tags in use +system.cpu.dcache.total_refs 1986 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 16535 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 29787 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 36497 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 5653 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2641 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 38 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 5322 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 6542 # Number of cache lines fetched +system.cpu.fetch.Cycles 21461 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 388 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 35708 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.086728 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 6542 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 3502 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.581905 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6869 +system.cpu.fetch.rateDist.samples 61364 system.cpu.fetch.rateDist.min_value 0 - 0 4548 6621.05% - 1 174 253.31% - 2 186 270.78% - 3 157 228.56% - 4 211 307.18% - 5 153 222.74% - 6 171 248.94% - 7 105 152.86% - 8 1164 1694.57% + 0 54337 8854.87% + 1 197 32.10% + 2 585 95.33% + 3 1433 233.52% + 4 1461 238.09% + 5 241 39.27% + 6 330 53.78% + 7 1227 199.95% + 8 1553 253.08% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 6541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5110.042601 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4297.762058 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6095 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 2279079 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.068185 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 446 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 135 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1336604 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047546 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3658.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 19.598071 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 25610 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses -system.cpu.icache.demand_misses 327 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 6541 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5110.042601 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency +system.cpu.icache.demand_hits 6095 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 2279079 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.068185 # miss rate for demand accesses +system.cpu.icache.demand_misses 446 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1336604 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047546 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1255 # number of overall hits -system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses -system.cpu.icache.overall_misses 327 # number of overall misses -system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_accesses 6541 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5110.042601 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4297.762058 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 6095 # number of overall hits +system.cpu.icache.overall_miss_latency 2279079 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.068185 # miss rate for overall accesses +system.cpu.icache.overall_misses 446 # number of overall misses +system.cpu.icache.overall_mshr_hits 135 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1336604 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047546 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use -system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 147.733346 # Cycle average of tags in use +system.cpu.icache.total_refs 6095 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate -system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 985 # Number of stores executed +system.cpu.idleCycles 1346768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2391 # Number of branches executed +system.cpu.iew.EXEC:nop 45 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.222997 # Inst execution rate +system.cpu.iew.EXEC:refs 5561 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2148 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5409 # num instructions consuming a value -system.cpu.iew.WB:count 7670 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back +system.cpu.iew.WB:consumers 6673 # num instructions consuming a value +system.cpu.iew.WB:count 11743 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790499 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4025 # num instructions producing a value -system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle -system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 5275 # num instructions producing a value +system.cpu.iew.WB:rate 0.191366 # insts written-back per cycle +system.cpu.iew.WB:sent 11811 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 6301 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3819 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2540 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3727 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19466 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3413 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 276 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 13684 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2641 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 1736 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 45 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 2840 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2915 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.003993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.003993 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 13960 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5573 66.67% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 21.02% # Type of FU issued - MemWrite 1024 12.25% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued +(null) 2 0.01% # Type of FU issued +IntAlu 8277 59.29% # Type of FU issued +IntMult 1 0.01% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 2 0.01% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 3509 25.14% # Type of FU issued +MemWrite 2169 15.54% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006662 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 0.87% # attempts to use FU when none available + IntAlu 3 3.23% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,78 +297,78 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 76 66.09% # attempts to use FU when none available - MemWrite 38 33.04% # attempts to use FU when none available + MemRead 54 58.06% # attempts to use FU when none available + MemWrite 36 38.71% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6869 +system.cpu.iq.ISSUE:issued_per_cycle.samples 61364 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3761 5475.32% - 1 891 1297.13% - 2 720 1048.19% - 3 617 898.24% - 4 445 647.84% - 5 278 404.72% - 6 104 151.40% - 7 41 59.69% - 8 12 17.47% + 0 54449 8873.12% + 1 3310 539.40% + 2 1268 206.64% + 3 1704 277.69% + 4 325 52.96% + 5 194 31.61% + 6 79 12.87% + 7 22 3.59% + 8 13 2.12% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate -system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.iq.ISSUE:rate 0.227495 # Inst issue rate +system.cpu.iq.iqInstsAdded 19398 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 13960 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 13240 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 66 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 9412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4537.301455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2307.006237 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2182442 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995859 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1109670 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004065 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004158 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 494 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4537.301455 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995951 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2182442 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995859 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995951 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1109670 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 494 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4537.301455 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2307.006237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995951 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 492 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2182442 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995859 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 481 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1109670 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,28 +381,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 248.876875 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6869 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.numCycles 61364 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 6939 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 36651 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 36093 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 29280 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 20221 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 5480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2641 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 493 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 16170 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 9160 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 927 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.timesIdled 369 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 558105896..0ca948630 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -8,5 +8,7904 @@ warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. +warn: cycle 252001: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252002: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252017: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252018: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252019: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252062: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252063: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252064: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252065: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252066: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 252067: fault (page_table_fault) detected @ PC 0x000000 warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. +warn: cycle 1252071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1252999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1253999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1254999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1255999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1256999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1257999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1258999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259004: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259005: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259006: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259007: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259008: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259009: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259010: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259011: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259012: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259013: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259014: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259015: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259016: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259017: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259018: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259019: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259020: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259021: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259022: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259023: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259024: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259025: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259026: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259027: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259028: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259029: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259030: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259031: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259032: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259033: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259034: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259035: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259036: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259037: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259038: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259039: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259040: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259041: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259042: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259043: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259044: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259045: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259046: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259047: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259048: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259049: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259050: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259051: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259052: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259053: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259054: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259055: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259056: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259057: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259058: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259059: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259060: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259061: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259062: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259063: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259064: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259065: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259066: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259067: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259068: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259069: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259070: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259071: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259072: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259073: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259074: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259075: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259076: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259077: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259078: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259079: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259080: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259081: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259082: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259083: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259084: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259085: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259086: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259087: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259088: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259089: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259090: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259091: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259092: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259093: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259094: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259095: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259096: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259097: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259098: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259099: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259100: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259101: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259102: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259103: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259104: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259105: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259106: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259107: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259108: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259109: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259110: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259111: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259112: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259113: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259114: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259115: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259116: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259117: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259118: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259119: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259120: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259121: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259122: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259123: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259124: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259125: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259126: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259127: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259128: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259129: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259130: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259131: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259132: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259133: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259134: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259135: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259136: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259137: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259138: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259139: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259140: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259141: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259142: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259143: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259144: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259145: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259146: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259147: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259148: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259149: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259150: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259151: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259152: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259153: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259154: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259155: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259156: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259157: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259158: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259159: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259160: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259161: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259162: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259163: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259164: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259165: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259166: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259167: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259168: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259169: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259170: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259171: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259172: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259173: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259174: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259175: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259176: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259177: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259178: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259179: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259180: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259181: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259182: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259183: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259184: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259185: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259186: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259187: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259188: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259189: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259190: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259191: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259192: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259193: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259194: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259195: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259196: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259197: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259198: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259199: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259200: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259201: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259202: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259203: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259204: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259205: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259206: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259207: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259208: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259209: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259210: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259211: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259212: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259213: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259214: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259215: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259216: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259217: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259218: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259219: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259220: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259221: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259222: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259223: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259224: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259225: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259226: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259227: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259228: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259229: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259230: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259231: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259232: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259233: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259234: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259235: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259236: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259237: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259238: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259239: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259240: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259241: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259242: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259243: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259244: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259245: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259246: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259247: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259248: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259249: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259250: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259251: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259252: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259253: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259254: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259255: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259256: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259257: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259258: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259259: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259260: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259261: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259262: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259263: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259264: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259265: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259266: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259267: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259268: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259269: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259270: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259271: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259272: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259273: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259274: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259275: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259276: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259277: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259278: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259279: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259280: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259281: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259282: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259283: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259284: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259285: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259286: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259287: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259288: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259289: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259290: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259291: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259292: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259293: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259294: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259295: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259296: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259297: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259298: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259299: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259300: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259301: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259302: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259303: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259304: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259305: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259306: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259307: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259308: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259309: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259310: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259311: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259312: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259313: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259314: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259315: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259316: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259317: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259318: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259319: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259320: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259321: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259322: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259323: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259324: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259325: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259326: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259327: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259328: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259329: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259330: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259331: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259332: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259333: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259334: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259335: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259336: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259337: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259338: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259339: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259340: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259341: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259342: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259343: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259344: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259345: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259346: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259347: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259348: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259349: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259350: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259351: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259352: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259353: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259354: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259355: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259356: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259357: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259358: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259359: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259360: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259361: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259362: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259363: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259364: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259365: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259366: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259367: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259368: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259369: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259370: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259371: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259372: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259373: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259374: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259375: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259376: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259377: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259378: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259379: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259380: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259381: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259382: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259383: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259384: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259385: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259386: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259387: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259388: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259389: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259390: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259391: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259392: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259393: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259394: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259395: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259396: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259397: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259398: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259399: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259400: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259401: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259402: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259403: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259404: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259405: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259406: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259407: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259408: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259409: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259410: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259411: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259412: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259413: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259414: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259415: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259416: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259417: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259418: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259419: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259420: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259421: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259422: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259423: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259424: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259425: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259426: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259427: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259428: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259429: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259430: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259431: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259432: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259433: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259434: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259435: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259436: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259437: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259438: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259439: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259440: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259441: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259442: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259443: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259444: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259445: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259446: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259447: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259448: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259449: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259450: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259451: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259452: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259453: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259454: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259455: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259456: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259457: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259458: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259459: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259460: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259461: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259462: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259463: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259464: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259465: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259466: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259467: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259468: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259469: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259470: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259471: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259472: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259473: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259474: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259475: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259476: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259477: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259478: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259479: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259480: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259481: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259482: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259483: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259484: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259485: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259486: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259487: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259488: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259489: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259490: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259491: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259492: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259493: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259494: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259495: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259496: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259497: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259498: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259499: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259500: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259501: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259502: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259503: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259504: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259505: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259506: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259507: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259508: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259509: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259510: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259511: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259512: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259513: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259514: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259515: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259516: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259517: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259518: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259519: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259520: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259521: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259522: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259523: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259524: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259525: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259526: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259527: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259528: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259529: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259530: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259531: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259532: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259533: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259534: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259535: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259536: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259537: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259538: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259539: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259540: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259541: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259542: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259543: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259544: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259545: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259546: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259547: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259548: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259549: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259550: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259551: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259552: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259553: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259554: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259555: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259556: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259557: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259558: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259559: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259560: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259561: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259562: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259563: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259564: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259565: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259566: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259567: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259568: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259569: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259570: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259571: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259572: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259573: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259574: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259575: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259576: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259577: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259578: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259579: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259580: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259581: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259582: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259583: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259584: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259585: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259586: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259587: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259588: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259589: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259590: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259591: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259592: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259593: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259594: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259595: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259596: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259597: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259598: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259599: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259600: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259601: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259602: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259603: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259604: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259605: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259606: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259607: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259608: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259609: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259610: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259611: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259612: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259613: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259614: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259615: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259616: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259617: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259618: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259619: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259620: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259621: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259622: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259623: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259624: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259625: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259626: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259627: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259628: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259629: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259630: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259631: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259632: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259633: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259634: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259635: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259636: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259637: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259638: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259639: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259640: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259641: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259642: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259643: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259644: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259645: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259646: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259647: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259648: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259649: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259650: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259651: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259652: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259653: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259654: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259655: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259656: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259657: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259658: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259659: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259660: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259661: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259662: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259663: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259664: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259665: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259666: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259667: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259668: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259669: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259670: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259671: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259672: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259673: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259674: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259675: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259676: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259677: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259678: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259679: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259680: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259681: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259682: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259683: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259684: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259685: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259686: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259687: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259688: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259689: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259690: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259691: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259692: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259693: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259694: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259695: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259696: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259697: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259698: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259699: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259700: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259701: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259702: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259703: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259704: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259705: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259706: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259707: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259708: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259709: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259710: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259711: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259712: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259713: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259714: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259715: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259716: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259717: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259718: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259719: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259720: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259721: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259722: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259723: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259724: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259725: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259726: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259727: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259728: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259729: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259730: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259731: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259732: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259733: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259734: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259735: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259736: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259737: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259738: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259739: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259740: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259741: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259742: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259743: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259744: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259745: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259746: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259747: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259748: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259749: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259750: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259751: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259752: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259753: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259754: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259755: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259756: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259757: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259758: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259759: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259760: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259761: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259762: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259763: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259764: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259765: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259766: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259767: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259768: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259769: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259770: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259771: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259772: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259773: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259774: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259775: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259776: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259777: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259778: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259779: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259780: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259781: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259782: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259783: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259784: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259785: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259786: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259787: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259788: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259789: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259790: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259791: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259792: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259793: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259794: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259795: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259796: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259797: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259798: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259799: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259800: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259801: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259802: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259803: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259804: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259805: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259806: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259807: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259808: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259809: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259810: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259811: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259812: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259813: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259814: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259815: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259816: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259817: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259818: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259819: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259820: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259821: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259822: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259823: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259824: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259825: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259826: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259827: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259828: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259829: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259830: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259831: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259832: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259833: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259834: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259835: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259836: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259837: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259838: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259839: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259840: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259841: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259842: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259843: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259844: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259845: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259846: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259847: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259848: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259849: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259850: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259851: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259852: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259853: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259854: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259855: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259856: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259857: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259858: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259859: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259860: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259861: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259862: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259863: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259864: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259865: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259866: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259867: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259868: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259869: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259870: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259871: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259872: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259873: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259874: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259875: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259876: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259877: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259878: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259879: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259880: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259881: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259882: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259883: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259884: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259885: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259886: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259887: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259888: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259889: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259890: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259891: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259892: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259893: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259894: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259895: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259896: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259897: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259898: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259899: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259900: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259901: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259902: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259903: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259904: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259905: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259906: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259907: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259908: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259909: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259910: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259911: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259912: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259913: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259914: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259915: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259916: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259917: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259918: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259919: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259920: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259921: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259922: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259923: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259924: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259925: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259926: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259927: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259928: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259929: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259930: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259931: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259932: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259933: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259934: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259935: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259936: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259937: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259938: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259939: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259940: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259941: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259942: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259943: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259944: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259945: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259946: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259947: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259948: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259949: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259950: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259951: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259952: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259953: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259954: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259955: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259956: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259957: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259958: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259959: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259960: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259961: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259962: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259963: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259964: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259965: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259966: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259967: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259968: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259969: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259970: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259971: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259972: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259973: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259974: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259975: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259976: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259977: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259978: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259979: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259980: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259981: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259982: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259983: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259984: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259985: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259986: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259987: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259988: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259989: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259990: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259991: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259992: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259993: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259994: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259995: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259996: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259997: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259998: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1259999: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1260000: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1260001: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1260002: fault (page_table_fault) detected @ PC 0xfffffffffffffffc +warn: cycle 1260003: fault (page_table_fault) detected @ PC 0xfffffffffffffffc diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index f2a1151c4..d088333a5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 20:54:51 -M5 started Sun Oct 8 20:55:10 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:07:55 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6868 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 1408131 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 6914938e5..6ab4e0920 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 152920 # Simulator instruction rate (inst/s) -host_mem_usage 166272 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 221766 # Simulator tick rate (ticks/s) +host_inst_rate 8293 # Simulator instruction rate (inst/s) +host_mem_usage 179892 # Number of bytes of host memory used +host_seconds 0.68 # Real time elapsed on the host +host_tick_rate 2595779 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8316 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1767066 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.996390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996390 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 830 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 553 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.996390 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 830 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 553 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.996390 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.996390 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 830 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 553 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use +system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 8316 # number of cpu cycles simulated +system.cpu.numCycles 1767066 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 423c0b115..31db8804a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 10 2006 01:56:36 -M5 started Tue Oct 10 01:57:04 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:08:16 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 8316 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Exiting @ tick 1767066 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 41348bbfb..95835cb62 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 155 # Number of BTB hits +global.BPredUnit.BTBHits 200 # Number of BTB hits global.BPredUnit.BTBLookups 711 # Number of BTB lookups -global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 441 # Number of conditional branches predicted -global.BPredUnit.lookups 888 # Number of BP lookups -global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 26386 # Simulator instruction rate (inst/s) -host_mem_usage 159884 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 31792 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.RASInCorrect 42 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 221 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 451 # Number of conditional branches predicted +global.BPredUnit.lookups 891 # Number of BP lookups +global.BPredUnit.usedRAS 172 # Number of times the RAS was used to get a target. +host_inst_rate 1447 # Simulator instruction rate (inst/s) +host_mem_usage 180084 # Number of bytes of host memory used +host_seconds 1.65 # Real time elapsed on the host +host_tick_rate 455868 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 784 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 376 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 2886 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 752027 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 56 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2646 +system.cpu.commit.COM:committed_per_cycle.samples 28113 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1713 6473.92% - 1 239 903.25% - 2 322 1216.93% - 3 139 525.32% - 4 78 294.78% - 5 67 253.21% - 6 27 102.04% - 7 21 79.37% - 8 40 151.17% + 0 27203 9676.31% + 1 230 81.81% + 2 313 111.34% + 3 133 47.31% + 4 80 28.46% + 5 53 18.85% + 6 27 9.60% + 7 18 6.40% + 8 56 19.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 144 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1694 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses +system.cpu.cpi 315.051110 # CPI: Cycles Per Instruction +system.cpu.cpi_total 315.051110 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 7254.010870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7288.590164 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 667369 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.163701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 444604 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.108541 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 6647.600000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6571.583333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 224 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 465332 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.238095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 70 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 157718 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_targets 2980.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 8 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 23841 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses -system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 856 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 6991.981481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency +system.cpu.dcache.demand_hits 694 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1132701 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.189252 # miss rate for demand accesses +system.cpu.dcache.demand_misses 162 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 77 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 602322 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.099299 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 705 # number of overall hits -system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses -system.cpu.dcache.overall_misses 123 # number of overall misses -system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses +system.cpu.dcache.overall_accesses 856 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 6991.981481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 694 # number of overall hits +system.cpu.dcache.overall_miss_latency 1132701 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.189252 # miss rate for overall accesses +system.cpu.dcache.overall_misses 162 # number of overall misses +system.cpu.dcache.overall_mshr_hits 77 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 602322 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.099299 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use -system.cpu.dcache.total_refs 705 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.684937 # Cycle average of tags in use +system.cpu.dcache.total_refs 694 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 888 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 740 # Number of cache lines fetched -system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 21872 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 150 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4868 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5315 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 925 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 891 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 814 # Number of cache lines fetched +system.cpu.fetch.Cycles 1788 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 145 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5562 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 260 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.031316 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 814 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 372 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.195487 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2887 +system.cpu.fetch.rateDist.samples 28452 system.cpu.fetch.rateDist.min_value 0 - 0 1965 6806.37% - 1 36 124.70% - 2 79 273.64% - 3 66 228.61% - 4 125 432.98% - 5 60 207.83% - 6 40 138.55% - 7 42 145.48% - 8 474 1641.84% + 0 27494 9663.29% + 1 51 17.92% + 2 92 32.34% + 3 74 26.01% + 4 117 41.12% + 5 71 24.95% + 6 43 15.11% + 7 56 19.68% + 8 454 159.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 4971.589641 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4152.244565 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 563 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1247869 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.308354 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 251 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 764013 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.226044 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 3445 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.059783 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 4 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 13780 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.demand_hits 550 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses -system.cpu.icache.demand_misses 190 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 814 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 4971.589641 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency +system.cpu.icache.demand_hits 563 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1247869 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.308354 # miss rate for demand accesses +system.cpu.icache.demand_misses 251 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 764013 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.226044 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 550 # number of overall hits -system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses -system.cpu.icache.overall_misses 190 # number of overall misses -system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses +system.cpu.icache.overall_accesses 814 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 4971.589641 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 563 # number of overall hits +system.cpu.icache.overall_miss_latency 1247869 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.308354 # miss rate for overall accesses +system.cpu.icache.overall_misses 251 # number of overall misses +system.cpu.icache.overall_mshr_hits 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 764013 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.226044 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use -system.cpu.icache.total_refs 550 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 91.596526 # Cycle average of tags in use +system.cpu.icache.total_refs 563 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 532 # Number of branches executed -system.cpu.iew.EXEC:nop 247 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate -system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 336 # Number of stores executed +system.cpu.idleCycles 723576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 571 # Number of branches executed +system.cpu.iew.EXEC:nop 266 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.119043 # Inst execution rate +system.cpu.iew.EXEC:refs 1018 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 343 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1788 # num instructions consuming a value -system.cpu.iew.WB:count 3053 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1875 # num instructions consuming a value +system.cpu.iew.WB:count 3246 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.785067 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1414 # num instructions producing a value -system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle -system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1472 # num instructions producing a value +system.cpu.iew.WB:rate 0.114087 # insts written-back per cycle +system.cpu.iew.WB:sent 3258 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 160 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 14741 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 784 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 71 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 376 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4271 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 675 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 113 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3387 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 82 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 369 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 82 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3500 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 2308 70.86% # Type of FU issued - IntMult 1 0.03% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 605 18.58% # Type of FU issued - MemWrite 343 10.53% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued +(null) 0 0.00% # Type of FU issued +IntAlu 2460 70.29% # Type of FU issued +IntMult 1 0.03% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 0 0.00% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 695 19.86% # Type of FU issued +MemWrite 344 9.83% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010000 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 5 12.50% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 12 30.00% # attempts to use FU when none available - MemWrite 23 57.50% # attempts to use FU when none available + MemRead 11 31.43% # attempts to use FU when none available + MemWrite 22 62.86% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 +system.cpu.iq.ISSUE:issued_per_cycle.samples 28452 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1607 5566.33% - 1 435 1506.75% - 2 298 1032.21% - 3 221 765.50% - 4 164 568.06% - 5 94 325.60% - 6 46 159.33% - 7 15 51.96% - 8 7 24.25% + 0 26938 9467.88% + 1 609 214.04% + 2 344 120.91% + 3 248 87.16% + 4 180 63.26% + 5 81 28.47% + 6 35 12.30% + 7 12 4.22% + 8 5 1.76% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate -system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.123014 # Inst issue rate +system.cpu.iq.iqInstsAdded 3999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3500 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1423 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4622.063197 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2296.591078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1243335 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 617783 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4622.063197 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1243335 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 617783 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4622.063197 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1243335 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 274 # number of overall misses +system.cpu.l2cache.overall_misses 269 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 617783 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +380,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.802720 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2887 # number of cpu cycles simulated +system.cpu.numCycles 28452 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14785 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 5396 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5263 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4690 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3393 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 851 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 25 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1625 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 7057 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 88 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index 688d89868..5f8fafdd1 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,22 @@ warn: Entering event queue @ 0. Starting simulation... warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: cycle 109049: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109050: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109051: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109052: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109053: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109054: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109055: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109056: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109057: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109062: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109063: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109064: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109065: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109066: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109067: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109068: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109069: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 109070: fault (page_table_fault) detected @ PC 0x000000 warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index c51631489..6f8154bb0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 14:00:39 -M5 started Sun Oct 8 14:00:52 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:08:37 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing -Exiting @ tick 2886 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +Exiting @ tick 752027 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 27b01a108..53f245414 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 120829 # Simulator instruction rate (inst/s) -host_mem_usage 165792 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 168699 # Simulator tick rate (ticks/s) +host_inst_rate 7429 # Simulator instruction rate (inst/s) +host_mem_usage 179540 # Number of bytes of host memory used +host_seconds 0.35 # Real time elapsed on the host +host_tick_rate 2820365 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 3777 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 980012 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 81 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use +system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3777 # number of cpu cycles simulated +system.cpu.numCycles 980012 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 1beab6f4b..b479e5a46 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 10 2006 01:56:36 -M5 started Tue Oct 10 01:57:11 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:08:56 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing -Exiting @ tick 3777 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +Exiting @ tick 980012 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index ab86ba509..ae23f7eec 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 68704 # Simulator instruction rate (inst/s) -host_mem_usage 166092 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 103651 # Simulator tick rate (ticks/s) +host_inst_rate 57798 # Simulator instruction rate (inst/s) +host_mem_usage 179040 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 17679602 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8579 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 1738011 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3987.109756 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2987.109756 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 326943 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 244943 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3968.740000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2968.740000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 198437 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 148437 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3980.151515 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 525380 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 393380 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 3980.151515 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 525380 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 393380 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.396200 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.993399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3978.069307 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2978.069307 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 907 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1205355 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 902355 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.993399 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3978.069307 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 907 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1205355 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 604 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 902355 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.993399 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 3978.069307 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 907 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1205355 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 604 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 902355 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.062649 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 2983.237875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1982.237875 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1291742 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 858309 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2983.237875 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1291742 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 858309 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 2983.237875 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1291742 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 858309 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 216.976175 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 1738011 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 4acd2a2e5..8722547ad 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 9 2006 19:28:25 -M5 started Mon Oct 9 19:28:56 2006 +M5 compiled Oct 13 2006 18:43:33 +M5 started Fri Oct 13 18:44:16 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 8579 because target called exit() +Exiting @ tick 1738011 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index e5fad9159..32bf8dc98 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 640 # Number of BTB hits -global.BPredUnit.BTBLookups 3595 # Number of BTB lookups -global.BPredUnit.RASInCorrect 99 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1081 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2447 # Number of conditional branches predicted -global.BPredUnit.lookups 4169 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 8624 # Simulator instruction rate (inst/s) -host_mem_usage 167824 # Number of bytes of host memory used -host_seconds 1.30 # Real time elapsed on the host -host_tick_rate 6469 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1868 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1106 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 1308 # Number of BTB hits +global.BPredUnit.BTBLookups 6837 # Number of BTB lookups +global.BPredUnit.RASInCorrect 164 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1235 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 4603 # Number of conditional branches predicted +global.BPredUnit.lookups 12596 # Number of BP lookups +global.BPredUnit.usedRAS 5739 # Number of times the RAS was used to get a target. +host_inst_rate 945 # Simulator instruction rate (inst/s) +host_mem_usage 181580 # Number of bytes of host memory used +host_seconds 11.90 # Real time elapsed on the host +host_tick_rate 187981 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 52 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 3 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 6560 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3600 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 5837 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2389 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8439 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2237162 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 126 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 130 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 8391 +system.cpu.commit.COM:committed_per_cycle.samples 189229 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3954 4712.19% - 1 1909 2275.06% - 2 920 1096.41% - 3 516 614.94% - 4 376 448.10% - 5 235 280.06% - 6 188 224.05% - 7 167 199.02% - 8 126 150.16% + 0 183654 9705.38% + 1 3073 162.40% + 2 1213 64.10% + 3 492 26.00% + 4 307 16.22% + 5 181 9.57% + 6 120 6.34% + 7 59 3.12% + 8 130 6.87% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5640 # Number of instructions committed -system.cpu.commit.COM:count_1 5641 # Number of instructions committed +system.cpu.commit.COM:count_0 5641 # Number of instructions committed +system.cpu.commit.COM:count_1 5640 # Number of instructions committed system.cpu.commit.COM:loads 1958 # Number of loads committed system.cpu.commit.COM:loads_0 979 # Number of loads committed system.cpu.commit.COM:loads_1 979 # Number of loads committed @@ -61,141 +61,141 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 832 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 980 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7510 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5623 # Number of Instructions Simulated -system.cpu.committedInsts_1 5624 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 31727 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5624 # Number of Instructions Simulated +system.cpu.committedInsts_1 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.500800 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.500533 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.750333 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.077253 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 3.077253 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.232323 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.232323 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2678 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 717 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 717 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080041 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.080041 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 233 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 233 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 442 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 442 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.cpi_0 397.788407 # CPI: Cycles Per Instruction +system.cpu.cpi_1 397.859150 # CPI: Cycles Per Instruction +system.cpu.cpi_total 198.911888 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10081.356250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 10081.356250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10477.810000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10477.810000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2888 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2888 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3226034 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 3226034 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.099751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.099751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 320 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 320 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2095562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 2095562 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.062344 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.062344 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 200 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.762376 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 2.762376 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.062500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.062500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1321 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1321 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 837 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 837 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.186576 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.186576 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 303 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 303 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 159 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 297 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 297 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.692982 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 6532.834320 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 6532.834320 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7817.623288 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 7817.623288 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1117 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1117 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3312147 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 3312147 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.312192 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.312192 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 507 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 507 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 361 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 361 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1141373 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1141373 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 3977 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 3606.011765 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.575145 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 85 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 3977 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 306511 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4832 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4832 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.899254 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 2.899254 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 7905.902056 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 7905.902056 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9355.303468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 9355.303468 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3999 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3999 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4005 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4005 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1554 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 1554 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6538181 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 6538181 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118192 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.118192 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 536 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 536 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate 0.171151 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.171151 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.dcache.demand_misses 827 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 827 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 481 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 739 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3236935 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 3236935 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075413 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075413 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 342 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 342 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_rate 0.071606 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.071606 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4535 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4535 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4832 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4832 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.899254 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 2.899254 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7905.902056 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 7905.902056 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.160819 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9355.303468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 9355.303468 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3999 # number of overall hits -system.cpu.dcache.overall_hits_0 3999 # number of overall hits +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 4005 # number of overall hits +system.cpu.dcache.overall_hits_0 4005 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 1554 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 1554 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6538181 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 6538181 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118192 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.118192 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 536 # number of overall misses -system.cpu.dcache.overall_misses_0 536 # number of overall misses +system.cpu.dcache.overall_miss_rate 0.171151 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.171151 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 no value # miss rate for overall accesses +system.cpu.dcache.overall_misses 827 # number of overall misses +system.cpu.dcache.overall_misses_0 827 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 481 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 481 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 739 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3236935 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 3236935 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075413 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075413 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 342 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 342 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate 0.071606 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.071606 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +215,153 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 346 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 226.387441 # Cycle average of tags in use -system.cpu.dcache.total_refs 3999 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 198.595005 # Cycle average of tags in use +system.cpu.dcache.total_refs 4005 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1691 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 271 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 367 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22675 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 9659 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3750 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 233 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4169 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2866 # Number of cache lines fetched -system.cpu.fetch.Cycles 6955 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25228 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1143 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.493957 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1190 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.989100 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 101864 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 264 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 379 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 73628 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 257376 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12701 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6044 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 680 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 340 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 12596 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13043 # Number of cache lines fetched +system.cpu.fetch.Cycles 28220 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1653 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 84650 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4944 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.066558 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 52829 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7047 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.447294 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 8440 +system.cpu.fetch.rateDist.samples 189249 system.cpu.fetch.rateDist.min_value 0 - 0 4352 5156.40% - 1 273 323.46% - 2 228 270.14% - 3 247 292.65% - 4 313 370.85% - 5 277 328.20% - 6 294 348.34% - 7 291 344.79% - 8 2165 2565.17% + 0 174064 9197.62% + 1 369 19.50% + 2 570 30.12% + 3 3356 177.33% + 4 1799 95.06% + 5 1035 54.69% + 6 675 35.67% + 7 2396 126.61% + 8 4985 263.41% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 2.982343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.995153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2243 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2243 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 1858 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.217376 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.217376 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 4 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 1235 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.215980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 13041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 13041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 7799.181319 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 7799.181319 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 7166.106518 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7166.106518 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12131 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 12131 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7097255 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 7097255 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.069780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.069780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 910 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 910 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 281 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 281 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4507481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 4507481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.048232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 629 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 629 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.623586 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets 5755.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 19.286169 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 16 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 92083 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 13041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 13041 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 7799.181319 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 7799.181319 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 7166.106518 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 7166.106518 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2243 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2243 # number of demand (read+write) hits +system.cpu.icache.demand_hits 12131 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 12131 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 7097255 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 7097255 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.217376 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.217376 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 623 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate 0.069780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.069780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.icache.demand_misses 910 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 910 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 281 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 281 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4507481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 4507481 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.215980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.215980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_rate 0.048232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.048232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 629 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 629 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 13041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 13041 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 7799.181319 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 7799.181319 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 7166.106518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 7166.106518 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2243 # number of overall hits -system.cpu.icache.overall_hits_0 2243 # number of overall hits +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 12131 # number of overall hits +system.cpu.icache.overall_hits_0 12131 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 7097255 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 7097255 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.217376 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.217376 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.069780 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.069780 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 no value # miss rate for overall accesses -system.cpu.icache.overall_misses 623 # number of overall misses -system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses 910 # number of overall misses +system.cpu.icache.overall_misses_0 910 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 281 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 281 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4507481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 4507481 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.215980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.215980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_rate 0.048232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.048232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 629 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 629 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,123 +378,124 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9 # number of replacements -system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements 6 # number of replacements +system.cpu.icache.replacements_0 6 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 629 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 332.363626 # Cycle average of tags in use -system.cpu.icache.total_refs 2243 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 289.520052 # Cycle average of tags in use +system.cpu.icache.total_refs 12131 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.iew.EXEC:branches 2318 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1160 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1158 # Number of branches executed -system.cpu.iew.EXEC:nop 65 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.813863 # Inst execution rate -system.cpu.iew.EXEC:refs 4922 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2464 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2458 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1868 # Number of stores executed -system.cpu.iew.EXEC:stores_0 932 # Number of stores executed -system.cpu.iew.EXEC:stores_1 936 # Number of stores executed +system.cpu.idleCycles 2047914 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4335 # Number of branches executed +system.cpu.iew.EXEC:branches_0 2743 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1592 # Number of branches executed +system.cpu.iew.EXEC:nop 76 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 38 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 38 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.146521 # Inst execution rate +system.cpu.iew.EXEC:refs 11792 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 7324 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 4468 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 3821 # Number of stores executed +system.cpu.iew.EXEC:stores_0 2506 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10001 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5003 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 4998 # num instructions consuming a value -system.cpu.iew.WB:count 14799 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7402 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7397 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.777122 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776134 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.778111 # average fanout of values written-back +system.cpu.iew.WB:consumers 12302 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 6628 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5674 # num instructions consuming a value +system.cpu.iew.WB:count 22631 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 12849 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 9782 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.818810 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.828908 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.807014 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7772 # num instructions producing a value -system.cpu.iew.WB:producers_0 3883 # num instructions producing a value -system.cpu.iew.WB:producers_1 3889 # num instructions producing a value -system.cpu.iew.WB:rate 1.753436 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.877014 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.876422 # insts written-back per cycle -system.cpu.iew.WB:sent 14932 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7467 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7465 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 926 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3701 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 604 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2214 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18792 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3054 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1532 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1522 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15309 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 10073 # num instructions producing a value +system.cpu.iew.WB:producers_0 5494 # num instructions producing a value +system.cpu.iew.WB:producers_1 4579 # num instructions producing a value +system.cpu.iew.WB:rate 0.119583 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.067895 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.051689 # insts written-back per cycle +system.cpu.iew.WB:sent 22783 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 12935 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 9848 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1057 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 60428 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10160 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 5995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 8226 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 42995 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 7971 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 4818 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 3153 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1093 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 27729 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1395 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6044 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 109 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 3147 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 889 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 294 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 5581 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 5025 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.cacheBlocked 1500 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 34 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 764 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 162 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.666311 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.666430 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.332741 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8135 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 2621 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 1577 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 74 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 830 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.002514 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.002513 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.005027 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 16810 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5505 67.67% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1656 20.36% # Type of FU issued - MemWrite 969 11.91% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued +(null) 2 0.01% # Type of FU issued +IntAlu 9156 54.47% # Type of FU issued +IntMult 1 0.01% # Type of FU issued +IntDiv 0 0.00% # Type of FU issued +FloatAdd 2 0.01% # Type of FU issued +FloatCmp 0 0.00% # Type of FU issued +FloatCvt 0 0.00% # Type of FU issued +FloatMult 0 0.00% # Type of FU issued +FloatDiv 0 0.00% # Type of FU issued +FloatSqrt 0 0.00% # Type of FU issued +MemRead 5111 30.40% # Type of FU issued +MemWrite 2538 15.10% # Type of FU issued +IprAccess 0 0.00% # Type of FU issued +InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 12012 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5481 67.75% # Type of FU issued + IntAlu 7390 61.52% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -503,37 +504,37 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1640 20.27% # Type of FU issued - MemWrite 964 11.92% # Type of FU issued + MemRead 3275 27.26% # Type of FU issued + MemWrite 1342 11.17% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16225 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 28822 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist - (null) 4 0.02% # Type of FU issued - IntAlu 10986 67.71% # Type of FU issued + (null) 4 0.01% # Type of FU issued + IntAlu 16546 57.41% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 4 0.02% # Type of FU issued + FloatAdd 4 0.01% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3296 20.31% # Type of FU issued - MemWrite 1933 11.91% # Type of FU issued + MemRead 8386 29.10% # Type of FU issued + MemWrite 3880 13.46% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt 154 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 76 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011156 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.006348 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004807 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.005343 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.002637 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.002706 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 10 5.52% # attempts to use FU when none available + IntAlu 3 1.95% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -542,135 +543,135 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 100 55.25% # attempts to use FU when none available - MemWrite 71 39.23% # attempts to use FU when none available + MemRead 86 55.84% # attempts to use FU when none available + MemWrite 65 42.21% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 8440 +system.cpu.iq.ISSUE:issued_per_cycle.samples 189249 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2689 3186.02% - 1 1457 1726.30% - 2 1432 1696.68% - 3 1110 1315.17% - 4 757 896.92% - 5 583 690.76% - 6 287 340.05% - 7 91 107.82% - 8 34 40.28% + 0 174743 9233.50% + 1 7200 380.45% + 2 2967 156.78% + 3 2563 135.43% + 4 1137 60.08% + 5 450 23.78% + 6 138 7.29% + 7 35 1.85% + 8 16 0.85% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.922393 # Inst issue rate -system.cpu.iq.iqInstsAdded 18687 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16225 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6645 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 961 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 961 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.059623 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059623 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1969 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 1969 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994797 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.994797 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 956 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 956 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 956 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994797 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994797 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 956 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 956 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 0.152297 # Inst issue rate +system.cpu.iq.iqInstsAdded 42876 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 28822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 30249 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 220 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 25020 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 975 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 975 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6774.326824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 6774.326824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3621.391572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3621.391572 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 6591420 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 6591420 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.997949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 973 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 973 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3523614 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3523614 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 973 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 973 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005230 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002055 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 961 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 961 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 975 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 975 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.059623 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 2.059623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 6774.326824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 6774.326824 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 3621.391572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3621.391572 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1969 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 1969 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6591420 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 6591420 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994797 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.994797 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_rate 0.997949 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.997949 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.l2cache.demand_misses 973 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 973 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 956 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 956 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3523614 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 3523614 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.994797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_rate 0.997949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.997949 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 973 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 973 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 961 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 961 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 975 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 975 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.059623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 2.059623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 6774.326824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 6774.326824 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 3621.391572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3621.391572 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5 # number of overall hits -system.cpu.l2cache.overall_hits_0 5 # number of overall hits +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_hits_0 2 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1969 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 1969 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6591420 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 6591420 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994797 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.994797 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 956 # number of overall misses -system.cpu.l2cache.overall_misses_0 956 # number of overall misses +system.cpu.l2cache.overall_miss_rate 0.997949 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.997949 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 no value # miss rate for overall accesses +system.cpu.l2cache.overall_misses 973 # number of overall misses +system.cpu.l2cache.overall_misses_0 973 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 956 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 956 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3523614 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 3523614 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.994797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_rate 0.997949 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.997949 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 no value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 973 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 973 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -690,32 +691,35 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 956 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 973 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 558.812441 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 489.175621 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 8440 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 345 # Number of cycles rename is blocking +system.cpu.numCycles 189249 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 77071 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 9958 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 698 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26874 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21097 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15772 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3566 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 766 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7670 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 572 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1906 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IQFullEvents 22 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 258812 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2912 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 26 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 78724 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 64105 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 44626 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 11563 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6044 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2613 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 36524 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 22222 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 52 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5371 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 39 # count of temporary serializing insts renamed +system.cpu.timesIdled 686 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 48d711163..e192672a7 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -16,7 +16,17 @@ warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. +warn: cycle 1311113: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311114: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311115: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311124: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311125: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311126: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311127: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311128: fault (page_table_fault) detected @ PC 0x000000 +warn: cycle 1311129: fault (page_table_fault) detected @ PC 0x000000 warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. warn: Default fetch doesn't update it's state from a functional call. +warn: Found outstanding miss on an non-update probe warn: Default fetch doesn't update it's state from a functional call. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 2b27a0049..9ffc67aec 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 10 2006 01:56:36 -M5 started Tue Oct 10 01:57:16 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:09:16 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing -Exiting @ tick 8439 because target called exit() +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Exiting @ tick 2237162 because target called exit() diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 72ea32994..a3e69e540 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -194,6 +194,8 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] @@ -206,6 +208,8 @@ system=system [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index 14eb07351..3d64b3547 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -19,6 +19,8 @@ mem_mode=atomic [system.membus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.dcache] type=BaseCache @@ -87,6 +89,8 @@ function_trace_start=0 [system.cpu.toL2Bus] type=Bus bus_id=0 +clock=1000 +width=64 [system.cpu.icache] type=BaseCache diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index ebc70e1f0..a786f3201 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 620088 # Simulator instruction rate (inst/s) -host_mem_usage 159272 # Number of bytes of host memory used -host_seconds 0.81 # Real time elapsed on the host -host_tick_rate 845969 # Simulator tick rate (ticks/s) +host_inst_rate 66568 # Simulator instruction rate (inst/s) +host_mem_usage 179344 # Number of bytes of host memory used +host_seconds 7.51 # Real time elapsed on the host +host_tick_rate 530155 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 682488 # Number of ticks simulated +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 3982316 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1209 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1209 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 806 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 806 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use +system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 0 # number of cpu cycles simulated +system.cpu.numCycles 3982316 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 076cf0a5a..2f704cddb 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 8 2006 20:54:51 -M5 started Sun Oct 8 20:55:29 2006 +M5 compiled Oct 13 2006 16:07:10 +M5 started Fri Oct 13 16:09:55 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 682488 because a thread reached the max instruction count +command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Exiting @ tick 3982316 because a thread reached the max instruction count |