diff options
| -rw-r--r-- | src/arch/arm/insts/mem.cc | 14 | ||||
| -rw-r--r-- | src/arch/arm/insts/mem.hh | 17 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/insts.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 96 |
5 files changed, 0 insertions, 134 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc index 3b57aae64..9cc9af025 100644 --- a/src/arch/arm/insts/mem.cc +++ b/src/arch/arm/insts/mem.cc @@ -78,20 +78,6 @@ MemoryReg::printOffset(std::ostream &os) const } string -Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const -{ - stringstream ss; - printMnemonic(ss); - printIntReg(ss, dest); - ss << ", "; - printIntReg(ss, op1); - ss << ", ["; - printIntReg(ss, base); - ss << "]"; - return ss.str(); -} - -string RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { stringstream ss; diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index da4dac3f3..0c82acfcf 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -47,23 +47,6 @@ namespace ArmISA { -class Swap : public PredOp -{ - protected: - IntRegIndex dest; - IntRegIndex op1; - IntRegIndex base; - - Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass, - IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base) - : PredOp(mnem, _machInst, __opClass), - dest(_dest), op1(_op1), base(_base) - {} - - std::string generateDisassembly( - Addr pc, const SymbolTable *symtab) const override; -}; - class MightBeMicro : public PredOp { protected: diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 50e3e358f..888bbdff6 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -226,10 +226,6 @@ def format ArmSyncMem() {{ const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); switch (PUBWL) { - case 0x10: - return new Swp(machInst, rt, rt2, rn); - case 0x14: - return new Swpb(machInst, rt, rt2, rn); case 0x18: return new %(strex)s(machInst, rt, rt2, rn, true, 0); case 0x19: diff --git a/src/arch/arm/isa/insts/insts.isa b/src/arch/arm/isa/insts/insts.isa index faca2f697..007d99ff2 100644 --- a/src/arch/arm/isa/insts/insts.isa +++ b/src/arch/arm/isa/insts/insts.isa @@ -62,9 +62,6 @@ split decoder; //Stores of a single item ##include "str.isa" -//Swaps -##include "swap.isa" - //Load/store multiple ##include "macromem.isa" diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa deleted file mode 100644 index 4eac18e4c..000000000 --- a/src/arch/arm/isa/insts/swap.isa +++ /dev/null @@ -1,96 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2010-2011 ARM Limited -// All rights reserved -// -// The license below extends only to copyright in the software and shall -// not be construed as granting a license to any other intellectual -// property including but not limited to intellectual property relating -// to a hardware implementation of the functionality of the software -// licensed hereunder. You may use the software subject to the license -// terms below provided that you ensure that this notice is replicated -// unmodified and in its entirety in all distributions of the software, -// modified or unmodified, in source code or in binary form. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Gabe Black - -let {{ - - header_output = decoder_output = exec_output = "" - - class SwapInst(LoadStoreInst): - execBase = 'Swap' - decConstBase = 'Swap' - - def __init__(self, name, Name, eaCode, - preAccCode, postAccCode, memFlags, instFlags = []): - super(SwapInst, self).__init__() - self.name = name - self.Name = Name - self.eaCode = eaCode - self.preAccCode = preAccCode - self.postAccCode = postAccCode - self.memFlags = memFlags - self.instFlags = instFlags - - def emit(self): - global header_output, decoder_output, exec_output - codeBlobs = { "ea_code": self.eaCode, - "preacc_code": self.preAccCode, - "postacc_code": self.postAccCode } - codeBlobs["predicate_test"] = pickPredicate(codeBlobs) - (newHeader, - newDecoder, - newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, - self.memFlags, self.instFlags, - base = 'Swap') - header_output += newHeader - decoder_output += newDecoder - exec_output += newExec - - swpPreAccCode = ''' - if (!((SCTLR)Sctlr).sw) { - return std::make_shared<UndefinedInstruction>(machInst, false, - mnemonic); - } - ''' - - SwapInst('swp', 'Swp', 'EA = Base;', - swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);', - 'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);', - ['Request::MEM_SWAP', - 'ArmISA::TLB::AlignWord', - 'ArmISA::TLB::MustBeOne'], - ['IsStoreConditional']).emit() - - SwapInst('swpb', 'Swpb', 'EA = Base;', - swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);', - 'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', - ['Request::MEM_SWAP', - 'ArmISA::TLB::AlignByte', - 'ArmISA::TLB::MustBeOne'], - ['IsStoreConditional']).emit() -}}; |