diff options
| -rw-r--r-- | dev/ns_gige.cc | 7 | ||||
| -rw-r--r-- | dev/ns_gige.hh | 1 | ||||
| -rw-r--r-- | dev/ns_gige_reg.h | 1 | ||||
| -rw-r--r-- | dev/sinic.cc | 7 | ||||
| -rw-r--r-- | dev/sinic.hh | 1 | ||||
| -rw-r--r-- | dev/sinicreg.hh | 1 | ||||
| -rw-r--r-- | python/m5/objects/Ethernet.py | 1 |
7 files changed, 17 insertions, 2 deletions
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index d6df347bc..ed8c794f9 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -767,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data) reg |= M5REG_RX_THREAD; if (params()->tx_thread) reg |= M5REG_TX_THREAD; + if (params()->rss) + reg |= M5REG_RSS; break; default: @@ -3009,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(NSGigE) @@ -3048,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(NSGigE) @@ -3093,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new NSGigE(params); } diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cdd8e4b9e..59c55056e 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -385,6 +385,7 @@ class NSGigE : public PciDev uint32_t rx_fifo_size; bool rx_thread; bool tx_thread; + bool rss; bool dma_no_allocate; }; diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index eadc60d03..5f6fa2cc5 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -306,6 +306,7 @@ /* M5 control register */ #define M5REG_RESERVED 0xfffffffc +#define M5REG_RSS 0x00000004 #define M5REG_RX_THREAD 0x00000002 #define M5REG_TX_THREAD 0x00000001 diff --git a/dev/sinic.cc b/dev/sinic.cc index 34b4213e0..363994919 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -761,6 +761,8 @@ Device::reset() regs.Config |= Config_RxThread; if (params()->tx_thread) regs.Config |= Config_TxThread; + if (params()->rss) + regs.Config |= Config_RSS; regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow; regs.RxMaxCopy = params()->rx_max_copy; regs.TxMaxCopy = params()->tx_max_copy; @@ -1624,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device) Param<string> hardware_address; Param<bool> rx_thread; Param<bool> tx_thread; + Param<bool> rss; END_DECLARE_SIM_OBJECT_PARAMS(Device) @@ -1666,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device) INIT_PARAM(rx_filter, "Enable Receive Filter"), INIT_PARAM(hardware_address, "Ethernet Hardware Address"), INIT_PARAM(rx_thread, ""), - INIT_PARAM(tx_thread, "") + INIT_PARAM(tx_thread, ""), + INIT_PARAM(rss, "") END_INIT_SIM_OBJECT_PARAMS(Device) @@ -1714,6 +1718,7 @@ CREATE_SIM_OBJECT(Device) params->eaddr = hardware_address; params->rx_thread = rx_thread; params->tx_thread = tx_thread; + params->rss = rss; return new Device(params); } diff --git a/dev/sinic.hh b/dev/sinic.hh index c4027be86..25172fa45 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -355,6 +355,7 @@ class Device : public Base bool dma_no_allocate; bool rx_thread; bool tx_thread; + bool rss; }; protected: diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh index fc1f4c06b..f90432398 100644 --- a/dev/sinicreg.hh +++ b/dev/sinicreg.hh @@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address __SINIC_REG32(Size, 0x68); // register addres space size // Config register bits +__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling __SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads __SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread __SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 3a7f88d04..6113e656f 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -86,6 +86,7 @@ class EtherDevBase(PciDevice): intr_delay = Param.Latency('10us', "Interrupt propagation delay") rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") tx_thread = Param.Bool(False, "dedicated kernel threads for receive") + rss = Param.Bool(False, "Receive Side Scaling") class NSGigE(EtherDevBase): type = 'NSGigE' |