diff options
32 files changed, 4208 insertions, 34 deletions
diff --git a/SConscript b/SConscript index 677a06d1f..5b4361298 100644 --- a/SConscript +++ b/SConscript @@ -43,15 +43,8 @@ Import('env') ################################################### # Base sources used by all configurations. -base_sources = Split(''' - arch/alpha/decoder.cc - arch/alpha/alpha_o3_exec.cc - arch/alpha/fast_cpu_exec.cc - arch/alpha/simple_cpu_exec.cc - arch/alpha/full_cpu_exec.cc - arch/alpha/faults.cc - arch/alpha/isa_traits.cc +base_sources = Split(''' base/circlebuf.cc base/copyright.cc base/cprintf.cc @@ -229,6 +222,14 @@ base_sources = Split(''' sim/stat_control.cc sim/trace_context.cc ''') +# These are now included by the architecture specific SConscript +# arch/alpha/decoder.cc +# arch/alpha/alpha_o3_exec.cc +# arch/alpha/fast_cpu_exec.cc +# arch/alpha/simple_cpu_exec.cc +# arch/alpha/full_cpu_exec.cc +# arch/alpha/faults.cc +# arch/alpha/isa_traits.cc # MySql sources mysql_sources = Split(''' @@ -238,14 +239,6 @@ mysql_sources = Split(''' # Full-system sources full_system_sources = Split(''' - arch/alpha/alpha_memory.cc - arch/alpha/arguments.cc - arch/alpha/ev5.cc - arch/alpha/osfpal.cc - arch/alpha/pseudo_inst.cc - arch/alpha/stacktrace.cc - arch/alpha/vtophys.cc - base/crc.cc base/inet.cc base/remote_gdb.cc @@ -301,6 +294,15 @@ full_system_sources = Split(''' sim/system.cc ''') +# These are now included by the architecture specific SConscript +# arch/alpha/alpha_memory.cc +# arch/alpha/arguments.cc +# arch/alpha/ev5.cc +# arch/alpha/osfpal.cc +# arch/alpha/pseudo_inst.cc +# arch/alpha/stacktrace.cc +# arch/alpha/vtophys.cc + # turbolaser encumbered sources turbolaser_sources = Split(''' encumbered/dev/dma.cc @@ -323,9 +325,6 @@ turbolaser_sources = Split(''' # Syscall emulation (non-full-system) sources syscall_emulation_sources = Split(''' - arch/alpha/alpha_common_syscall_emul.cc - arch/alpha/alpha_linux_process.cc - arch/alpha/alpha_tru64_process.cc cpu/memtest/memtest.cc encumbered/eio/eio.cc encumbered/eio/exolex.cc @@ -334,6 +333,11 @@ syscall_emulation_sources = Split(''' sim/syscall_emul.cc ''') +# These are now included by the architecture specific SConscript +# arch/alpha/alpha_common_syscall_emul.cc +# arch/alpha/alpha_linux_process.cc +# arch/alpha/alpha_tru64_process.cc + targetarch_files = Split(''' alpha_common_syscall_emul.hh alpha_linux_process.hh @@ -354,13 +358,18 @@ targetarch_files = Split(''' vtophys.hh ''') +# Set up bridging headers to the architecture specific versions for f in targetarch_files: - env.Command('targetarch/' + f, 'arch/alpha/' + f, - '''echo '#include "arch/alpha/%s"' > $TARGET''' % f) + env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f), + '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f)) +# Let the target architecture define what sources it needs +arch_source = SConscript('arch/%s/SConscript' % env['TARGET_ISA'], + build_dir = 'build/%s/' % env['BUILD_DIR'], + exports = 'env', duplicate = False) # Set up complete list of sources based on configuration. -sources = base_sources +sources = base_sources + arch_source if env['FULL_SYSTEM']: sources += full_system_sources @@ -377,6 +386,25 @@ for opt in env.ExportOptions: ################################################### # +# Add an SCons scanner for ISA files +# +################################################### +def ISAScan(): + return SCons.Scanner.Classic("ISAScan", + "$ISASUFFIXES", + "SRCDIR", + '^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"') + +def ISAPath(env, dir, a=None): + return (Dir(env['SRCDIR']), Dir('.')) + +iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"], + path_function = ISAPath) +env.Append(SCANNERS = iscan) + + +################################################### +# # Special build rules. # ################################################### @@ -388,15 +416,24 @@ env.Command(Split('base/traceflags.hh base/traceflags.cc'), 'python $SOURCE $TARGET.base') # several files are generated from arch/$TARGET_ISA/isa_desc. -env.Command(Split('''arch/alpha/decoder.cc - arch/alpha/decoder.hh - arch/alpha/alpha_o3_exec.cc - arch/alpha/fast_cpu_exec.cc - arch/alpha/simple_cpu_exec.cc - arch/alpha/full_cpu_exec.cc'''), - Split('''arch/alpha/isa_desc - arch/isa_parser.py'''), - '$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha') +env.Command(Split(''' + arch/%s/decoder.cc + arch/%s/decoder.hh + arch/%s/alpha_o3_exec.cc + arch/%s/fast_cpu_exec.cc + arch/%s/simple_cpu_exec.cc + arch/%s/full_cpu_exec.cc''' % + (env['TARGET_ISA'], + env['TARGET_ISA'], + env['TARGET_ISA'], + env['TARGET_ISA'], + env['TARGET_ISA'], + env['TARGET_ISA'])), + Split(''' + arch/%s/isa_desc + arch/isa_parser.py''' % + env['TARGET_ISA']), + '$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/%s' % env['TARGET_ISA']) # libelf build is described in its own SConscript file. diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript new file mode 100644 index 000000000..2c98125bc --- /dev/null +++ b/arch/alpha/SConscript @@ -0,0 +1,488 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +import os +import sys +from os.path import isdir + +# This file defines how to build a particular configuration of M5 +# based on variable settings in the 'env' build environment. + +# Import build environment variable from SConstruct. +Import('env') + +################################################### +# +# Define needed sources. +# +################################################### + +# Base sources used by all configurations. +arch_base_sources = Split(''' + arch/alpha/decoder.cc + arch/alpha/alpha_o3_exec.cc + arch/alpha/fast_cpu_exec.cc + arch/alpha/simple_cpu_exec.cc + arch/alpha/full_cpu_exec.cc + arch/alpha/faults.cc + arch/alpha/isa_traits.cc + ''') + +# base/circlebuf.cc +# base/copyright.cc +# base/cprintf.cc +# base/embedfile.cc +# base/fast_alloc.cc +# base/fifo_buffer.cc +# base/hostinfo.cc +# base/hybrid_pred.cc +# base/inifile.cc +# base/intmath.cc +# base/match.cc +# base/misc.cc +# base/output.cc +# base/pollevent.cc +# base/range.cc +# base/random.cc +# base/sat_counter.cc +# base/socket.cc +# base/statistics.cc +# base/str.cc +# base/time.cc +# base/trace.cc +# base/traceflags.cc +# base/userinfo.cc +# base/compression/lzss_compression.cc +# base/loader/aout_object.cc +# base/loader/ecoff_object.cc +# base/loader/elf_object.cc +# base/loader/object_file.cc +# base/loader/symtab.cc +# base/stats/events.cc +# base/stats/statdb.cc +# base/stats/visit.cc +# base/stats/text.cc +# +# cpu/base.cc +# cpu/base_dyn_inst.cc +# cpu/exec_context.cc +# cpu/exetrace.cc +# cpu/pc_event.cc +# cpu/static_inst.cc +# cpu/o3/2bit_local_pred.cc +# cpu/o3/alpha_dyn_inst.cc +# cpu/o3/alpha_cpu.cc +# cpu/o3/alpha_cpu_builder.cc +# cpu/o3/bpred_unit.cc +# cpu/o3/btb.cc +# cpu/o3/commit.cc +# cpu/o3/decode.cc +# cpu/o3/fetch.cc +# cpu/o3/free_list.cc +# cpu/o3/cpu.cc +# cpu/o3/iew.cc +# cpu/o3/inst_queue.cc +# cpu/o3/ldstq.cc +# cpu/o3/mem_dep_unit.cc +# cpu/o3/ras.cc +# cpu/o3/rename.cc +# cpu/o3/rename_map.cc +# cpu/o3/rob.cc +# cpu/o3/sat_counter.cc +# cpu/o3/store_set.cc +# cpu/o3/tournament_pred.cc +# cpu/fast/cpu.cc +# cpu/sampler/sampler.cc +# cpu/simple/cpu.cc +# cpu/trace/reader/mem_trace_reader.cc +# cpu/trace/reader/ibm_reader.cc +# cpu/trace/reader/itx_reader.cc +# cpu/trace/reader/m5_reader.cc +# cpu/trace/opt_cpu.cc +# cpu/trace/trace_cpu.cc +# +# encumbered/cpu/full/bpred.cc +# encumbered/cpu/full/commit.cc +# encumbered/cpu/full/cpu.cc +# encumbered/cpu/full/create_vector.cc +# encumbered/cpu/full/cv_spec_state.cc +# encumbered/cpu/full/dd_queue.cc +# encumbered/cpu/full/dep_link.cc +# encumbered/cpu/full/dispatch.cc +# encumbered/cpu/full/dyn_inst.cc +# encumbered/cpu/full/execute.cc +# encumbered/cpu/full/fetch.cc +# encumbered/cpu/full/floss_reasons.cc +# encumbered/cpu/full/fu_pool.cc +# encumbered/cpu/full/inst_fifo.cc +# encumbered/cpu/full/instpipe.cc +# encumbered/cpu/full/issue.cc +# encumbered/cpu/full/ls_queue.cc +# encumbered/cpu/full/machine_queue.cc +# encumbered/cpu/full/pipetrace.cc +# encumbered/cpu/full/readyq.cc +# encumbered/cpu/full/reg_info.cc +# encumbered/cpu/full/rob_station.cc +# encumbered/cpu/full/spec_memory.cc +# encumbered/cpu/full/spec_state.cc +# encumbered/cpu/full/storebuffer.cc +# encumbered/cpu/full/writeback.cc +# encumbered/cpu/full/iq/iq_station.cc +# encumbered/cpu/full/iq/iqueue.cc +# encumbered/cpu/full/iq/segmented/chain_info.cc +# encumbered/cpu/full/iq/segmented/chain_wire.cc +# encumbered/cpu/full/iq/segmented/iq_seg.cc +# encumbered/cpu/full/iq/segmented/iq_segmented.cc +# encumbered/cpu/full/iq/segmented/seg_chain.cc +# encumbered/cpu/full/iq/seznec/iq_seznec.cc +# encumbered/cpu/full/iq/standard/iq_standard.cc +# encumbered/mem/functional/main.cc +# +# mem/base_hier.cc +# mem/base_mem.cc +# mem/hier_params.cc +# mem/mem_cmd.cc +# mem/mem_debug.cc +# mem/mem_req.cc +# mem/memory_interface.cc +# mem/bus/base_interface.cc +# mem/bus/bus.cc +# mem/bus/bus_bridge.cc +# mem/bus/bus_bridge_master.cc +# mem/bus/bus_bridge_slave.cc +# mem/bus/bus_interface.cc +# mem/bus/dma_bus_interface.cc +# mem/bus/dma_interface.cc +# mem/bus/master_interface.cc +# mem/bus/slave_interface.cc +# mem/cache/base_cache.cc +# mem/cache/cache.cc +# mem/cache/cache_builder.cc +# mem/cache/coherence/coherence_protocol.cc +# mem/cache/coherence/uni_coherence.cc +# mem/cache/miss/blocking_buffer.cc +# mem/cache/miss/miss_queue.cc +# mem/cache/miss/mshr.cc +# mem/cache/miss/mshr_queue.cc +# mem/cache/prefetch/base_prefetcher.cc +# mem/cache/prefetch/prefetcher.cc +# mem/cache/prefetch/tagged_prefetcher.cc +# mem/cache/tags/base_tags.cc +# mem/cache/tags/cache_tags.cc +# mem/cache/tags/fa_lru.cc +# mem/cache/tags/iic.cc +# mem/cache/tags/lru.cc +# mem/cache/tags/repl/gen.cc +# mem/cache/tags/repl/repl.cc +# mem/cache/tags/split.cc +# mem/cache/tags/split_lru.cc +# mem/cache/tags/split_lifo.cc +# mem/functional/functional.cc +# mem/timing/base_memory.cc +# mem/timing/memory_builder.cc +# mem/timing/simple_mem_bank.cc +# mem/trace/itx_writer.cc +# mem/trace/mem_trace_writer.cc +# mem/trace/m5_writer.cc +# +# python/pyconfig.cc +# python/embedded_py.cc +# +# sim/builder.cc +# sim/configfile.cc +# sim/debug.cc +# sim/eventq.cc +# sim/main.cc +# sim/param.cc +# sim/profile.cc +# sim/root.cc +# sim/serialize.cc +# sim/sim_events.cc +# sim/sim_exit.cc +# sim/sim_object.cc +# sim/startup.cc +# sim/stat_context.cc +# sim/stat_control.cc +# sim/trace_context.cc +# ''') + +# MySql sources +arch_mysql_sources = Split(''' + ''') +# base/mysql.cc +# base/stats/mysql.cc +# ''') + +# Full-system sources +arch_full_system_sources = Split(''' + arch/alpha/alpha_memory.cc + arch/alpha/arguments.cc + arch/alpha/ev5.cc + arch/alpha/osfpal.cc + arch/alpha/pseudo_inst.cc + arch/alpha/stacktrace.cc + arch/alpha/vtophys.cc + ''') + +# base/crc.cc +# base/inet.cc +# base/remote_gdb.cc +# +# cpu/intr_control.cc +# cpu/profile.cc +# +# dev/alpha_console.cc +# dev/baddev.cc +# dev/simconsole.cc +# dev/disk_image.cc +# dev/etherbus.cc +# dev/etherdump.cc +# dev/etherint.cc +# dev/etherlink.cc +# dev/etherpkt.cc +# dev/ethertap.cc +# dev/ide_ctrl.cc +# dev/ide_disk.cc +# dev/io_device.cc +# dev/ns_gige.cc +# dev/pciconfigall.cc +# dev/pcidev.cc +# dev/pcifake.cc +# dev/pktfifo.cc +# dev/platform.cc +# dev/sinic.cc +# dev/simple_disk.cc +# dev/tsunami.cc +# dev/tsunami_cchip.cc +# dev/isa_fake.cc +# dev/tsunami_io.cc +# dev/tsunami_pchip.cc +# dev/uart.cc +# dev/uart8250.cc +# +# kern/kernel_binning.cc +# kern/kernel_stats.cc +# kern/system_events.cc +# kern/freebsd/freebsd_system.cc +# kern/linux/linux_syscalls.cc +# kern/linux/linux_system.cc +# kern/linux/printk.cc +# kern/tru64/dump_mbuf.cc +# kern/tru64/printf.cc +# kern/tru64/tru64_events.cc +# kern/tru64/tru64_syscalls.cc +# kern/tru64/tru64_system.cc +# +# mem/functional/memory_control.cc +# mem/functional/physical.cc +# +# sim/system.cc +# ''') + +# turbolaser encumbered sources +arch_turbolaser_sources = Split(''' + ''') +# encumbered/dev/dma.cc +# encumbered/dev/etherdev.cc +# encumbered/dev/scsi.cc +# encumbered/dev/scsi_ctrl.cc +# encumbered/dev/scsi_disk.cc +# encumbered/dev/scsi_none.cc +# encumbered/dev/tlaser_clock.cc +# encumbered/dev/tlaser_ipi.cc +# encumbered/dev/tlaser_mbox.cc +# encumbered/dev/tlaser_mc146818.cc +# encumbered/dev/tlaser_node.cc +# encumbered/dev/tlaser_pcia.cc +# encumbered/dev/tlaser_pcidev.cc +# encumbered/dev/tlaser_serial.cc +# encumbered/dev/turbolaser.cc +# encumbered/dev/uart8530.cc +# ''') + +# Syscall emulation (non-full-system) sources +arch_syscall_emulation_sources = Split(''' + arch/alpha/alpha_common_syscall_emul.cc + arch/alpha/alpha_linux_process.cc + arch/alpha/alpha_tru64_process.cc + ''') +# cpu/memtest/memtest.cc +# encumbered/eio/eio.cc +# encumbered/eio/exolex.cc +# encumbered/eio/libexo.cc +# sim/process.cc +# sim/syscall_emul.cc +# ''') + +#targetarch_files = Split(''' +# alpha_common_syscall_emul.hh +# alpha_linux_process.hh +# alpha_memory.hh +# alpha_tru64_process.hh +# aout_machdep.h +# arguments.hh +# byte_swap.hh +# ecoff_machdep.h +# ev5.hh +# faults.hh +# isa_fullsys_traits.hh +# isa_traits.hh +# osfpal.hh +# pseudo_inst.hh +# stacktrace.hh +# vptr.hh +# vtophys.hh +# ''') + +#for f in targetarch_files: +# env.Command('targetarch/' + f, 'arch/alpha/' + f, +# '''echo '#include "arch/alpha/%s"' > $TARGET''' % f) + + +# Set up complete list of sources based on configuration. +sources = arch_base_sources + +if env['FULL_SYSTEM']: + sources += arch_full_system_sources + if env['ALPHA_TLASER']: + sources += arch_turbolaser_sources +else: + sources += arch_syscall_emulation_sources + +if env['USE_MYSQL']: + sources += arch_mysql_sources + +for opt in env.ExportOptions: + env.ConfigFile(opt) + +################################################### +# +# Special build rules. +# +################################################### + +# base/traceflags.{cc,hh} are generated from base/traceflags.py. +# $TARGET.base will expand to "<build-dir>/base/traceflags". +# env.Command(Split('base/traceflags.hh base/traceflags.cc'), +# 'base/traceflags.py', +# 'python $SOURCE $TARGET.base') + +# several files are generated from arch/$TARGET_ISA/isa_desc. +#env.Command(Split('''decoder.cc +# decoder.hh +# alpha_o3_exec.cc +# fast_cpu_exec.cc +# simple_cpu_exec.cc +# full_cpu_exec.cc'''), +# Split('''isa_desc +# ../isa_parser.py'''), +# '$SRCDIR/arch/isa_parser.py $SOURCE $TARGET.dir arch/alpha') + + +# libelf build is described in its own SConscript file. +# SConscript-local is the per-config build, which just copies some +# header files into a place where they can be found. +# SConscript('libelf/SConscript-local', exports = 'env', duplicate=0) +# SConscript('python/SConscript', exports = ['env'], duplicate=0) + +# This function adds the specified sources to the given build +# environment, and returns a list of all the corresponding SCons +# Object nodes (including an extra one for date.cc). We explicitly +# add the Object nodes so we can set up special dependencies for +# date.cc. +# def make_objs(sources, env): +# objs = [env.Object(s) for s in sources] +# # make date.cc depend on all other objects so it always gets +# # recompiled whenever anything else does +# date_obj = env.Object('base/date.cc') +# base/traceflags.{cc,hh} are generated from base/traceflags.py. +# $TARGET.base will expand to "<build-dir>/base/traceflags". +# env.Command(Split('base/traceflags.hh base/traceflags.cc'), +# 'base/traceflags.py', +# 'python $SOURCE $TARGET.base') +# +# Split('''arch/alpha/isa_desc +# arch/isa_parser.py'''), +# env.Depends(date_obj, objs) +# objs.append(date_obj) +# return objs + +################################################### +# +# Define binaries. Each different build type (debug, opt, etc.) gets +# a slightly different build environment. +# +################################################### + +# Include file paths are rooted in this directory. SCons will +# automatically expand '.' to refer to both the source directory and +# the corresponding build directory to pick up generated include +# files. +# env.Append(CPPPATH='.') + +# Debug binary +# debugEnv = env.Copy(OBJSUFFIX='.do') +# debugEnv.Label = 'debug' +# debugEnv.Append(CCFLAGS=Split('-g -gstabs+ -O0')) +# debugEnv.Append(CPPDEFINES='DEBUG') +# tlist = debugEnv.Program(target = 'm5.debug', +# source = make_objs(sources, debugEnv)) +# debugEnv.M5Binary = tlist[0] + +# Optimized binary +# optEnv = env.Copy() +# optEnv.Label = 'opt' +# optEnv.Append(CCFLAGS=Split('-g -O5')) +# tlist = optEnv.Program(target = 'm5.opt', +# source = make_objs(sources, optEnv)) +# optEnv.M5Binary = tlist[0] + +# "Fast" binary +# fastEnv = env.Copy(OBJSUFFIX='.fo') +# fastEnv.Label = 'fast' +# fastEnv.Append(CCFLAGS=Split('-O5')) +# fastEnv.Append(CPPDEFINES='NDEBUG') +# fastEnv.Program(target = 'm5.fast.unstripped', +# source = make_objs(sources, fastEnv)) +# tlist = fastEnv.Command(target = 'm5.fast', +# source = 'm5.fast.unstripped', +# action = 'strip $SOURCE -o $TARGET') +# fastEnv.M5Binary = tlist[0] + +# Profiled binary +# profEnv = env.Copy(OBJSUFFIX='.po') +# profEnv.Label = 'prof' +# profEnv.Append(CCFLAGS=Split('-O5 -g -pg'), LINKFLAGS='-pg') +# tlist = profEnv.Program(target = 'm5.prof', +# source = make_objs(sources, profEnv)) +# profEnv.M5Binary = tlist[0] +# +# envList = [debugEnv, optEnv, fastEnv, profEnv] +# +# Return('envList') +Return('sources') diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 8f4c6bce7..6a8935963 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -91,6 +91,14 @@ tokens = reserved + ( # C preprocessor directives 'CPPDIRECTIVE' + +# The following are matched but never returned. commented out to +# suppress PLY warning + # newfile directive +# 'NEWFILE', + + # endfile directive +# 'ENDFILE' ) # Regular expressions for token matching @@ -149,10 +157,20 @@ def t_CODELIT(t): return t def t_CPPDIRECTIVE(t): - r'^\#.*\n' + r'^\#[^\#].*\n' t.lineno += t.value.count('\n') return t +def t_NEWFILE(t): + r'^\#\#newfile[ /t]*\"[A-Za-z0-9\\/-_.]*\"' + global fileNameStack + fileNameStack.append((t.value[11:-1], t.lineno)) + t.lineno = 0 + +def t_ENDFILE(t): + r'^\#\#endfile' + (filename, t.lineno) = fileNameStack.pop() + # # The functions t_NEWLINE, t_ignore, and t_error are # special for the lex module. @@ -852,7 +870,12 @@ def fixPythonIndentation(s): # Error handler. Just call exit. Output formatted to work under # Emacs compile-mode. def error(lineno, string): - sys.exit("%s:%d: %s" % (input_filename, lineno, string)) + global fileNameStack + spaces = "" + for (filename, line) in fileNameStack[0:-1]: + print spaces + "In file included from " + filename + spaces += " " + sys.exit(spaces + "%s:%d: %s" % (fileNameStack[-1][0], lineno, string)) # Like error(), but include a Python stack backtrace (for processing # Python exceptions). @@ -1601,6 +1624,25 @@ def update_if_needed(file, contents): f.write(contents) f.close() +# This regular expression matches include directives +regExp = re.compile('(?P<include>^[ \t]*##include[ \t]*\"[ \t]*(?P<filename>[A-Za-z0-9\\/-_.]*)[ \t]*\"[ \t]*\n)', re.MULTILINE) + +def preprocess_isa_desc(isa_desc): + # Find any includes and include them + + # Look for an include + m = re.search(regExp, isa_desc) + while m: + filename = m.group('filename') + print 'Including file "%s"' % filename + includeFile = open(filename) + includecontents = includeFile.read() + isa_desc = isa_desc[:m.start('include')] + '##newfile "' + filename + '"\n' + includecontents + '##endfile\n' + isa_desc[m.end('include'):] + # Look for the next include + m = re.search(regExp, isa_desc) + return isa_desc + + # # Read in and parse the ISA description. # @@ -1608,12 +1650,17 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path): # set a global var for the input filename... used in error messages global input_filename input_filename = isa_desc_file + global fileNameStack + fileNameStack = [(input_filename, 1)] # Suck the ISA description file in. input = open(isa_desc_file) isa_desc = input.read() input.close() + # Perform Preprocessing + isa_desc = preprocess_isa_desc(isa_desc) + # Parse it. (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) diff --git a/arch/mips/isa_desc/bitfields.h b/arch/mips/isa_desc/bitfields.h new file mode 100644 index 000000000..f0d6fc8d7 --- /dev/null +++ b/arch/mips/isa_desc/bitfields.h @@ -0,0 +1,51 @@ +//////////////////////////////////////////////////////////////////// +// +// Bitfield definitions. +// + +def bitfield OPCODE_HI <31:29>; +def bitfield OPCODE_LO <28:26>; + +def bitfield FUNCTION_HI < 5: 3>; +def bitfield FUNCTION_LO < 2: 0>; + +def bitfield RT <20:16>; +def bitfield RT_HI <20:19>; +def bitfield RT_LO <18:16>; + +def bitfield RS <25:21>; +def bitfield RS_HI <25:24>; +def bitfield RS_LO <23:21>; + +def bitfield RD <15:11>; + +// Floating-point operate format +def bitfield FMT <25:21>; +def bitfield FT <20:16>; +def bitfield FS <15:11>; +def bitfield FD <10:6>; + +def bitfield MOVCI <16:16>; +def bitfield MOVCF <16:16>; +def bitfield SRL <21:21>; +def bitfield SRLV < 6: 6>; +def bitfield SA <10: 6>; + +// Interrupts +def bitfield SC < 5: 5>; + +// Integer operate format(s>; +def bitfield INTIMM <15: 0>; // integer immediate (literal) + +// Branch format +def bitfield OFFSET <15: 0>; // displacement + +// Memory-format jumps +def bitfield JMPTARG <25: 0>; +def bitfield JMPHINT <10: 6>; + +def bitfield SYSCALLCODE <25: 6>; +def bitfield TRAPCODE <15:13>; + +// M5 instructions +def bitfield M5FUNC <7:0>; diff --git a/arch/mips/isa_desc/decoder.h b/arch/mips/isa_desc/decoder.h new file mode 100644 index 000000000..7e911cb45 --- /dev/null +++ b/arch/mips/isa_desc/decoder.h @@ -0,0 +1,575 @@ +//////////////////////////////////////////////////////////////////// +// +// The actual MIPS32 ISA decoder +// ----------------------------- +// The following instructions are specified in the MIPS32 ISA +// Specification. Decoding closely follows the style specified +// in the MIPS32 ISAthe specification document starting with Table +// A-2 (document available @ www.mips.com) +// +//@todo: Distinguish "unknown/future" use insts from "reserved" +// ones +decode OPCODE_HI default FailUnimpl::unknown() { + + // Derived From ... Table A-2 MIPS32 ISA Manual + 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ + + 0x0: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x1: decode MOVCI { + format Move { + 0: movc({{ }}); + 1: movt({{ }}); + } + } + + format ShiftRotate { + //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields + //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." + 0x0: sll({{ }}); + + 0x2: decode SRL { + 0: srl({{ }}); + 1: rotr({{ }}); + } + + 0x3: sar({{ }}); + + 0x4: sllv({{ }}); + + 0x6: decode SRLV { + 0: srlv({{ }}); + 1: rotrv({{ }}); + } + + 0x7: srav({{ }}); + } + } + + 0x1: decode FUNCTION_LO { + + //Table A-3 Note: "Specific encodings of the hint field are used + //to distinguish JR from JR.HB and JALR from JALR.HB" + format Jump { + 0x0: jr({{ }}); + 0x1: jalr({{ }}); + } + + format Move { + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: Syscall::syscall({{ }}); + 0x5: Break::break({{ }}); + 0x7: Synchronize::synch({{ }}); + } + + 0x2: decode FUNCTION_LO { + format MultDiv { + 0x0: mfhi({{ }}); + 0x1: mthi({{ }}); + 0x2: mflo({{ }}); + 0x3: mtlo({{ }}); + } + }; + + 0x3: decode FUNCTION_LO { + format MultDiv { + 0x0: mult({{ }}); + 0x1: multu({{ }}); + 0x2: div({{ }}); + 0x3: divu({{ }}); + } + }; + + 0x4: decode FUNCTION_LO { + format Arithmetic { + 0x0: add({{ }}); + 0x1: addu({{ }}); + 0x2: sub({{ }}); + 0x3: subu({{ }}); + } + + format Logical { + 0x0: and({{ }}); + 0x1: or({{ }}); + 0x2: xor({{ }}); + 0x3: nor({{ }}); + } + } + + 0x5: decode FUNCTION_LO { + format SetInstructions{ + 0x2: slt({{ }}); + 0x3: sltu({{ }}); + } + }; + + 0x6: decode FUNCTION_LO { + format Trap { + 0x0: tge({{ }}); + 0x1: tgeu({{ }}); + 0x2: tlt({{ }}); + 0x3: tltu({{ }}); + 0x4: teq({{ }}); + 0x6: tne({{ }}); + } + } + } + + 0x1: decode REGIMM_HI { + 0x0: decode REGIMM_LO { + format Branch { + 0x0: bltz({{ }}); + 0x1: bgez({{ }}); + + //MIPS obsolete instructions + 0x2: bltzl({{ }}); + 0x3: bgezl({{ }}); + } + } + + 0x1: decode REGIMM_LO { + format Trap { + 0x0: tgei({{ }}); + 0x1: tgeiu({{ }}); + 0x2: tlti({{ }}); + 0x3: tltiu({{ }}); + 0x4: teqi({{ }}); + 0x6: tnei({{ }}); + } + } + + 0x2: decode REGIMM_LO { + format Branch { + 0x0: bltzal({{ }}); + 0x1: bgezal({{ }}); + + //MIPS obsolete instructions + 0x2: bltzall({{ }}); + 0x3: bgezall({{ }}); + } + } + + 0x3: decode REGIMM_LO { + 0x7: synci({{ }}); + } + } + + format Jump { + 0x2: j({{ }}); + 0x3: jal({{ }}); + } + + format Branch { + 0x4: beq({{ }}); + 0x5: bne({{ }}); + 0x6: blez({{ }}); + 0x7: bgtz({{ }}); + } + }; + + 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ + format IntImmediate { + 0x0: addi({{ }}); + 0x1: addiu({{ }}); + 0x2: slti({{ }}); + 0x3: sltiu({{ }}); + 0x4: andi({{ }}); + 0x5: ori({{ }}); + 0x6: xori({{ }}); + 0x7: lui({{ }}); + }; + }; + + 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-11 MIPS32 COP0 Encoding of rs Field + 0x0: decode RS_MSB { + 0x0: decode RS { + 0x0: mfc0({{ }}); + 0xC: mtc0({{ }}); + 0xA: rdpgpr({{ }}); + + 0xB: decode SC { + 0x0: di({{ }}); + 0x1: ei({{ }}); + } + + 0xE: wrpgpr({{ }}); + } + + //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO + 0x1: decode FUNCTION { + 0x01: tlbr({{ }}); + 0x02: tlbwi({{ }}); + 0x06: tlbwr({{ }}); + 0x08: tlbp({{ }}); + 0x18: eret({{ }}); + 0x1F: deret({{ }}); + 0x20: wait({{ }}); + } + } + + //Table A-13 MIPS32 COP1 Encoding of rs Field + 0x1: decode RS_MSB { + + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc1({{ }}); + 0x2: cfc1({{ }}); + 0x3: mfhc1({{ }}); + 0x4: mtc1({{ }}); + 0x6: ctc1({{ }}); + 0x7: mftc1({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc1f({{ }}); + 0x1: bc1t({{ }}); + } + + 0x1: decode TF { + 0x0: bc1fl({{ }}); + 0x1: bc1tl({{ }}); + } + } + } + + 0x1: decode RS_HI { + 0x2: decode RS_LO { + + //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S + //(( single-word )) + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x2: recip({{ }}); + 0x3: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x1: cvt_d({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + 0x6: cvt_ps({{ }}); + } + } + } + + //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D + 0x1: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x3: div_fmt({{ }}); + 0x4: sqrt_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x1: decode RS_LO { + //only legal for 64 bit + format mode64 { + 0x0: round_l({{ }}); + 0x1: trunc_l({{ }}); + 0x2: ceil_l({{ }}); + 0x3: floor_l({{ }}); + } + + 0x4: round_w({{ }}); + 0x5: trunc_w({{ }}); + 0x6: ceil_w({{ }}); + 0x7: floor_w({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + + format mode64 { + 0x5: recip({{ }}); + 0x6: rsqrt{{ }}); + } + } + + 0x4: decode RS_LO { + 0x0: cvt_s({{ }}); + 0x4: cvt_w({{ }}); + + //only legal for 64 bit + format mode64 { + 0x5: cvt_l({{ }}); + } + } + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W + 0x4: decode FUNCTION { + 0x10: cvt_s({{ }}); + 0x10: cvt_d({{ }}); + } + + //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 + //Note: "1. Format type L is legal only if 64-bit floating point operations + //are enabled." + 0x5: decode FUNCTION_HI { + 0x10: cvt_s({{ }}); + 0x11: cvt_d({{ }}); + } + + //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 + //Note: "1. Format type PS is legal only if 64-bit floating point operations + //are enabled. " + 0x6: decode RS_HI { + 0x0: decode RS_LO { + 0x0: add_fmt({{ }}); + 0x1: sub_fmt({{ }}); + 0x2: mul_fmt({{ }}); + 0x5: abs_fmt({{ }}); + 0x6: mov_fmt({{ }}); + 0x7: neg_fmt({{ }}); + } + + 0x2: decode RS_LO { + 0x1: decode MOVCF { + 0x0: movf_fmt({{ }}); + 0x1: movt_fmt({{ }}); + } + + 0x2: movz({{ }}); + 0x3: movn({{ }}); + } + + 0x4: decode RS_LO { + 0x0: cvt_s_pu({{ }}); + } + + 0x5: decode RS_LO { + 0x0: cvt_s_pl({{ }}); + 0x4: pll_s_pl({{ }}); + 0x5: plu_s_pl({{ }}); + 0x6: pul_s_pl({{ }}); + 0x7: puu_s_pl({{ }}); + } + } + } + + //Table A-19 MIPS32 COP2 Encoding of rs Field + 0x2: decode RS_MSB { + 0x0: decode RS_HI { + 0x0: decode RS_LO { + 0x0: mfc2({{ }}); + 0x2: cfc2({{ }}); + 0x3: mfhc2({{ }}); + 0x4: mtc2({{ }}); + 0x6: ctc2({{ }}); + 0x7: mftc2({{ }}); + } + + 0x1: decode ND { + 0x0: decode TF { + 0x0: bc2f({{ }}); + 0x1: bc2t({{ }}); + } + + 0x1: decode TF { + 0x0: bc2fl({{ }}); + 0x1: bc2tl({{ }}); + } + } + } + } + + //Table A-20 MIPS64 COP1X Encoding of Function Field 1 + //Note: "COP1X instructions are legal only if 64-bit floating point + //operations are enabled." + 0x3: decode FUNCTION_HI { + 0x0: decode FUNCTION_LO { + 0x0: lwxc1({{ }}); + 0x1: ldxc1({{ }}); + 0x5: luxc1({{ }}); + } + + 0x1: decode FUNCTION_LO { + 0x0: swxc1({{ }}); + 0x1: sdxc1({{ }}); + 0x5: suxc1({{ }}); + 0x7: prefx({{ }}); + } + + 0x3: alnv_ps({{ }}); + + 0x4: decode FUNCTION_LO { + 0x0: madd_s({{ }}); + 0x1: madd_d({{ }}); + 0x6: madd_ps({{ }}); + } + + 0x5: decode FUNCTION_LO { + 0x0: msub_s({{ }}); + 0x1: msub_d({{ }}); + 0x6: msub_ps({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x0: nmadd_s({{ }}); + 0x1: nmadd_d({{ }}); + 0x6: nmadd_ps({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x0: nmsub_s({{ }}); + 0x1: nmsub_d({{ }}); + 0x6: nmsub_ps({{ }}); + } + } + + //MIPS obsolete instructions + 0x4: beql({{ }}); + 0x5: bnel({{ }}); + 0x6: blezl({{ }}); + 0x7: bgtzl({{ }}); + }; + + 0x3: decode OPCODE_LO default FailUnimpl::reserved(){ + + //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field + 0x4: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x0: madd({{ }}); + 0x1: maddu({{ }}); + 0x2: mult({{ }}); + 0x4: msub({{ }}); + 0x5: msubu({{ }}); + } + + 0x4: decode FUNCTION_LO { + 0x0: clz({{ }}); + 0x1: clo({{ }}); + } + + 0x7: decode FUNCTION_LO { + 0x7: sdbbp({{ }}); + } + } + + //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture + 0x7: decode FUNCTION_HI { + + 0x0: decode FUNCTION_LO { + 0x1: ext({{ }}); + 0x4: ins({{ }}); + } + + //Table A-10 MIPS32 BSHFL Encoding of sa Field + 0x4: decode SA { + 0x02: wsbh({{ }}); + 0x10: seb({{ }}); + 0x18: seh({{ }}); + } + + 0x6: decode FUNCTION_LO { + 0x7: rdhwr({{ }}); + } + } + }; + + 0x4: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: lb({{ }}); + 0x1: lh({{ }}); + 0x2: lwl({{ }}); + 0x3: lw({{ }}); + 0x4: lbu({{ }}); + 0x5: lhu({{ }}); + 0x6: lhu({{ }}); + }; + + 0x7: FailUnimpl::reserved({{ }}); + }; + + 0x5: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sb({{ }}); + 0x1: sh({{ }}); + 0x2: swl({{ }}); + 0x3: sw({{ }}); + 0x6: swr({{ }}); + }; + + format FailUnimpl{ + 0x4: reserved({{ }}); + 0x5: reserved({{ }}); + 0x7: cache({{ }}); + }; + + }; + + 0x6: decode OPCODE_LO default FailUnimpl::reserved(){ + format LoadMemory{ + 0x0: ll({{ }}); + 0x1: lwc1({{ }}); + 0x5: ldc1({{ }}); + }; + }; + + 0x7: decode OPCODE_LO default FailUnimpl::reserved(){ + format StoreMemory{ + 0x0: sc({{ }}); + 0x1: swc1({{ }}); + 0x5: sdc1({{ }}); + }; + + } +} + + diff --git a/arch/mips/isa_desc/formats.h b/arch/mips/isa_desc/formats.h new file mode 100644 index 000000000..404314c7a --- /dev/null +++ b/arch/mips/isa_desc/formats.h @@ -0,0 +1,22 @@ +//Include the basic format +//Templates from this format are used later +##include "m5/arch/mips/isa_desc/formats/basic.format" + +//Include the integerOp and integerOpCc format +##include "m5/arch/mips/isa_desc/formats/integerop.format" + +//Include the floatOp format +##include "m5/arch/mips/isa_desc/formats/floatop.format" + +//Include the mem format +##include "m5/arch/mips/isa_desc/formats/mem.format" + +//Include the trap format +##include "m5/arch/mips/isa_desc/formats/trap.format" + +//Include the branch format +##include "m5/arch/mips/isa_desc/formats/branch.format" + +//Include the noop format +##include "m5/arch/mips/isa_desc/formats/noop.format" + diff --git a/arch/mips/isa_desc/formats/basic.format b/arch/mips/isa_desc/formats/basic.format new file mode 100644 index 000000000..8fba9845a --- /dev/null +++ b/arch/mips/isa_desc/formats/basic.format @@ -0,0 +1,65 @@ + +// Declarations for execute() methods. +def template BasicExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +// Basic instruction class declaration template. +def template BasicDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(BasicExecDeclare)s + }; +}}; + +// Basic instruction class constructor template. +def template BasicConstructor {{ + inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + +// Basic instruction class execute method template. +def template BasicExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if(fault == No_Fault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// Basic decode template. +def template BasicDecode {{ + return new %(class_name)s(machInst); +}}; + +// Basic decode template, passing mnemonic in as string arg to constructor. +def template BasicDecodeWithMnemonic {{ + return new %(class_name)s("%(mnemonic)s", machInst); +}}; + +// The most basic instruction format... used only for a few misc. insts +def format BasicOperate(code, *flags) {{ + iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/branch.format b/arch/mips/isa_desc/formats/branch.format new file mode 100644 index 000000000..5327f30e8 --- /dev/null +++ b/arch/mips/isa_desc/formats/branch.format @@ -0,0 +1,66 @@ +//////////////////////////////////////////////////////////////////// +// +// Branch instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Branch : public MipsStaticInst + { + protected: + + /// Constructor + Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template BranchExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Branch(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = BranchExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/integerop.format b/arch/mips/isa_desc/formats/integerop.format new file mode 100644 index 000000000..6fa7feed3 --- /dev/null +++ b/arch/mips/isa_desc/formats/integerop.format @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Integer operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class IntegerOp : public MipsStaticInst + { + protected: + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template IntegerExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format IntegerOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/mem.format b/arch/mips/isa_desc/formats/mem.format new file mode 100644 index 000000000..5ed5237c5 --- /dev/null +++ b/arch/mips/isa_desc/formats/mem.format @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////////////////// +// +// Mem instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Mem : public MipsStaticInst + { + protected: + + /// Constructor + Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template MemExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + + %(op_decl)s; + %(op_rd)s; + ea_code + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(MipsException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Mem(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); +}}; + +def format Cas(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = R1;'); +}}; diff --git a/arch/mips/isa_desc/formats/noop.format b/arch/mips/isa_desc/formats/noop.format new file mode 100644 index 000000000..b1ece654d --- /dev/null +++ b/arch/mips/isa_desc/formats/noop.format @@ -0,0 +1,47 @@ +//////////////////////////////////////////////////////////////////// +// +// Noop instruction +// + +output header {{ + /** + * Base class for integer operations. + */ + class Noop : public MipsStaticInst + { + protected: + + /// Constructor + Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template NoopExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Noop(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = NoopExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/formats/trap.format b/arch/mips/isa_desc/formats/trap.format new file mode 100644 index 000000000..78f8d87b0 --- /dev/null +++ b/arch/mips/isa_desc/formats/trap.format @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// Trap instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Trap : public MipsStaticInst + { + protected: + + /// Constructor + Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TrapExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Trap(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TrapExecute.subst(iop) +}}; diff --git a/arch/mips/isa_desc/includes.h b/arch/mips/isa_desc/includes.h new file mode 100644 index 000000000..ff7cb7d1d --- /dev/null +++ b/arch/mips/isa_desc/includes.h @@ -0,0 +1,40 @@ +//////////////////////////////////////////////////////////////////// +// +// Output include file directives. +// + +output header {{ +#include <sstream> +#include <iostream> +#include <iomanip> + +#include "cpu/static_inst.hh" +#include "traps.hh" +#include "mem/mem_req.hh" // some constructors use MemReq flags +}}; + +output decoder {{ +#include "base/cprintf.hh" +#include "base/loader/symtab.hh" +#include "cpu/exec_context.hh" // for Jump::branchTarget() + +#include <math.h> +#if defined(linux) +#include <fenv.h> +#endif +}}; + +output exec {{ +#include <math.h> +#if defined(linux) +#include <fenv.h> +#endif + +#ifdef FULL_SYSTEM +//#include "arch/alpha/pseudo_inst.hh" +#endif +#include "cpu/base.hh" +#include "cpu/exetrace.hh" +#include "sim/sim_exit.hh" +}}; + diff --git a/arch/mips/isa_desc/operands.h b/arch/mips/isa_desc/operands.h new file mode 100644 index 000000000..77de6c9c4 --- /dev/null +++ b/arch/mips/isa_desc/operands.h @@ -0,0 +1,33 @@ +def operand_types {{ + 'sb' : ('signed int', 8), + 'ub' : ('unsigned int', 8), + 'shw' : ('signed int', 16), + 'uhw' : ('unsigned int', 16), + 'sw' : ('signed int', 32), + 'uw' : ('unsigned int', 32), + 'sdw' : ('signed int', 64), + 'udw' : ('unsigned int', 64), + 'sf' : ('float', 32), + 'df' : ('float', 64), + 'qf' : ('float', 128) +}}; + +def operands {{ + # Int regs default to unsigned, but code should not count on this. + # For clarity, descriptions that depend on unsigned behavior should + # explicitly specify '.uq'. + 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), + 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), + 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), + #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), + #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), + #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), + 'Mem': MemOperandTraits('udw', None, + ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), + #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), + #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + # The next two are hacks for non-full-system call-pal emulation + #'R0': IntRegOperandTraits('uq', '0', None, 1), + #'R16': IntRegOperandTraits('uq', '16', None, 1) +}}; diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc new file mode 100644 index 000000000..90a85feb6 --- /dev/null +++ b/arch/mips/isa_traits.cc @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/mips/isa_traits.hh" +#include "cpu/static_inst.hh" +#include "sim/serialize.hh" + +// Alpha UNOP (ldq_u r31,0(r0)) +// @todo: fix to MIPS specific +const MachInst MipsISA::NoopMachInst = 0x2ffe0000; + +void +MipsISA::RegFile::serialize(std::ostream &os) +{ + intRegFile.serialize(os); + floatRegFile.serialize(os); + miscRegs.serialize(os); + SERIALIZE_SCALAR(pc); + SERIALIZE_SCALAR(npc); +} + + +void +MipsISA::RegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + intRegFile.unserialize(cp, section); + floatRegFile.unserialize(cp, section); + miscRegs.unserialize(cp, section); + UNSERIALIZE_SCALAR(pc); + UNSERIALIZE_SCALAR(npc); +} + +#endif //FULL_SYSTEM diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh new file mode 100644 index 000000000..e8401cefb --- /dev/null +++ b/arch/mips/isa_traits.hh @@ -0,0 +1,528 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ +#define __ARCH_MIPS_ISA_TRAITS_HH__ + +#include "arch/mips/faults.hh" +#include "base/misc.hh" +#include "sim/host.hh" + +class FastCPU; +class FullCPU; +class Checkpoint; + +#define TARGET_MIPS + +template <class ISA> class StaticInst; +template <class ISA> class StaticInstPtr; + +//namespace EV5 +//{ +// int DTB_ASN_ASN(uint64_t reg); +// int ITB_ASN_ASN(uint64_t reg); +//} + +class MipsISA +{ + public: + + typedef uint32_t MachInst; + typedef uint64_t Addr; + typedef uint8_t RegIndex; + + enum + { + MemoryEnd = 0xffffffffffffffffULL, + + NumFloatRegs = 32, + NumMiscRegs = 32, + + MaxRegsOfAnyType = 32, + // Static instruction parameters + MaxInstSrcRegs = 3, + MaxInstDestRegs = 2, + + // Maximum trap level + MaxTL = 4 + + // semantically meaningful register indices + ZeroReg = 0, // architecturally meaningful + // the rest of these depend on the ABI + } + typedef uint64_t IntReg; + + class IntRegFile + { + private: + //For right now, let's pretend the register file is static + IntReg regs[32]; + public: + IntReg & operator [] (RegIndex index) + { + //Don't allow indexes outside of the 32 registers + index &= 0x1F + return regs[index]; + } + }; + + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regs, 32); + } + + void inline unserialize(Checkpoint &*cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, 32); + } + + class FloatRegFile + { + private: + //By using the largest data type, we ensure everything + //is aligned correctly in memory + union + { + double double rawRegs[16]; + uint64_t regDump[32]; + }; + class QuadRegs + { + private: + FloatRegFile * parent; + public: + QuadRegs(FloatRegFile * p) : parent(p) {;} + double double & operator [] (RegIndex index) + { + //Quad floats are index by the single + //precision register the start on, + //and only 16 should be accessed + index = (index >> 2) & 0xF; + return parent->rawRegs[index]; + } + }; + class DoubleRegs + { + private: + FloatRegFile * parent; + public: + DoubleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegIndex index) + { + //Double floats are index by the single + //precision register the start on, + //and only 32 should be accessed + index = (index >> 1) & 0x1F + return ((double [])parent->rawRegs)[index]; + } + } + class SingleRegs + { + private: + FloatRegFile * parent; + public: + SingleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegFile index) + { + //Only 32 single floats should be accessed + index &= 0x1F + return ((float [])parent->rawRegs)[index]; + } + } + public: + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regDump, 32); + } + + void inline unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_ARRAY(regDump, 32); + } + + QuadRegs quadRegs; + DoubleRegs doubleRegs; + SingleRegs singleRegs; + FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) + {;} + }; + + // control register file contents + typedef uint64_t MiscReg; + // The control registers, broken out into fields + class MiscRegFile + { + public: + union + { + uint16_t pstate; // Process State Register + struct + { + uint16_t ag:1; // Alternate Globals + uint16_t ie:1; // Interrupt enable + uint16_t priv:1; // Privelege mode + uint16_t am:1; // Address mask + uint16_t pef:1; // PSTATE enable floating-point + uint16_t red:1; // RED (reset, error, debug) state + uint16_t mm:2; // Memory Model + uint16_t tle:1; // Trap little-endian + uint16_t cle:1; // Current little-endian + } pstateFields; + } + uint64_t tba; // Trap Base Address + union + { + uint64_t y; // Y (used in obsolete multiplication) + struct + { + uint64_t value:32; // The actual value stored in y + const uint64_t :32; // reserved bits + } yFields; + } + uint8_t pil; // Process Interrupt Register + uint8_t cwp; // Current Window Pointer + uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) + union + { + uint8_t ccr; // Condition Code Register + struct + { + union + { + uint8_t icc:4; // 32-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } iccFields:4; + } :4; + union + { + uint8_t xcc:4; // 64-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } xccFields:4; + } :4; + } ccrFields; + } + uint8_t asi; // Address Space Identifier + uint8_t tl; // Trap Level + uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) + uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) + union + { + uint64_t tstate[MaxTL]; // Trap State + struct + { + //Values are from previous trap level + uint64_t cwp:5; // Current Window Pointer + const uint64_t :2; // Reserved bits + uint64_t pstate:10; // Process State + const uint64_t :6; // Reserved bits + uint64_t asi:8; // Address Space Identifier + uint64_t ccr:8; // Condition Code Register + } tstateFields[MaxTL]; + } + union + { + uint64_t tick; // Hardware clock-tick counter + struct + { + uint64_t counter:63; // Clock-tick count + uint64_t npt:1; // Non-priveleged trap + } tickFields; + } + uint8_t cansave; // Savable windows + uint8_t canrestore; // Restorable windows + uint8_t otherwin; // Other windows + uint8_t cleanwin; // Clean windows + union + { + uint8_t wstate; // Window State + struct + { + uint8_t normal:3; // Bits TT<4:2> are set to on a normal + // register window trap + uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" + // register window trap + } wstateFields; + } + union + { + uint64_t ver; // Version + struct + { + uint64_t maxwin:5; // Max CWP value + const uint64_t :2; // Reserved bits + uint64_t maxtl:8; // Maximum trap level + const uint64_t :8; // Reserved bits + uint64_t mask:8; // Processor mask set revision number + uint64_t impl:16; // Implementation identification number + uint64_t manuf:16; // Manufacturer code + } verFields; + } + union + { + uint64_t fsr; // Floating-Point State Register + struct + { + union + { + uint64_t cexc:5; // Current excpetion + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } cexecFields:5; + } :5; + union + { + uint64_t aexc:5; // Accrued exception + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } aexecFields:5; + } :5; + uint64_t fcc0:2; // Floating-Point condtion codes + const uint64_t :1; // Reserved bits + uint64_t qne:1; // Deferred trap queue not empty + // with no queue, it should read 0 + uint64_t ftt:3; // Floating-Point trap type + uint64_t ver:3; // Version (of the FPU) + const uint64_t :2; // Reserved bits + uint64_t ns:1; // Nonstandard floating point + union + { + uint64_t tem:5; // Trap Enable Mask + struct + { + uint64_t nxm:1; // Inexact + uint64_t dzm:1; // Divide by zero + uint64_t ufm:1; // Underflow + uint64_t ofm:1; // Overflow + uint64_t nvm:1; // Invalid operand + } temFields:5; + } :5; + const uint64_t :2; // Reserved bits + uint64_t rd:2; // Rounding direction + uint64_t fcc1:2; // Floating-Point condition codes + uint64_t fcc2:2; // Floating-Point condition codes + uint64_t fcc3:2; // Floating-Point condition codes + const uint64_t :26; // Reserved bits + } fsrFields; + } + union + { + uint8_t fprs; // Floating-Point Register State + struct + { + dl:1; // Dirty lower + du:1; // Dirty upper + fef:1; // FPRS enable floating-Point + } fprsFields; + }; + + void serialize(std::ostream & os) + { + SERIALIZE_SCALAR(pstate); + SERIAlIZE_SCALAR(tba); + SERIALIZE_SCALAR(y); + SERIALIZE_SCALAR(pil); + SERIALIZE_SCALAR(cwp); + SERIALIZE_ARRAY(tt, MaxTL); + SERIALIZE_SCALAR(ccr); + SERIALIZE_SCALAR(asi); + SERIALIZE_SCALAR(tl); + SERIALIZE_SCALAR(tpc); + SERIALIZE_SCALAR(tnpc); + SERIALIZE_ARRAY(tstate, MaxTL); + SERIALIZE_SCALAR(tick); + SERIALIZE_SCALAR(cansave); + SERIALIZE_SCALAR(canrestore); + SERIALIZE_SCALAR(otherwin); + SERIALIZE_SCALAR(cleanwin); + SERIALIZE_SCALAR(wstate); + SERIALIZE_SCALAR(ver); + SERIALIZE_SCALAR(fsr); + SERIALIZE_SCALAR(fprs); + } + + void unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_SCALAR(pstate); + UNSERIAlIZE_SCALAR(tba); + UNSERIALIZE_SCALAR(y); + UNSERIALIZE_SCALAR(pil); + UNSERIALIZE_SCALAR(cwp); + UNSERIALIZE_ARRAY(tt, MaxTL); + UNSERIALIZE_SCALAR(ccr); + UNSERIALIZE_SCALAR(asi); + UNSERIALIZE_SCALAR(tl); + UNSERIALIZE_SCALAR(tpc); + UNSERIALIZE_SCALAR(tnpc); + UNSERIALIZE_ARRAY(tstate, MaxTL); + UNSERIALIZE_SCALAR(tick); + UNSERIALIZE_SCALAR(cansave); + UNSERIALIZE_SCALAR(canrestore); + UNSERIALIZE_SCALAR(otherwin); + UNSERIALIZE_SCALAR(cleanwin); + UNSERIALIZE_SCALAR(wstate); + UNSERIALIZE_SCALAR(ver); + UNSERIALIZE_SCALAR(fsr); + UNSERIALIZE_SCALAR(fprs); + } + }; + + typedef union + { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + struct RegFile + { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + Addr pc; // Program Counter + Addr npc; // Next Program Counter + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + static StaticInstPtr<AlphaISA> decodeInst(MachInst); + + // return a no-op instruction... used for instruction fetch faults + static const MachInst NoopMachInst; + + // Instruction address compression hooks + static inline Addr realPCToFetchPC(const Addr &addr) + { + return addr; + } + + static inline Addr fetchPCToRealPC(const Addr &addr) + { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + static inline size_t fetchInstSize() + { + return sizeof(MachInst); + } + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + static void zeroRegisters(XC *xc); +}; + + +typedef MIPSISA TheISA; + +typedef TheISA::MachInst MachInst; +typedef TheISA::Addr Addr; +typedef TheISA::RegIndex RegIndex; +typedef TheISA::IntReg IntReg; +typedef TheISA::IntRegFile IntRegFile; +typedef TheISA::FloatReg FloatReg; +typedef TheISA::FloatRegFile FloatRegFile; +typedef TheISA::MiscReg MiscReg; +typedef TheISA::MiscRegFile MiscRegFile; +typedef TheISA::AnyReg AnyReg; +typedef TheISA::RegFile RegFile; + +const int VMPageSize = TheISA::VMPageSize; +const int LogVMPageSize = TheISA::LogVMPageSize; +const int ZeroReg = TheISA::ZeroReg; +const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; +const int MaxAddr = (Addr)-1; + +#ifndef FULL_SYSTEM +class SyscallReturn { + public: + template <class T> + SyscallReturn(T v, bool s) + { + retval = (uint64_t)v; + success = s; + } + + template <class T> + SyscallReturn(T v) + { + success = (v >= 0); + retval = (uint64_t)v; + } + + ~SyscallReturn() {} + + SyscallReturn& operator=(const SyscallReturn& s) { + retval = s.retval; + success = s.success; + return *this; + } + + bool successful() { return success; } + uint64_t value() { return retval; } + + + private: + uint64_t retval; + bool success; +}; + +#endif + + +#ifdef FULL_SYSTEM + +#include "arch/alpha/ev5.hh" +#endif + +#endif // __ARCH_MIPS_ISA_TRAITS_HH__ diff --git a/arch/sparc/isa_desc/base.h b/arch/sparc/isa_desc/base.h new file mode 100644 index 000000000..b504f1906 --- /dev/null +++ b/arch/sparc/isa_desc/base.h @@ -0,0 +1,82 @@ +//////////////////////////////////////////////////////////////////// +// +// Base class for sparc instructions, and some support functions +// + +output header {{ + /** + * Base class for all SPARC static instructions. + */ + class SparcStaticInst : public StaticInst<SPARCISA> + { + protected: + + // Constructor. + SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass) + : StaticInst<SPARCISA>(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; + + bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition); +}}; + +output decoder {{ + + std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // just print the first two source regs... if there's + // a third one, it's a read-modify-write dest (Rc), + // e.g. for CMOVxx + if(_numSrcRegs > 0) + { + printReg(ss, _srcRegIdx[0]); + } + if(_numSrcRegs > 1) + { + ss << ","; + printReg(ss, _srcRegIdx[1]); + } + + // just print the first dest... if there's a second one, + // it's generally implicit + if(_numDestRegs > 0) + { + if(_numSrcRegs > 0) + ss << ","; + printReg(ss, _destRegIdx[0]); + } + + return ss.str(); + } + + bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition) + { + switch(condition) + { + case 0b1000: return true; + case 0b0000: return false; + case 0b1001: return !codes.z; + case 0b0001: return codes.z; + case 0b1010: return !(codes.z | (codes.n ^ codes.v)); + case 0b0010: return codes.z | (codes.n ^ codes.v); + case 0b1011: return !(codes.n ^ codes.v); + case 0b0011: return (codes.n ^ codes.v); + case 0b1100: return !(codes.c | codes.z); + case 0b0100: return (codes.c | codes.z); + case 0b1101: return !codes.c; + case 0b0101: return codes.c; + case 0b1110: return !codes.n; + case 0b0110: return codes.n; + case 0b1111: return !codes.v; + case 0b0111: return codes.v; + } + } +}}; + diff --git a/arch/sparc/isa_desc/bitfields.h b/arch/sparc/isa_desc/bitfields.h new file mode 100644 index 000000000..b0ac57575 --- /dev/null +++ b/arch/sparc/isa_desc/bitfields.h @@ -0,0 +1,50 @@ +//////////////////////////////////////////////////////////////////// +// +// Bitfield definitions. +// + +// Bitfields are shared liberally between instruction formats, so they are +// simply defined alphabetically + +def bitfield A <29>; +def bitfield CC02 <20>; +def bitfield CC03 <25>; +def bitfield CC04 <11>; +def bitfield CC12 <21>; +def bitfield CC13 <26>; +def bitfield CC14 <12>; +def bitfield CC2 <18>; +def bitfield CMASK <6:4>; +def bitfield COND2 <28:25>; +def bitfield COND4 <17:14>; +def bitfield D16HI <21:20>; +def bitfield D16LO <13:0>; +def bitfield DISP19 <18:0>; +def bitfield DISP22 <21:0>; +def bitfield DISP30 <29:0>; +def bitfield FCN <29:26>; +def bitfield I <13>; +def bitfield IMM_ASI <12:5>; +def bitfield IMM22 <21:0>; +def bitfield MMASK <3:0>; +def bitfield OP <31:30>; +def bitfield OP2 <24:22>; +def bitfield OP3 <24:19>; +def bitfield OPF <13:5>; +def bitfield OPF_CC <13:11>; +def bitfield OPF_LOW5 <9:5>; +def bitfield OPF_LOW6 <10:5>; +def bitfield P <19>; +def bitfield RCOND2 <27:25>; +def bitfield RCOND3 <12:10>; +def bitfield RCOND4 <12:10>; +def bitfield RD <29:25>; +def bitfield RS1 <18:14>; +def bitfield RS2 <4:0>; +def bitfield SHCNT32 <4:0>; +def bitfield SHCNT64 <5:0>; +def bitfield SIMM10 <9:0>; +def bitfield SIMM11 <10:0>; +def bitfield SIMM13 <12:0>; +def bitfield SW_TRAP <6:0>; +def bitfield X <12>; diff --git a/arch/sparc/isa_desc/decoder.h b/arch/sparc/isa_desc/decoder.h new file mode 100644 index 000000000..06834ecc3 --- /dev/null +++ b/arch/sparc/isa_desc/decoder.h @@ -0,0 +1,638 @@ +//////////////////////////////////////////////////////////////////// +// +// The actual decoder specification +// + +decode OP default Trap::unknown({{illegal_instruction}}) { + + 0x0: decode OP2 { + 0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP + 0x1: Branch::bpcc({{ + switch((CC12 << 1) | CC02) + { + case 1: case 3: + throw illegal_instruction; + case 0: + if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) + ;//branchHere + break; + case 2: + if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2)) + ;//branchHere + break; + } + }});//BPcc + 0x2: Branch::bicc({{ + if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2)) + ;//branchHere + }});//Bicc + 0x3: Branch::bpr({{ + switch(RCOND) + { + case 0: case 4: + throw illegal_instruction; + case 1: + if(Rs1 == 0) ;//branchHere + break; + case 2: + if(Rs1 <= 0) ;//branchHere + break; + case 3: + if(Rs1 < 0) ;//branchHere + break; + case 5: + if(Rs1 != 0) ;//branchHere + break; + case 6: + if(Rs1 > 0) ;//branchHere + break; + case 7: + if(Rs1 >= 0) ;//branchHere + break; + } + }}); //BPr + 0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}}); //SETHI (or NOP if rd == 0 and imm == 0) + 0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc + 0x6: Trap::fbfcc({{throw fp_disabled;}}); //FBfcc + } + 0x1: Branch::call({{ + //branch here + Rd = xc->pc; + }}); + 0x2: decode OP3 { + format IntegerOp { + 0x00: add({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + Rd = Rs1.sdw + val2; + }});//ADD + 0x01: and({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = Rs1.udw & val2; + }});//AND + 0x02: or({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = Rs1.udw | val2; + }});//OR + 0x03: xor({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = Rs1.udw ^ val2; + }});//XOR + 0x04: sub({{ + INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1; + Rd = Rs1.sdw + val2; + }});//SUB + 0x05: andn({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = Rs1.udw & ~val2; + }});//ANDN + 0x06: orn({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = Rs1.udw | ~val2; + }});//ORN + 0x07: xnor({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = ~(Rs1.udw ^ val2); + }});//XNOR + 0x08: addc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; + Rd = Rs1.sdw + val2 + carryin; + }});//ADDC + 0x09: mulx({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 * val2; + }});//MULX + 0x0A: umul({{ + UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw); + Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; + xc->regs.MiscRegs.yFields.value = resTemp<63:32>; + }});//UMUL + 0x0B: smul({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw); + rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>; + xc->regs.MiscRegs.yFields.value = resTemp<63:32>; + }});//SMUL + 0x0C: subc({{ + INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1; + INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; + Rd.sdw = Rs1.sdw + val2 + carryin; + }});//SUBC + 0x0D: udivx({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + if(val2 == 0) throw division_by_zero; + Rd.udw = Rs1.udw / val2; + }});//UDIVX + 0x0E: udiv({{ + UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); + if(val2 == 0) throw division_by_zero; + resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; + INT32 overflow = (resTemp<63:32> != 0); + if(overflow) rd.udw = resTemp = 0xFFFFFFFF; + else rd.udw = resTemp; + }}); //UDIV + 0x0F: sdiv({{ + INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); + if(val2 == 0) throw division_by_zero; + Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; + INT32 overflow = (resTemp<63:31> != 0); + INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); + if(overflow) rd.udw = resTemp = 0x7FFFFFFF; + else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; + else rd.udw = resTemp; + }});//SDIV + } + format IntegerOpCc { + 0x10: addcc({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 + val2;}}, + {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, + {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//ADDcc + 0x11: andcc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 & val2;}} + ,{{0}},{{0}},{{0}},{{0}});//ANDcc + 0x12: orcc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 | val2;}} + ,{{0}},{{0}},{{0}},{{0}});//ORcc + 0x13: xorcc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 ^ val2;}} + ,{{0}},{{0}},{{0}},{{0}});//XORcc + 0x14: subcc({{ + INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 - val2;}}, + {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}}, + {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, + {{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}}, + {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} + );//SUBcc + 0x15: andncc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 & ~val2;}} + ,{{0}},{{0}},{{0}},{{0}});//ANDNcc + 0x16: orncc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = Rs1 | ~val2;}} + ,{{0}},{{0}},{{0}},{{0}});//ORNcc + 0x17: xnorcc({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2); + Rd = ~(Rs1 ^ val2);}} + ,{{0}},{{0}},{{0}},{{0}});//XNORcc + 0x18: addccc({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; + Rd = resTemp = Rs1 + val2 + carryin;}}, + {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}}, + {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, + {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//ADDCcc + 0x1A: umulcc({{ + UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1.udw<31:0> * val2<31:0>; + xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} + ,{{0}},{{0}},{{0}},{{0}});//UMULcc + 0x1B: smulcc({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>; + xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}} + ,{{0}},{{0}},{{0}},{{0}});//SMULcc + 0x1C: subccc({{ + INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2); + INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c; + Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}}, + {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}}, + {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, + {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}}, + {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} + );//SUBCcc + 0x1D: udivxcc({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw); + if(val2 == 0) throw division_by_zero; + Rd.udw = Rs1.udw / val2;}} + ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc + 0x1E: udivcc({{ + UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>); + if(val2 == 0) throw division_by_zero; + resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2; + INT32 overflow = (resTemp<63:32> != 0); + if(overflow) rd.udw = resTemp = 0xFFFFFFFF; + else rd.udw = resTemp;}}, + {{0}}, + {{overflow}}, + {{0}}, + {{0}} + );//UDIVcc + 0x1F: sdivcc({{ + INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>); + if(val2 == 0) throw division_by_zero; + Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2; + INT32 overflow = (resTemp<63:31> != 0); + INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF); + if(overflow) rd.udw = resTemp = 0x7FFFFFFF; + else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000; + else rd.udw = resTemp;}}, + {{0}}, + {{overflow || underflow}}, + {{0}}, + {{0}} + );//SDIVcc + 0x20: taddcc({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 + val2; + INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, + {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{overflow}}, + {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//TADDcc + 0x21: tsubcc({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 + val2; + INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, + {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{overflow}}, + {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//TSUBcc + 0x22: taddcctv({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 + val2; + INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); + if(overflow) throw tag_overflow;}}, + {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{overflow}}, + {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//TADDccTV + 0x23: tsubcctv({{ + INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2); + Rd = resTemp = Rs1 + val2; + INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); + if(overflow) throw tag_overflow;}}, + {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}}, + {{overflow}}, + {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, + {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} + );//TSUBccTV + 0x24: mulscc({{ + INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2); + INT32 multiplier = Rs1<31:0>; + INT32 savedLSB = Rs1<0:>; + multiplier = multipler<31:1> | + ((xc->regs.MiscRegs.ccrFields.iccFields.n + ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32); + if(!xc->regs.MiscRegs.yFields.value<0:>) + multiplicand = 0; + Rd = resTemp = multiplicand + multiplier; + xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}}, + {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}}, + {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, + {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, + {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} + );//MULScc + } + format IntegerOp + { + 0x25: decode X { + 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL + 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX + } + 0x26: decode X { + 0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL + 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX + } + 0x27: decode X { + 0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA + 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX + } + 0x28: decode RS1 { + 0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY + 0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR + 0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI + 0x4: rdtick({{ + if(xc->regs.MiscRegs.pstateFields.priv == 0 && + xc->regs.MiscRegs.tickFields.npt == 1) + throw privileged_action; + Rd = xc->regs.MiscRegs.tick; + }});//RDTICK + 0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC + 0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS + 0xF: decode I { + 0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR + 0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR + } + } + + 0x2A: decode RS1 { + 0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}}); + 0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}}); + 0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}}); + 0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}}); + 0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}}); + 0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}}); + 0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}}); + 0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}}); + 0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}}); + 0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}}); + 0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}}); + 0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}}); + 0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}}); + 0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}}); + 0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}}); + 0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now. + } + 0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW + 0x2C: movcc({{ + ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0); + switch(ccBank) + { + case 0: case 1: case 2: case 3: + throw fp_disabled; + break; + case 5: case 7: + throw illegal_instruction; + break; + case 4: + if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4)) + Rd = (I ? SIMM11.sdw : RS2); + break; + case 6: + if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4)) + Rd = (I ? SIMM11.sdw : RS2); + break; + } + }});//MOVcc + 0x2D: sdivx({{ + INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + if(val2 == 0) throw division_by_zero; + Rd.sdw = Rs1.sdw / val2; + }});//SDIVX + 0x2E: decode RS1 { + 0x0: IntegerOp::popc({{ + INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw); + UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4} + for(unsigned int x = 0; x < 16; x++) + { + count += oneBits[val2 & 0xF]; + val2 >> 4; + } + }});//POPC + } + 0x2F: movr({{ + UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw); + switch(RCOND) + { + case 0: case 4: + throw illegal_instruction; + break; + case 1: + if(Rs1 == 0) Rd = val2; + break; + case 2: + if(Rs1 <= 0) Rd = val2; + break; + case 3: + if(Rs1 = 0) Rd = val2; + break; + case 5: + if(Rs1 != 0) Rd = val2; + break; + case 6: + if(Rs1 > 0) Rd = val2; + break; + case 7: + if(Rs1 >= 0) Rd = val2; + break; + } + }});//MOVR + 0x30: decode RD { + 0x0: wry({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.y = Rs1 ^ val2; + }});//WRY + 0x2: wrccr({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.ccr = Rs1 ^ val2; + }});//WRCCR + 0x3: wrasi({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.asi = Rs1 ^ val2; + }});//WRASI + 0x6: wrfprs({{ + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.asi = Rs1 ^ val2; + }});//WRFPRS + 0xF: Trap::sir({{software_initiated_reset}}); //SIR + } + 0x31: decode FCN { + 0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED + 0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED + } + 0x32: decode RD { + 0x0: wrprtpc({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; + }}); + 0x1: wrprtnpc({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2; + }}); + 0x2: wrprtstate({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2; + }}); + 0x3: wrprtt({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2; + }}); + 0x4: wrprtick({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tick = Rs1 ^ val2; + }}); + 0x5: wrprtba({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tba = Rs1 ^ val2; + }}); + 0x6: wrprpstate({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.pstate = Rs1 ^ val2; + }}); + 0x7: wrprtl({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.tl = Rs1 ^ val2; + }}); + 0x8: wrprpil({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.pil = Rs1 ^ val2; + }}); + 0x9: wrprcwp({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.cwp = Rs1 ^ val2; + }}); + 0xA: wrprcansave({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.cansave = Rs1 ^ val2; + }}); + 0xB: wrprcanrestore({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.canrestore = Rs1 ^ val2; + }}); + 0xC: wrprcleanwin({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.cleanwin = Rs1 ^ val2; + }}); + 0xD: wrprotherwin({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.otherwin = Rs1 ^ val2; + }}); + 0xE: wrprwstate({{checkPriv + UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw); + xc->regs.MiscRegs.wstate = Rs1 ^ val2; + }}); + } + + 0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1 + 0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2 + + + 0x38: Branch::jmpl({{//Stuff}}); //JMPL + 0x39: Branch::return({{//Other Stuff}}); //RETURN + 0x3A: Trap::tcc({{ + switch((CC14 << 1) | (CC04 << 0)) + { + case 1: case 3: + throw illegal_instruction; + case 0: + if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) + throw trap_instruction; + break; + case 2: + if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) + throw trap_instruction; + break; + } + }}); //Tcc + 0x3B: BasicOperate::flush({{//Lala}}); //FLUSH + 0x3C: BasicOperate::save({{//leprechauns); //SAVE + 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE + 0x3E: decode FCN { + 0x1: BasicOperate::done({{//Done thing}}); //DONE + 0x2: BasicOperate::retry({{//Retry thing}}); //RETRY + } + } + } + 0x3: decode OP3 { + format Mem { + 0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW + 0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB + 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH + 0x03: ldd({{ + UINT64 val = Mem.udw; + setIntReg(RD & (~1), val<31:0>); + setIntReg(RD | 1, val<63:32>); + }});//LDD + 0x04: stw({{Mem.sw = Rd.sw;}}); //STW + 0x05: stb({{Mem.sb = Rd.sb;}}); //STB + 0x06: sth({{Mem.shw = Rd.shw;}}); //STH + 0x07: std({{ + Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); + }});//STD + 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW + 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB + 0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH + 0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX + + 0x0D: ldstub({{ + Rd.ub = Mem.ub; + Mem.ub = 0xFF; + }}); //LDSTUB + 0x0E: stx({{Rd.udw = Mem.udw;}}); //STX + 0x0F: swap({{ + UINT32 temp = Rd.uw; + Rd.uw = Mem.uw; + Mem.uw = temp; + }}); //SWAP + 0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA + 0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA + 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA + 0x13: ldda({{ + UINT64 val = Mem.udw; + setIntReg(RD & (~1), val<31:0>); + setIntReg(RD | 1, val<63:32>); + }}); //LDDA + 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA + 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA + 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA + 0x17: stda({{ + Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); + }}); //STDA + 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA + 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA + 0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA + 0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA + + 0x1D: ldstuba({{ + Rd.ub = Mem.ub; + Mem.ub = 0xFF; + }}); //LDSTUBA + 0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA + 0x1F: swapa({{ + UINT32 temp = Rd.uw; + Rd.uw = Mem.uw; + Mem.uw = temp; + }}); //SWAPA + 0x20: Trap::ldf({{throw fp_disabled;}}); //LDF + 0x21: decode X { + 0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR + 0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR + } + 0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF + 0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF + 0x24: Trap::stf({{throw fp_disabled;}}); //STF + 0x25: decode X { + 0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR + 0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR + } + 0x26: Trap::stqf({{throw fp_disabled;}}); //STQF + 0x27: Trap::stdf({{throw fp_disabled;}}); //STDF + + + + + + 0x2D: Noop::prefetch({{ }}); //PREFETCH + + + 0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA + + 0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA + 0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA + 0x34: Trap::stfa({{throw fp_disabled;}}); //STFA + 0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA + 0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA + + + + + + 0x3C: Cas::casa( + {{UINT64 val = Mem.uw; + if(Rs2.uw == val) + Mem.uw = Rd.uw; + Rd.uw = val; + }}); //CASA + 0x3D: Noop::prefetcha({{ }}); //PREFETCHA + 0x3E: Cas::casxa( + {{UINT64 val = Mem.udw; + if(Rs2 == val) + Mem.udw = Rd; + Rd = val; + }}); //CASXA + } + } +} diff --git a/arch/sparc/isa_desc/formats.h b/arch/sparc/isa_desc/formats.h new file mode 100644 index 000000000..733a093f5 --- /dev/null +++ b/arch/sparc/isa_desc/formats.h @@ -0,0 +1,19 @@ +//Include the basic format +//Templates from this format are used later +##include "m5/arch/sparc/isa_desc/formats/basic.format" + +//Include the integerOp and integerOpCc format +##include "m5/arch/sparc/isa_desc/formats/integerop.format" + +//Include the mem format +##include "m5/arch/sparc/isa_desc/formats/mem.format" + +//Include the trap format +##include "m5/arch/sparc/isa_desc/formats/trap.format" + +//Include the branch format +##include "m5/arch/sparc/isa_desc/formats/branch.format" + +//Include the noop format +##include "m5/arch/sparc/isa_desc/formats/noop.format" + diff --git a/arch/sparc/isa_desc/formats/basic.format b/arch/sparc/isa_desc/formats/basic.format new file mode 100644 index 000000000..1994df41c --- /dev/null +++ b/arch/sparc/isa_desc/formats/basic.format @@ -0,0 +1,65 @@ + +// Declarations for execute() methods. +def template BasicExecDeclare {{ + Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +// Basic instruction class declaration template. +def template BasicDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + /// Constructor. + %(class_name)s(MachInst machInst); + %(BasicExecDeclare)s + }; +}}; + +// Basic instruction class constructor template. +def template BasicConstructor {{ + inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + +// Basic instruction class execute method template. +def template BasicExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + Fault fault = No_Fault; + + %(fp_enable_check)s; + %(op_decl)s; + %(op_rd)s; + %(code)s; + + if(fault == No_Fault) + { + %(op_wb)s; + } + return fault; + } +}}; + +// Basic decode template. +def template BasicDecode {{ + return new %(class_name)s(machInst); +}}; + +// Basic decode template, passing mnemonic in as string arg to constructor. +def template BasicDecodeWithMnemonic {{ + return new %(class_name)s("%(mnemonic)s", machInst); +}}; + +// The most basic instruction format... used only for a few misc. insts +def format BasicOperate(code, *flags) {{ + iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BasicExecute.subst(iop) +}}; diff --git a/arch/sparc/isa_desc/formats/branch.format b/arch/sparc/isa_desc/formats/branch.format new file mode 100644 index 000000000..c4c0a90af --- /dev/null +++ b/arch/sparc/isa_desc/formats/branch.format @@ -0,0 +1,66 @@ +//////////////////////////////////////////////////////////////////// +// +// Branch instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Branch : public SparcStaticInst + { + protected: + + /// Constructor + Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template BranchExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(SparcException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Branch(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = BranchExecute.subst(iop) +}}; diff --git a/arch/sparc/isa_desc/formats/integerop.format b/arch/sparc/isa_desc/formats/integerop.format new file mode 100644 index 000000000..275a346d3 --- /dev/null +++ b/arch/sparc/isa_desc/formats/integerop.format @@ -0,0 +1,110 @@ +//////////////////////////////////////////////////////////////////// +// +// Integer operate instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class IntegerOp : public SparcStaticInst + { + protected: + + /// Constructor + IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template IntegerExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //These are set to constants when the execute method + //is generated + bool useCc = ; + bool checkPriv = ; + + //Attempt to execute the instruction + try + { + checkPriv; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(SparcException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + if(useCc) + { + xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63); + xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0); + xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue; + xc->regs.miscRegFile.ccrFields.iccFields.c = icValue; + xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31); + xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0); + xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue; + xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue; + } + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format IntegerOp(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', '0'), ('icValue', '0'), + ('xvValue', '0'), ('xcValue', '0')): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; + +// Primary format for integer operate instructions: +def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + checkPriv = (code.find('checkPriv') != -1) + code.replace('checkPriv', '') + if checkPriv: + code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;') + else: + code.replace('checkPriv;', '') + for (marker, value) in (('ivValue', ivValue), ('icValue', icValue), + ('xvValue', xvValue), ('xcValue', xcValue)): + code.replace(marker, value) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = IntegerExecute.subst(iop) +}}; diff --git a/arch/sparc/isa_desc/formats/mem.format b/arch/sparc/isa_desc/formats/mem.format new file mode 100644 index 000000000..abc00b6f2 --- /dev/null +++ b/arch/sparc/isa_desc/formats/mem.format @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////////////////// +// +// Mem instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Mem : public SparcStaticInst + { + protected: + + /// Constructor + Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template MemExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Attempt to execute the instruction + try + { + + %(op_decl)s; + %(op_rd)s; + ea_code + %(code)s; + } + //If we have an exception for some reason, + //deal with it + catch(SparcException except) + { + //Deal with exception + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Mem(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;'); +}}; + +def format Cas(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = MemExecute.subst(iop) + exec_output.replace('ea_code', 'EA = R1;'); +}}; diff --git a/arch/sparc/isa_desc/formats/noop.format b/arch/sparc/isa_desc/formats/noop.format new file mode 100644 index 000000000..bc83e3261 --- /dev/null +++ b/arch/sparc/isa_desc/formats/noop.format @@ -0,0 +1,47 @@ +//////////////////////////////////////////////////////////////////// +// +// Noop instruction +// + +output header {{ + /** + * Base class for integer operations. + */ + class Noop : public SparcStaticInst + { + protected: + + /// Constructor + Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template NoopExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Nothing to see here, move along + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Noop(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = NoopExecute.subst(iop) +}}; diff --git a/arch/sparc/isa_desc/formats/trap.format b/arch/sparc/isa_desc/formats/trap.format new file mode 100644 index 000000000..bee77fe69 --- /dev/null +++ b/arch/sparc/isa_desc/formats/trap.format @@ -0,0 +1,53 @@ +//////////////////////////////////////////////////////////////////// +// +// Trap instructions +// + +output header {{ + /** + * Base class for integer operations. + */ + class Trap : public SparcStaticInst + { + protected: + + /// Constructor + Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) + { + } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + return "Disassembly of integer instruction\n"; + } +}}; + +def template TrapExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const + { + //Call into the trap handler with the appropriate fault + return No_Fault; + } + + //Write the resulting state to the execution context + %(op_wb)s; + + return No_Fault; + } +}}; + +// Primary format for integer operate instructions: +def format Trap(code, *opt_flags) {{ + orig_code = code + cblk = CodeBlock(code) + iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + decode_block = BasicDecodeWithMnemonic.subst(iop) + exec_output = TrapExecute.subst(iop) +}}; diff --git a/arch/sparc/isa_desc/includes.h b/arch/sparc/isa_desc/includes.h new file mode 100644 index 000000000..ff7cb7d1d --- /dev/null +++ b/arch/sparc/isa_desc/includes.h @@ -0,0 +1,40 @@ +//////////////////////////////////////////////////////////////////// +// +// Output include file directives. +// + +output header {{ +#include <sstream> +#include <iostream> +#include <iomanip> + +#include "cpu/static_inst.hh" +#include "traps.hh" +#include "mem/mem_req.hh" // some constructors use MemReq flags +}}; + +output decoder {{ +#include "base/cprintf.hh" +#include "base/loader/symtab.hh" +#include "cpu/exec_context.hh" // for Jump::branchTarget() + +#include <math.h> +#if defined(linux) +#include <fenv.h> +#endif +}}; + +output exec {{ +#include <math.h> +#if defined(linux) +#include <fenv.h> +#endif + +#ifdef FULL_SYSTEM +//#include "arch/alpha/pseudo_inst.hh" +#endif +#include "cpu/base.hh" +#include "cpu/exetrace.hh" +#include "sim/sim_exit.hh" +}}; + diff --git a/arch/sparc/isa_desc/isa_desc b/arch/sparc/isa_desc/isa_desc new file mode 100644 index 000000000..1a5cc4a56 --- /dev/null +++ b/arch/sparc/isa_desc/isa_desc @@ -0,0 +1,61 @@ +// -*- mode:c++ -*- + +//Copyright (c) 2003, 2004, 2005 +//The Regents of The University of Michigan +//All Rights Reserved + +//This code is part of the M5 simulator, developed by Nathan Binkert, +//Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions +//from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi, +//and Andrew Schultz. + +//Permission is granted to use, copy, create derivative works and +//redistribute this software and such derivative works for any purpose, +//so long as the copyright notice above, this grant of permission, and +//the disclaimer below appear in all copies made; and so long as the +//name of The University of Michigan is not used in any advertising or +//publicity pertaining to the use or distribution of this software +//without specific, written prior authorization. + +//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE +//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT +//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR +//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF +//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF +//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, +//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION +//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER +//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +//////////////////////////////////////////////////////////////////// +// +// SPARC ISA description file. +// +//////////////////////////////////////////////////////////////////// + +//Include the C++ include directives +##include "m5/arch/sparc/isa_desc/includes.h" + +//////////////////////////////////////////////////////////////////// +// +// Namespace statement. Everything below this line will be in the +// SparcISAInst namespace. +// + +namespace SparcISA; + +//Include the bitfield definitions +##include "m5/arch/sparc/isa_desc/bitfields.h" + +//Include the operand_types and operand definitions +##include "m5/arch/sparc/isa_desc/operands.h" + +//Include the base class for sparc instructions, and some support code +##include "m5/arch/sparc/isa_desc/base.h" + +//Include the definitions for the instruction formats +##include "m5/arch/sparc/isa_desc/formats.h" + +//Include the decoder definition +##include "m5/arch/sparc/isa_desc/decoder.h" diff --git a/arch/sparc/isa_desc/operands.h b/arch/sparc/isa_desc/operands.h new file mode 100644 index 000000000..77de6c9c4 --- /dev/null +++ b/arch/sparc/isa_desc/operands.h @@ -0,0 +1,33 @@ +def operand_types {{ + 'sb' : ('signed int', 8), + 'ub' : ('unsigned int', 8), + 'shw' : ('signed int', 16), + 'uhw' : ('unsigned int', 16), + 'sw' : ('signed int', 32), + 'uw' : ('unsigned int', 32), + 'sdw' : ('signed int', 64), + 'udw' : ('unsigned int', 64), + 'sf' : ('float', 32), + 'df' : ('float', 64), + 'qf' : ('float', 128) +}}; + +def operands {{ + # Int regs default to unsigned, but code should not count on this. + # For clarity, descriptions that depend on unsigned behavior should + # explicitly specify '.uq'. + 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1), + 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2), + 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3), + #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1), + #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2), + #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3), + 'Mem': MemOperandTraits('udw', None, + ('IsMemRef', 'IsLoad', 'IsStore'), 4) + #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4), + #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1), + #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1), + # The next two are hacks for non-full-system call-pal emulation + #'R0': IntRegOperandTraits('uq', '0', None, 1), + #'R16': IntRegOperandTraits('uq', '16', None, 1) +}}; diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh new file mode 100644 index 000000000..9513b99fc --- /dev/null +++ b/arch/sparc/isa_traits.hh @@ -0,0 +1,528 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ +#define __ARCH_SPARC_ISA_TRAITS_HH__ + +#include "arch/sparc/faults.hh" +#include "base/misc.hh" +#include "sim/host.hh" + +class FastCPU; +//class FullCPU; +//class Checkpoint; + +#define TARGET_SPARC + +template <class ISA> class StaticInst; +template <class ISA> class StaticInstPtr; + +//namespace EV5 +//{ +// int DTB_ASN_ASN(uint64_t reg); +// int ITB_ASN_ASN(uint64_t reg); +//} + +class SPARCISA +{ + public: + + typedef uint32_t MachInst; + typedef uint64_t Addr; + typedef uint8_t RegIndex; + + enum + { + MemoryEnd = 0xffffffffffffffffULL, + + NumFloatRegs = 32, + NumMiscRegs = 32, + + MaxRegsOfAnyType = 32, + // Static instruction parameters + MaxInstSrcRegs = 3, + MaxInstDestRegs = 2, + + // Maximum trap level + MaxTL = 4 + + // semantically meaningful register indices + ZeroReg = 0, // architecturally meaningful + // the rest of these depend on the ABI + } + typedef uint64_t IntReg; + + class IntRegFile + { + private: + //For right now, let's pretend the register file is static + IntReg regs[32]; + public: + IntReg & operator [] (RegIndex index) + { + //Don't allow indexes outside of the 32 registers + index &= 0x1F + return regs[index]; + } + }; + + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regs, 32); + } + + void inline unserialize(Checkpoint &*cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, 32); + } + + class FloatRegFile + { + private: + //By using the largest data type, we ensure everything + //is aligned correctly in memory + union + { + double double rawRegs[16]; + uint64_t regDump[32]; + }; + class QuadRegs + { + private: + FloatRegFile * parent; + public: + QuadRegs(FloatRegFile * p) : parent(p) {;} + double double & operator [] (RegIndex index) + { + //Quad floats are index by the single + //precision register the start on, + //and only 16 should be accessed + index = (index >> 2) & 0xF; + return parent->rawRegs[index]; + } + }; + class DoubleRegs + { + private: + FloatRegFile * parent; + public: + DoubleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegIndex index) + { + //Double floats are index by the single + //precision register the start on, + //and only 32 should be accessed + index = (index >> 1) & 0x1F + return ((double [])parent->rawRegs)[index]; + } + } + class SingleRegs + { + private: + FloatRegFile * parent; + public: + SingleRegs(FloatRegFile * p) : parent(p) {;} + double & operator [] (RegFile index) + { + //Only 32 single floats should be accessed + index &= 0x1F + return ((float [])parent->rawRegs)[index]; + } + } + public: + void inline serialize(std::ostream & os) + { + SERIALIZE_ARRAY(regDump, 32); + } + + void inline unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_ARRAY(regDump, 32); + } + + QuadRegs quadRegs; + DoubleRegs doubleRegs; + SingleRegs singleRegs; + FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) + {;} + }; + + // control register file contents + typedef uint64_t MiscReg; + // The control registers, broken out into fields + class MiscRegFile + { + public: + union + { + uint16_t pstate; // Process State Register + struct + { + uint16_t ag:1; // Alternate Globals + uint16_t ie:1; // Interrupt enable + uint16_t priv:1; // Privelege mode + uint16_t am:1; // Address mask + uint16_t pef:1; // PSTATE enable floating-point + uint16_t red:1; // RED (reset, error, debug) state + uint16_t mm:2; // Memory Model + uint16_t tle:1; // Trap little-endian + uint16_t cle:1; // Current little-endian + } pstateFields; + } + uint64_t tba; // Trap Base Address + union + { + uint64_t y; // Y (used in obsolete multiplication) + struct + { + uint64_t value:32; // The actual value stored in y + const uint64_t :32; // reserved bits + } yFields; + } + uint8_t pil; // Process Interrupt Register + uint8_t cwp; // Current Window Pointer + uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) + union + { + uint8_t ccr; // Condition Code Register + struct + { + union + { + uint8_t icc:4; // 32-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } iccFields:4; + } :4; + union + { + uint8_t xcc:4; // 64-bit condition codes + struct + { + uint8_t c:1; // Carry + uint8_t v:1; // Overflow + uint8_t z:1; // Zero + uint8_t n:1; // Negative + } xccFields:4; + } :4; + } ccrFields; + } + uint8_t asi; // Address Space Identifier + uint8_t tl; // Trap Level + uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) + uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) + union + { + uint64_t tstate[MaxTL]; // Trap State + struct + { + //Values are from previous trap level + uint64_t cwp:5; // Current Window Pointer + const uint64_t :2; // Reserved bits + uint64_t pstate:10; // Process State + const uint64_t :6; // Reserved bits + uint64_t asi:8; // Address Space Identifier + uint64_t ccr:8; // Condition Code Register + } tstateFields[MaxTL]; + } + union + { + uint64_t tick; // Hardware clock-tick counter + struct + { + uint64_t counter:63; // Clock-tick count + uint64_t npt:1; // Non-priveleged trap + } tickFields; + } + uint8_t cansave; // Savable windows + uint8_t canrestore; // Restorable windows + uint8_t otherwin; // Other windows + uint8_t cleanwin; // Clean windows + union + { + uint8_t wstate; // Window State + struct + { + uint8_t normal:3; // Bits TT<4:2> are set to on a normal + // register window trap + uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" + // register window trap + } wstateFields; + } + union + { + uint64_t ver; // Version + struct + { + uint64_t maxwin:5; // Max CWP value + const uint64_t :2; // Reserved bits + uint64_t maxtl:8; // Maximum trap level + const uint64_t :8; // Reserved bits + uint64_t mask:8; // Processor mask set revision number + uint64_t impl:16; // Implementation identification number + uint64_t manuf:16; // Manufacturer code + } verFields; + } + union + { + uint64_t fsr; // Floating-Point State Register + struct + { + union + { + uint64_t cexc:5; // Current excpetion + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } cexecFields:5; + } :5; + union + { + uint64_t aexc:5; // Accrued exception + struct + { + uint64_t nxc:1; // Inexact + uint64_t dzc:1; // Divide by zero + uint64_t ufc:1; // Underflow + uint64_t ofc:1; // Overflow + uint64_t nvc:1; // Invalid operand + } aexecFields:5; + } :5; + uint64_t fcc0:2; // Floating-Point condtion codes + const uint64_t :1; // Reserved bits + uint64_t qne:1; // Deferred trap queue not empty + // with no queue, it should read 0 + uint64_t ftt:3; // Floating-Point trap type + uint64_t ver:3; // Version (of the FPU) + const uint64_t :2; // Reserved bits + uint64_t ns:1; // Nonstandard floating point + union + { + uint64_t tem:5; // Trap Enable Mask + struct + { + uint64_t nxm:1; // Inexact + uint64_t dzm:1; // Divide by zero + uint64_t ufm:1; // Underflow + uint64_t ofm:1; // Overflow + uint64_t nvm:1; // Invalid operand + } temFields:5; + } :5; + const uint64_t :2; // Reserved bits + uint64_t rd:2; // Rounding direction + uint64_t fcc1:2; // Floating-Point condition codes + uint64_t fcc2:2; // Floating-Point condition codes + uint64_t fcc3:2; // Floating-Point condition codes + const uint64_t :26; // Reserved bits + } fsrFields; + } + union + { + uint8_t fprs; // Floating-Point Register State + struct + { + dl:1; // Dirty lower + du:1; // Dirty upper + fef:1; // FPRS enable floating-Point + } fprsFields; + }; + + void serialize(std::ostream & os) + { + SERIALIZE_SCALAR(pstate); + SERIAlIZE_SCALAR(tba); + SERIALIZE_SCALAR(y); + SERIALIZE_SCALAR(pil); + SERIALIZE_SCALAR(cwp); + SERIALIZE_ARRAY(tt, MaxTL); + SERIALIZE_SCALAR(ccr); + SERIALIZE_SCALAR(asi); + SERIALIZE_SCALAR(tl); + SERIALIZE_SCALAR(tpc); + SERIALIZE_SCALAR(tnpc); + SERIALIZE_ARRAY(tstate, MaxTL); + SERIALIZE_SCALAR(tick); + SERIALIZE_SCALAR(cansave); + SERIALIZE_SCALAR(canrestore); + SERIALIZE_SCALAR(otherwin); + SERIALIZE_SCALAR(cleanwin); + SERIALIZE_SCALAR(wstate); + SERIALIZE_SCALAR(ver); + SERIALIZE_SCALAR(fsr); + SERIALIZE_SCALAR(fprs); + } + + void unserialize(Checkpoint &* cp, std::string & section) + { + UNSERIALIZE_SCALAR(pstate); + UNSERIAlIZE_SCALAR(tba); + UNSERIALIZE_SCALAR(y); + UNSERIALIZE_SCALAR(pil); + UNSERIALIZE_SCALAR(cwp); + UNSERIALIZE_ARRAY(tt, MaxTL); + UNSERIALIZE_SCALAR(ccr); + UNSERIALIZE_SCALAR(asi); + UNSERIALIZE_SCALAR(tl); + UNSERIALIZE_SCALAR(tpc); + UNSERIALIZE_SCALAR(tnpc); + UNSERIALIZE_ARRAY(tstate, MaxTL); + UNSERIALIZE_SCALAR(tick); + UNSERIALIZE_SCALAR(cansave); + UNSERIALIZE_SCALAR(canrestore); + UNSERIALIZE_SCALAR(otherwin); + UNSERIALIZE_SCALAR(cleanwin); + UNSERIALIZE_SCALAR(wstate); + UNSERIALIZE_SCALAR(ver); + UNSERIALIZE_SCALAR(fsr); + UNSERIALIZE_SCALAR(fprs); + } + }; + + typedef union + { + IntReg intreg; + FloatReg fpreg; + MiscReg ctrlreg; + } AnyReg; + + struct RegFile + { + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + Addr pc; // Program Counter + Addr npc; // Next Program Counter + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + }; + + static StaticInstPtr<AlphaISA> decodeInst(MachInst); + + // return a no-op instruction... used for instruction fetch faults + static const MachInst NoopMachInst; + + // Instruction address compression hooks + static inline Addr realPCToFetchPC(const Addr &addr) + { + return addr; + } + + static inline Addr fetchPCToRealPC(const Addr &addr) + { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + static inline size_t fetchInstSize() + { + return sizeof(MachInst); + } + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template <class XC> + static void zeroRegisters(XC *xc); +}; + + +typedef SPARCISA TheISA; + +typedef TheISA::MachInst MachInst; +typedef TheISA::Addr Addr; +typedef TheISA::RegIndex RegIndex; +typedef TheISA::IntReg IntReg; +typedef TheISA::IntRegFile IntRegFile; +typedef TheISA::FloatReg FloatReg; +typedef TheISA::FloatRegFile FloatRegFile; +typedef TheISA::MiscReg MiscReg; +typedef TheISA::MiscRegFile MiscRegFile; +typedef TheISA::AnyReg AnyReg; +typedef TheISA::RegFile RegFile; + +const int VMPageSize = TheISA::VMPageSize; +const int LogVMPageSize = TheISA::LogVMPageSize; +const int ZeroReg = TheISA::ZeroReg; +const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; +const int MaxAddr = (Addr)-1; + +#ifndef FULL_SYSTEM +class SyscallReturn { + public: + template <class T> + SyscallReturn(T v, bool s) + { + retval = (uint64_t)v; + success = s; + } + + template <class T> + SyscallReturn(T v) + { + success = (v >= 0); + retval = (uint64_t)v; + } + + ~SyscallReturn() {} + + SyscallReturn& operator=(const SyscallReturn& s) { + retval = s.retval; + success = s.success; + return *this; + } + + bool successful() { return success; } + uint64_t value() { return retval; } + + + private: + uint64_t retval; + bool success; +}; + +#endif + + +#ifdef FULL_SYSTEM + +#include "arch/alpha/ev5.hh" +#endif + +#endif // __ARCH_SPARC_ISA_TRAITS_HH__ diff --git a/build/SConstruct b/build/SConstruct index 45461b0af..72b0930e1 100644 --- a/build/SConstruct +++ b/build/SConstruct @@ -223,7 +223,7 @@ env = conf.Finish() # value becomes sticky). sticky_opts = Options(args=ARGUMENTS) sticky_opts.AddOptions( - EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha')), + EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha', 'sparc')), BoolOption('FULL_SYSTEM', 'Full-system support', False), BoolOption('ALPHA_TLASER', 'Model Alpha TurboLaser platform (vs. Tsunami)', False), @@ -320,6 +320,10 @@ base_env = env for build_dir in build_dirs: # Make a copy of the default environment to use for this config. env = base_env.Copy() + + # Record what build_dir was in the environment + env.Append(BUILD_DIR=build_dir); + # Set env according to the build directory config. sticky_opts.files = [] diff --git a/build/build_options/default/SPARC_SE b/build/build_options/default/SPARC_SE new file mode 100644 index 000000000..3b256fc34 --- /dev/null +++ b/build/build_options/default/SPARC_SE @@ -0,0 +1,2 @@ +TARGET_ISA = 'sparc' +FULL_SYSTEM = 0 |