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-rw-r--r--src/cpu/o3/lsq_unit.hh39
1 files changed, 18 insertions, 21 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 512124bb4..7b65ef556 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -626,20 +626,27 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
++usedPorts;
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
- data_pkt->dataStatic(load_inst->memData);
-
- LSQSenderState *state = new LSQSenderState;
- state->isLoad = true;
- state->idx = load_idx;
- state->inst = load_inst;
- data_pkt->senderState = state;
-
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
+ PacketPtr data_pkt =
+ new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ data_pkt->dataStatic(load_inst->memData);
+
+ LSQSenderState *state = new LSQSenderState;
+ state->isLoad = true;
+ state->idx = load_idx;
+ state->inst = load_inst;
+ data_pkt->senderState = state;
+
if (!dcachePort->sendTiming(data_pkt)) {
- if (data_pkt->result == Packet::BadAddress) {
- delete data_pkt;
+ Packet::Result result = data_pkt->result;
+
+ // Delete state and data packet because a load retry
+ // initiates a pipeline restart; it does not retry.
+ delete state;
+ delete data_pkt;
+
+ if (result == Packet::BadAddress) {
return TheISA::genMachineCheckFault();
}
@@ -669,16 +676,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
return NoFault;
}
- if (data_pkt->result != Packet::Success) {
- DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
- DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
- load_inst->seqNum);
- } else {
- DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
- DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
- load_inst->seqNum);
- }
-
return NoFault;
}