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-rw-r--r--src/cpu/memtest/memtest.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh3
-rw-r--r--src/cpu/ozone/lw_lsq.hh3
-rw-r--r--src/dev/io_device.hh3
-rw-r--r--src/mem/bridge.hh3
-rw-r--r--src/mem/cache/cache_impl.hh3
-rw-r--r--src/mem/packet.hh4
7 files changed, 14 insertions, 8 deletions
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index ac2d0a058..43f141af6 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -35,6 +35,7 @@
#include <set>
#include "base/statistics.hh"
+#include "base/fast_alloc.hh"
#include "params/MemTest.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
@@ -116,7 +117,7 @@ class MemTest : public MemObject
bool snoopRangeSent;
- class MemTestSenderState : public Packet::SenderState
+ class MemTestSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Constructor. */
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 128a71dbc..3ae69723d 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -40,6 +40,7 @@
#include "arch/faults.hh"
#include "arch/locked_mem.hh"
#include "config/full_system.hh"
+#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "mem/packet.hh"
@@ -245,7 +246,7 @@ class LSQUnit {
Port *dcachePort;
/** Derived class to hold any sender state the LSQ needs. */
- class LSQSenderState : public Packet::SenderState
+ class LSQSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Default constructor. */
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 7fc8b6307..2525da76e 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -39,6 +39,7 @@
#include "arch/faults.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
+#include "base/fast_alloc.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "mem/packet.hh"
@@ -301,7 +302,7 @@ class OzoneLWLSQ {
};
/** Derived class to hold any sender state the LSQ needs. */
- class LSQSenderState : public Packet::SenderState
+ class LSQSenderState : public Packet::SenderState, public FastAlloc
{
public:
/** Default constructor. */
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 876166adb..44aa01798 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -32,6 +32,7 @@
#ifndef __DEV_IO_DEVICE_HH__
#define __DEV_IO_DEVICE_HH__
+#include "base/fast_alloc.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"
@@ -73,7 +74,7 @@ class PioPort : public SimpleTimingPort
class DmaPort : public Port
{
protected:
- struct DmaReqState : public Packet::SenderState
+ struct DmaReqState : public Packet::SenderState, public FastAlloc
{
/** Event to call on the device when this transaction (all packets)
* complete. */
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index 1331a45f9..a9dd67a2b 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -42,6 +42,7 @@
#include <inttypes.h>
#include <queue>
+#include "base/fast_alloc.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
@@ -73,7 +74,7 @@ class Bridge : public MemObject
/** Pass ranges from one side of the bridge to the other? */
std::vector<Range<Addr> > filterRanges;
- class PacketBuffer : public Packet::SenderState {
+ class PacketBuffer : public Packet::SenderState, public FastAlloc {
public:
Tick ready;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 2f4567e0d..47d20f915 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -38,6 +38,7 @@
*/
#include "sim/host.hh"
+#include "base/fast_alloc.hh"
#include "base/misc.hh"
#include "base/range_ops.hh"
@@ -346,7 +347,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, int &lat)
}
-class ForwardResponseRecord : public Packet::SenderState
+class ForwardResponseRecord : public Packet::SenderState, public FastAlloc
{
Packet::SenderState *prevSenderState;
int prevSrc;
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 05442b369..7aad9de98 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -295,7 +295,7 @@ class Packet : public FastAlloc, public Printable
* needed to process it. A specific subclass would be derived
* from this to carry state specific to a particular sending
* device. */
- class SenderState : public FastAlloc {
+ class SenderState {
public:
virtual ~SenderState() {}
};
@@ -304,7 +304,7 @@ class Packet : public FastAlloc, public Printable
* Object used to maintain state of a PrintReq. The senderState
* field of a PrintReq should always be of this type.
*/
- class PrintReqState : public SenderState {
+ class PrintReqState : public SenderState, public FastAlloc {
/** An entry in the label stack. */
class LabelStackEntry {
public: