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-rw-r--r--README23
-rw-r--r--RELEASE_NOTES4
-rw-r--r--src/Doxyfile4
-rw-r--r--src/arch/SConscript1
-rw-r--r--src/arch/alpha/ev5.cc3
-rw-r--r--src/arch/alpha/faults.hh2
-rw-r--r--src/arch/alpha/isa_traits.hh6
-rw-r--r--src/arch/alpha/pagetable.hh112
-rw-r--r--src/arch/alpha/tlb.cc2
-rw-r--r--src/arch/alpha/tlb.hh4
-rw-r--r--src/arch/alpha/vtophys.hh18
-rw-r--r--src/arch/sparc/ua2005.cc10
-rw-r--r--src/base/chunk_generator.hh2
-rw-r--r--src/base/loader/symtab.hh12
-rw-r--r--src/cpu/simple/base.cc1
-rw-r--r--src/cpu/static_inst.hh1
-rw-r--r--src/dev/io_device.hh2
-rw-r--r--src/dev/isa_fake.hh4
-rw-r--r--src/dev/platform.cc1
-rw-r--r--src/dev/tsunami.hh3
-rw-r--r--src/dev/tsunami_io.hh8
-rw-r--r--src/doxygen/footer.html (renamed from docs/footer.html)0
-rw-r--r--src/doxygen/stl.hh (renamed from docs/stl.hh)0
-rw-r--r--src/mem/bridge.cc3
-rw-r--r--src/mem/bridge.hh5
-rw-r--r--src/mem/bus.cc3
-rw-r--r--src/mem/bus.hh5
-rw-r--r--src/mem/cache/base_cache.hh6
-rw-r--r--src/mem/cache/cache.hh20
-rw-r--r--src/mem/cache/coherence/coherence_protocol.hh4
-rw-r--r--src/mem/cache/coherence/simple_coherence.hh4
-rw-r--r--src/mem/cache/coherence/uni_coherence.hh4
-rw-r--r--src/mem/cache/miss/blocking_buffer.hh34
-rw-r--r--src/mem/cache/miss/miss_queue.hh42
-rw-r--r--src/mem/cache/miss/mshr.hh22
-rw-r--r--src/mem/cache/miss/mshr_queue.hh34
-rw-r--r--src/mem/cache/tags/fa_lru.hh6
-rw-r--r--src/mem/cache/tags/iic.hh10
-rw-r--r--src/mem/cache/tags/lru.hh6
-rw-r--r--src/mem/cache/tags/split.hh14
-rw-r--r--src/mem/cache/tags/split_blk.hh2
-rw-r--r--src/mem/cache/tags/split_lifo.hh6
-rw-r--r--src/mem/cache/tags/split_lru.hh6
-rw-r--r--src/mem/mem_object.hh2
-rw-r--r--src/mem/page_table.hh2
-rw-r--r--src/mem/port.cc3
-rw-r--r--src/mem/port.hh2
-rw-r--r--src/mem/request.hh3
-rw-r--r--src/mem/vport.cc3
-rw-r--r--src/mem/vport.hh2
50 files changed, 297 insertions, 179 deletions
diff --git a/README b/README
index 7bcbe9523..5f3ea3653 100644
--- a/README
+++ b/README
@@ -1,11 +1,11 @@
This is release 2.0 of the M5 simulator.
For information about building the simulator and getting started please refer
-to: http://m5.eecs.umich.edu/
+to: http://www.m5sim.org/
Specific Pages of Interest are:
-http://m5.eecs.umich.edu/wiki/index.php/Compiling_M5
-http://m5.eecs.umich.edu/wiki/index.php/Running_M5
+http://www.m5sim.org/wiki/index.php/Compiling_M5
+http://www.m5sim.org/wiki/index.php/Running_M5
If you have questions, please send mail to m5sim-users@lists.sourceforge.net.
@@ -15,30 +15,17 @@ WHAT'S INCLUDED (AND NOT)
The basic source release includes these subdirectories:
- m5:
- src: source code of the m5 simulator
- - test: regression tests
+ - tests: regression tests
- ext: less-common external packages needed to build m5
- system/alpha: source for Alpha console and PALcode
To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images. These files
are collected in a separate archive, m5_system_2.0.tar.bz2. This file
-is included on the CD release, or you can download it separately from
-Sourceforge.
+can he downloaded separately from Sourceforge.
M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-dev@eecs.umich.edu.
-
-The CD release includes a few extra goodies, such as a tar file
-containing doxygen-generated HTML documentation (html-docs.tar.gz), a
-set of Linux source patches (linux_m5-2.6.8.1.diff), and the scons
-program needed to build M5. If you do not have the CD, the same HTML
-documentation is available online at http://m5.eecs.umich.edu/docs,
-the Linux source patches are available at
-http://m5.eecs.umich.edu/dist/linux_m5-2.6.8.1.diff, the scons
-program is available from http://www.scons.org, and swig is available from
-http://www.swig.org.
-
-
diff --git a/RELEASE_NOTES b/RELEASE_NOTES
index 6eb9b1844..6184f244c 100644
--- a/RELEASE_NOTES
+++ b/RELEASE_NOTES
@@ -1,8 +1,8 @@
-XXX. X, 2006: m5_2.0
+Aug. 14, 2006: m5_2.0_beta
--------------------
Major update to M5 including:
- New CPU model
-- Sew memory system
+- New memory system
- More extensive python integration
- Preliminary syscall emulation support for MIPS and SPARC
diff --git a/src/Doxyfile b/src/Doxyfile
index 38116f6b0..ed4245dd2 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -30,7 +30,7 @@ PROJECT_NUMBER =
# If a relative path is entered, it will be relative to the location
# where doxygen was started. If left blank the current directory will be used.
-OUTPUT_DIRECTORY = docs/doxygen
+OUTPUT_DIRECTORY = doxygen
# The OUTPUT_LANGUAGE tag is used to specify the language in which all
# documentation generated by doxygen is written. Doxygen will use this
@@ -570,7 +570,7 @@ HTML_HEADER =
# each generated HTML page. If it is left blank doxygen will generate a
# standard footer.
-HTML_FOOTER = docs/footer.html
+HTML_FOOTER = doxygen/footer.html
# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
# style sheet that is used by each HTML page. It can be used to
diff --git a/src/arch/SConscript b/src/arch/SConscript
index d77060d62..59cea6211 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -47,6 +47,7 @@ sources = []
# List of headers to generate
isa_switch_hdrs = Split('''
+ arguments.hh
faults.hh
isa_traits.hh
process.hh
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ae3b668ea..796ed07de 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -29,9 +29,10 @@
* Nathan Binkert
*/
-#include "arch/alpha/tlb.hh"
+#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/osfpal.hh"
+#include "arch/alpha/tlb.hh"
#include "base/kgdb.h"
#include "base/remote_gdb.hh"
#include "base/stats/events.hh"
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 11a568174..3ef4d5521 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -32,7 +32,7 @@
#ifndef __ALPHA_FAULTS_HH__
#define __ALPHA_FAULTS_HH__
-#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/pagetable.hh"
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index ae4397c4c..72e38ae3e 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -35,17 +35,11 @@
namespace LittleEndianGuest {}
#include "arch/alpha/types.hh"
-#include "arch/alpha/isa_traits.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
class StaticInstPtr;
-#if FULL_SYSTEM
-#include "arch/alpha/isa_fullsys_traits.hh"
-#endif
-
-
namespace AlphaISA
{
diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh
new file mode 100644
index 000000000..3108c0a3e
--- /dev/null
+++ b/src/arch/alpha/pagetable.hh
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ */
+
+#ifndef __ARCH_ALPHA_PAGETABLE_H__
+#define __ARCH_ALPHA_PAGETABLE_H__
+
+#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/utility.hh"
+#include "config/full_system.hh"
+
+namespace AlphaISA {
+
+#if FULL_SYSTEM
+ struct VAddr
+ {
+ static const int ImplBits = 43;
+ static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
+ static const Addr UnImplMask = ~ImplMask;
+
+ VAddr(Addr a) : addr(a) {}
+ Addr addr;
+ operator Addr() const { return addr; }
+ const VAddr &operator=(Addr a) { addr = a; return *this; }
+
+ Addr vpn() const { return (addr & ImplMask) >> PageShift; }
+ Addr page() const { return addr & PageMask; }
+ Addr offset() const { return addr & PageOffset; }
+
+ Addr level3() const
+ { return AlphaISA::PteAddr(addr >> PageShift); }
+ Addr level2() const
+ { return AlphaISA::PteAddr(addr >> NPtePageShift + PageShift); }
+ Addr level1() const
+ { return AlphaISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ };
+
+ struct PageTableEntry
+ {
+ PageTableEntry(uint64_t e) : entry(e) {}
+ uint64_t entry;
+ operator uint64_t() const { return entry; }
+ const PageTableEntry &operator=(uint64_t e) { entry = e; return *this; }
+ const PageTableEntry &operator=(const PageTableEntry &e)
+ { entry = e.entry; return *this; }
+
+ Addr _pfn() const { return (entry >> 32) & 0xffffffff; }
+ Addr _sw() const { return (entry >> 16) & 0xffff; }
+ int _rsv0() const { return (entry >> 14) & 0x3; }
+ bool _uwe() const { return (entry >> 13) & 0x1; }
+ bool _kwe() const { return (entry >> 12) & 0x1; }
+ int _rsv1() const { return (entry >> 10) & 0x3; }
+ bool _ure() const { return (entry >> 9) & 0x1; }
+ bool _kre() const { return (entry >> 8) & 0x1; }
+ bool _nomb() const { return (entry >> 7) & 0x1; }
+ int _gh() const { return (entry >> 5) & 0x3; }
+ bool _asm() const { return (entry >> 4) & 0x1; }
+ bool _foe() const { return (entry >> 3) & 0x1; }
+ bool _fow() const { return (entry >> 2) & 0x1; }
+ bool _for() const { return (entry >> 1) & 0x1; }
+ bool valid() const { return (entry >> 0) & 0x1; }
+
+ Addr paddr() const { return _pfn() << PageShift; }
+ };
+
+ // ITB/DTB page table entry
+ struct PTE
+ {
+ Addr tag; // virtual page number tag
+ Addr ppn; // physical page number
+ uint8_t xre; // read permissions - VMEM_PERM_* mask
+ uint8_t xwe; // write permissions - VMEM_PERM_* mask
+ uint8_t asn; // address space number
+ bool asma; // address space match
+ bool fonr; // fault on read
+ bool fonw; // fault on write
+ bool valid; // valid page table entry
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string &section);
+ };
+#endif
+};
+#endif // __ARCH_ALPHA_PAGETABLE_H__
+
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index c6684274b..bab44c434 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -33,7 +33,9 @@
#include <string>
#include <vector>
+#include "arch/alpha/pagetable.hh"
#include "arch/alpha/tlb.hh"
+#include "arch/alpha/faults.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 07d01fa5c..955460649 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -36,9 +36,11 @@
#include "arch/alpha/ev5.hh"
#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/faults.hh"
+#include "arch/alpha/utility.hh"
+#include "arch/alpha/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
+#include "sim/faults.hh"
#include "sim/sim_object.hh"
class ThreadContext;
diff --git a/src/arch/alpha/vtophys.hh b/src/arch/alpha/vtophys.hh
index 472c694ff..32b999c37 100644
--- a/src/arch/alpha/vtophys.hh
+++ b/src/arch/alpha/vtophys.hh
@@ -33,22 +33,24 @@
#define __ARCH_ALPHA_VTOPHYS_H__
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/pagetable.hh"
+#include "arch/alpha/utility.hh"
class ThreadContext;
class FunctionalPort;
namespace AlphaISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
+ PageTableEntry
+ kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
-Addr vtophys(Addr vaddr);
-Addr vtophys(ThreadContext *tc, Addr vaddr);
+ Addr vtophys(Addr vaddr);
+ Addr vtophys(ThreadContext *tc, Addr vaddr);
-void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
-void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
-void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
+ void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+ void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+ void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+ void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
};
#endif // __ARCH_ALPHA_VTOPHYS_H__
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b89d48663..6493ddfd5 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -37,7 +37,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
int64_t time;
SparcSystem *sys;
switch (miscReg) {
- /** Full system only ASRs */
+ /* Full system only ASRs */
case MISCREG_SOFTINT:
if (isNonPriv())
return new PrivilegedOpcode;
@@ -94,7 +94,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
sTickCompare.schedule(time * Clock::Int::ns);
return NoFault;
- /** Fullsystem only Priv registers. */
+ /* Fullsystem only Priv registers. */
case MISCREG_PIL:
if (FULL_SYSTEM) {
setReg(miscReg, val);
@@ -104,7 +104,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
} else
panic("PIL not implemented for syscall emulation\n");
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
setReg(miscReg, val);
@@ -147,7 +147,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
{
switch (miscReg) {
- /** Privileged registers. */
+ /* Privileged registers. */
case MISCREG_SOFTINT:
if (isNonPriv()) {
fault = new PrivilegedOpcode;
@@ -177,7 +177,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
return readReg(miscReg);
- /** Hyper privileged registers */
+ /* Hyper privileged registers */
case MISCREG_HPSTATE:
case MISCREG_HINTP:
return readReg(miscReg);
diff --git a/src/base/chunk_generator.hh b/src/base/chunk_generator.hh
index e9d5355ca..e8238464b 100644
--- a/src/base/chunk_generator.hh
+++ b/src/base/chunk_generator.hh
@@ -72,7 +72,7 @@ class ChunkGenerator
public:
/**
* Constructor.
- * @param startAddr The starting address of the region.
+ * @param _startAddr The starting address of the region.
* @param totalSize The total size of the region.
* @param _chunkSize The size/alignment of chunks into which
* the region should be decomposed.
diff --git a/src/base/loader/symtab.hh b/src/base/loader/symtab.hh
index 55ff0c86f..184c0a996 100644
--- a/src/base/loader/symtab.hh
+++ b/src/base/loader/symtab.hh
@@ -104,11 +104,11 @@ class SymbolTable
/// Find the nearest symbol equal to or less than the supplied
/// address (e.g., the label for the enclosing function).
- /// @param address The address to look up.
- /// @param symbol Return reference for symbol string.
- /// @param sym_address Return reference for symbol address.
- /// @param next_sym_address Address of following symbol (for
- /// determining valid range of symbol).
+ /// @param addr The address to look up.
+ /// @param symbol Return reference for symbol string.
+ /// @param symaddr Return reference for symbol address.
+ /// @param nextaddr Address of following symbol (for
+ /// determining valid range of symbol).
/// @retval True if a symbol was found.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr,
@@ -126,7 +126,7 @@ class SymbolTable
}
/// Overload for findNearestSymbol() for callers who don't care
- /// about next_sym_address.
+ /// about nextaddr.
bool
findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr) const
{
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 622455745..801c96c88 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -29,6 +29,7 @@
*/
#include "arch/utility.hh"
+#include "arch/faults.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 9d76c1225..578d14191 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -35,6 +35,7 @@
#include <string>
#include "arch/isa_traits.hh"
+#include "sim/faults.hh"
#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 22a32e73a..710b22b2c 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -259,7 +259,7 @@ class BasicPioDevice : public PioDevice
{}
/** return the address ranges that this device responds to.
- * @params range_list range list to populate with ranges
+ * @param range_list range list to populate with ranges
*/
void addressRanges(AddrRangeList &range_list);
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index a7a469e17..5166882f8 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -65,14 +65,14 @@ class IsaFake : public BasicPioDevice
/**
* This read always returns -1.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data Where to put the data.
*/
virtual Tick read(Packet *pkt);
/**
* All writes are simply ignored.
- * @param req The memory request.
+ * @param pkt The memory request.
* @param data the data to not write.
*/
virtual Tick write(Packet *pkt);
diff --git a/src/dev/platform.cc b/src/dev/platform.cc
index 8546b7805..07288249c 100644
--- a/src/dev/platform.cc
+++ b/src/dev/platform.cc
@@ -29,6 +29,7 @@
* Nathan Binkert
*/
+#include "base/misc.hh"
#include "dev/platform.hh"
#include "sim/builder.hh"
#include "sim/sim_exit.hh"
diff --git a/src/dev/tsunami.hh b/src/dev/tsunami.hh
index 8bb66e914..6fbfac851 100644
--- a/src/dev/tsunami.hh
+++ b/src/dev/tsunami.hh
@@ -83,7 +83,8 @@ class Tsunami : public Platform
/**
* Constructor for the Tsunami Class.
* @param name name of the object
- * @param intrctrl pointer to the interrupt controller
+ * @param s system the object belongs to
+ * @param intctrl pointer to the interrupt controller
*/
Tsunami(const std::string &name, System *s, IntrControl *intctrl);
diff --git a/src/dev/tsunami_io.hh b/src/dev/tsunami_io.hh
index ee25bbdfd..9084a1be8 100644
--- a/src/dev/tsunami_io.hh
+++ b/src/dev/tsunami_io.hh
@@ -126,12 +126,14 @@ class TsunamiIO : public BasicPioDevice
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
@@ -221,12 +223,14 @@ class TsunamiIO : public BasicPioDevice
/**
* Serialize this object to the given output stream.
- * @param os The stream to serialize to.
+ * @param base The base name of the counter object.
+ * @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
@@ -254,12 +258,14 @@ class TsunamiIO : public BasicPioDevice
/**
* Serialize this object to the given output stream.
+ * @param base The base name of the counter object.
* @param os The stream to serialize to.
*/
void serialize(const std::string &base, std::ostream &os);
/**
* Reconstruct the state of this object from a checkpoint.
+ * @param base The base name of the counter object.
* @param cp The checkpoint use.
* @param section The section name of this object
*/
diff --git a/docs/footer.html b/src/doxygen/footer.html
index 6ef5293de..6ef5293de 100644
--- a/docs/footer.html
+++ b/src/doxygen/footer.html
diff --git a/docs/stl.hh b/src/doxygen/stl.hh
index fd9f68140..fd9f68140 100644
--- a/docs/stl.hh
+++ b/src/doxygen/stl.hh
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 29ea2e12f..9c14e7ee2 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -31,7 +31,8 @@
*/
/**
- * @file Definition of a simple bus bridge without buffering.
+ * @file
+ * Definition of a simple bus bridge without buffering.
*/
#include <algorithm>
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index b3525d3e0..2ab9799c7 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -30,7 +30,8 @@
*/
/**
- * @file Decleration of a simple bus bridge object with no buffering
+ * @file
+ * Declaration of a simple bus bridge object with no buffering
*/
#ifndef __MEM_BRIDGE_HH__
@@ -49,7 +50,7 @@
class Bridge : public MemObject
{
protected:
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BridgePort : public Port
{
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 31271106b..b945f93b3 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -29,7 +29,8 @@
*/
/**
- * @file Definition of a bus object.
+ * @file
+ * Definition of a bus object.
*/
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 3a2896886..cd25fab2c 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -30,7 +30,8 @@
*/
/**
- * @file Decleration of a bus object.
+ * @file
+ * Declaration of a bus object.
*/
#ifndef __MEM_BUS_HH__
@@ -97,7 +98,7 @@ class Bus : public MemObject
void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
- /** Decleration of the buses port type, one will be instantiated for each
+ /** Declaration of the buses port type, one will be instantiated for each
of the interfaces connecting to the bus. */
class BusPort : public Port
{
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 0d1bfdfdb..7f0cb56f2 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -488,7 +488,7 @@ class BaseCache : public MemObject
/**
* Send a response to the slave interface.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
@@ -501,7 +501,7 @@ class BaseCache : public MemObject
/**
* Send a reponse to the slave interface and calculate miss latency.
- * @param req The request to respond to.
+ * @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
@@ -517,7 +517,7 @@ class BaseCache : public MemObject
/**
* Suppliess the data if cache to cache transfers are enabled.
- * @param req The bus transaction to fulfill.
+ * @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt)
{
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index ec5b800a8..a26d91709 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -159,7 +159,7 @@ class Cache : public BaseCache
/**
* Performs the access specified by the request.
- * @param req The request to perform.
+ * @param pkt The request to perform.
* @return The result of the access.
*/
bool access(Packet * &pkt);
@@ -172,26 +172,26 @@ class Cache : public BaseCache
/**
* Was the request was sent successfully?
- * @param req The request.
+ * @param pkt The request.
* @param success True if the request was sent successfully.
*/
virtual void sendResult(Packet * &pkt, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
*/
void handleResponse(Packet * &pkt);
/**
* Start handling a copy transaction.
- * @param req The copy request to perform.
+ * @param pkt The copy request to perform.
*/
void startCopy(Packet * &pkt);
/**
* Handle a delayed copy transaction.
- * @param req The delayed copy request to continue.
+ * @param pkt The delayed copy request to continue.
* @param addr The address being responded to.
* @param blk The block of the current response.
* @param mshr The mshr being handled.
@@ -206,7 +206,7 @@ class Cache : public BaseCache
/**
* Snoops bus transactions to maintain coherence.
- * @param req The current bus transaction.
+ * @param pkt The current bus transaction.
*/
void snoop(Packet * &pkt);
@@ -221,9 +221,9 @@ class Cache : public BaseCache
void invalidateBlk(Addr addr, int asid);
/**
- * Aquash all requests associated with specified thread.
+ * Squash all requests associated with specified thread.
* intended for use by I-cache.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum)
{
@@ -246,7 +246,7 @@ class Cache : public BaseCache
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
* state of the update flag.
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
@@ -257,7 +257,7 @@ class Cache : public BaseCache
* Snoop for the provided request in the cache and return the estimated
* time of completion.
* @todo Can a snoop probe not change state?
- * @param req The memory request to satisfy
+ * @param pkt The memory request to satisfy
* @param update If true, update the hierarchy, otherwise just perform the
* request.
* @return The estimated completion time.
diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh
index 21351ace4..b5d7d80aa 100644
--- a/src/mem/cache/coherence/coherence_protocol.hh
+++ b/src/mem/cache/coherence/coherence_protocol.hh
@@ -85,7 +85,7 @@ class CoherenceProtocol : public SimObject
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param oldState The current block state.
* @return The new state.
*/
@@ -95,7 +95,7 @@ class CoherenceProtocol : public SimObject
/**
* Handle snooped bus requests.
* @param cache The cache that snooped the request.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index ca9d18beb..71d8f36f4 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -96,7 +96,7 @@ class SimpleCoherence
/**
* Return the proper state given the current state and the bus response.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
@@ -107,7 +107,7 @@ class SimpleCoherence
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state Return the new state for the block.
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 764bf6276..27b6c7fb5 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -88,7 +88,7 @@ class UniCoherence
/**
* Just return readable and writeable.
- * @param req The bus response.
+ * @param pkt The bus response.
* @param current The current block state.
* @return The new state.
*/
@@ -116,7 +116,7 @@ class UniCoherence
/**
* Handle snooped bus requests.
- * @param req The snooped bus request.
+ * @param pkt The snooped bus request.
* @param blk The cache block corresponding to the request, if any.
* @param mshr The MSHR corresponding to the request, if any.
* @param new_state The new coherence state of the block.
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 39a06a377..a6261f62c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -107,7 +107,7 @@ public:
/**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
@@ -128,43 +128,43 @@ public:
}
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Frees the resources of the request and unblock the cache.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Frees the resources of the pktuest and unblock the cache.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
@@ -220,14 +220,14 @@ public:
int size, uint8_t *data, bool compressed);
/**
- * Perform a writeback request.
- * @param req The writeback request.
+ * Perform a writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending()
{
@@ -237,7 +237,7 @@ public:
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index b88b7038c..c558df956 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -77,7 +77,7 @@ class MissQueue
/** The block size of the parent cache. */
int blkSize;
- /** Increasing order number assigned to each incoming request. */
+ /** Increasing order number assigned to each incoming pktuest. */
uint64_t order;
bool prefetchMiss;
@@ -164,7 +164,7 @@ class MissQueue
/**
* Allocate a new MSHR to handle the provided miss.
- * @param req The miss to buffer.
+ * @param pkt The miss to buffer.
* @param size The number of bytes to fetch.
* @param time The time the miss occurs.
* @return A pointer to the new MSHR.
@@ -173,7 +173,7 @@ class MissQueue
/**
* Allocate a new WriteBuffer to handle the provided write.
- * @param req The write to handle.
+ * @param pkt The write to handle.
* @param size The number of bytes to write.
* @param time The time the write occurs.
* @return A pointer to the new write buffer.
@@ -212,9 +212,9 @@ class MissQueue
void setPrefetcher(BasePrefetcher *_prefetcher);
/**
- * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * Handle a cache miss properly. Either allocate an MSHR for the pktuest,
* or forward it through the write buffer.
- * @param req The request that missed in the cache.
+ * @param pkt The request that missed in the cache.
* @param blk_size The block size of the cache.
* @param time The time the miss is detected.
*/
@@ -232,43 +232,43 @@ class MissQueue
Packet * &target);
/**
- * Selects a outstanding request to service.
- * @return The request to service, NULL if none found.
+ * Selects a outstanding pktuest to service.
+ * @return The pktuest to service, NULL if none found.
*/
Packet * getPacket();
/**
* Set the command to the given bus command.
- * @param req The request to update.
+ * @param pkt The request to update.
* @param cmd The bus command to use.
*/
void setBusCmd(Packet * &pkt, Packet::Command cmd);
/**
* Restore the original command in case of a bus transmission error.
- * @param req The request to reset.
+ * @param pkt The request to reset.
*/
void restoreOrigCmd(Packet * &pkt);
/**
- * Marks a request as in service (sent on the bus). This can have side
+ * Marks a pktuest as in service (sent on the bus). This can have side
* effect since storage for no response commands is deallocated once they
* are successfully sent.
- * @param req The request that was sent on the bus.
+ * @param pkt The request that was sent on the bus.
*/
void markInService(Packet * &pkt);
/**
- * Collect statistics and free resources of a satisfied request.
- * @param req The request that has been satisfied.
- * @param time The time when the request is satisfied.
+ * Collect statistics and free resources of a satisfied pktuest.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the pktuest is satisfied.
*/
void handleResponse(Packet * &pkt, Tick time);
/**
- * Removes all outstanding requests for a given thread number. If a request
+ * Removes all outstanding pktuests for a given thread number. If a request
* has been sent to the bus, this function removes all of its targets.
- * @param req->getThreadNum()ber The thread number of the requests to squash.
+ * @param threadNum The thread number of the requests to squash.
*/
void squash(int threadNum);
@@ -313,21 +313,21 @@ class MissQueue
int size, uint8_t *data, bool compressed);
/**
- * Perform the given writeback request.
- * @param req The writeback request.
+ * Perform the given writeback pktuest.
+ * @param pkt The writeback request.
*/
void doWriteback(Packet * &pkt);
/**
- * Returns true if there are outstanding requests.
- * @return True if there are outstanding requests.
+ * Returns true if there are outstanding pktuests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending();
/**
* Add a target to the given MSHR. This assumes it is in the miss queue.
* @param mshr The mshr to add a target to.
- * @param req The target to add.
+ * @param pkt The target to add.
*/
void addTarget(MSHR *mshr, Packet * &pkt)
{
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 167aa26cd..ad2865973 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -44,7 +44,7 @@ class MSHR;
/**
* Miss Status and handling Register. This class keeps all the information
- * needed to handle a cache miss including a list of target requests.
+ * needed to handle a cache miss including a list of target pktuests.
*/
class MSHR {
public:
@@ -63,15 +63,15 @@ class MSHR {
Addr addr;
/** Adress space id of the miss. */
short asid;
- /** True if the request has been sent to the bus. */
+ /** True if the pktuest has been sent to the bus. */
bool inService;
/** Thread number of the miss. */
int threadNum;
- /** The request that is forwarded to the next level of the hierarchy. */
+ /** The pktuest that is forwarded to the next level of the hierarchy. */
Packet * pkt;
/** The number of currently allocated targets. */
short ntargets;
- /** The original requesting command. */
+ /** The original pktuesting command. */
Packet::Command originalCmd;
/** Order number of assigned by the miss queue. */
uint64_t order;
@@ -88,24 +88,24 @@ class MSHR {
Iterator allocIter;
private:
- /** List of all requests that match the address */
+ /** List of all pktuests that match the address */
TargetList targets;
public:
/**
* Allocate a miss to this MSHR.
- * @param cmd The requesting command.
+ * @param cmd The pktuesting command.
* @param addr The address of the miss.
* @param asid The address space id of the miss.
- * @param size The number of bytes to request.
- * @param req The original miss.
+ * @param size The number of bytes to pktuest.
+ * @param pkt The original miss.
*/
void allocate(Packet::Command cmd, Addr addr, int asid, int size,
Packet * &pkt);
/**
- * Allocate this MSHR as a buffer for the given request.
- * @param target The memory request to buffer.
+ * Allocate this MSHR as a buffer for the given pktuest.
+ * @param target The memory pktuest to buffer.
*/
void allocateAsBuffer(Packet * &target);
@@ -115,7 +115,7 @@ public:
void deallocate();
/**
- * Add a request to the list of targets.
+ * Add a pktuest to the list of targets.
* @param target The target.
*/
void allocateTarget(Packet * &target);
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index a67f1b9a6..02b6a026d 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -39,7 +39,7 @@
#include "mem/cache/miss/mshr.hh"
/**
- * A Class for maintaining a list of pending and allocated memory requests.
+ * A Class for maintaining a list of pending and allocated memory pktuests.
*/
class MSHRQueue {
private:
@@ -55,7 +55,7 @@ class MSHRQueue {
// Parameters
/**
* The total number of MSHRs in this queue. This number is set as the
- * number of MSHRs requested plus (numReserve - 1). This allows for
+ * number of MSHRs pktuested plus (numReserve - 1). This allows for
* the same number of effective MSHRs while still maintaining the reserve.
*/
const int numMSHRs;
@@ -103,16 +103,16 @@ class MSHRQueue {
bool findMatches(Addr addr, int asid, std::vector<MSHR*>& matches) const;
/**
- * Find any pending requests that overlap the given request.
- * @param req The request to find.
+ * Find any pending pktuests that overlap the given request.
+ * @param pkt The request to find.
* @return A pointer to the earliest matching MSHR.
*/
MSHR* findPending(Packet * &pkt) const;
/**
- * Allocates a new MSHR for the request and size. This places the request
+ * Allocates a new MSHR for the pktuest and size. This places the request
* as the first target in the MSHR.
- * @param req The request to handle.
+ * @param pkt The request to handle.
* @param size The number in bytes to fetch from memory.
* @return The a pointer to the MSHR allocated.
*
@@ -121,12 +121,12 @@ class MSHRQueue {
MSHR* allocate(Packet * &pkt, int size = 0);
/**
- * Allocate a read request for the given address, and places the given
+ * Allocate a read pktuest for the given address, and places the given
* target on the target list.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
- * @param target The first target for the request.
+ * @param size The number of bytes to pktuest.
+ * @param target The first target for the pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target);
@@ -135,7 +135,7 @@ class MSHRQueue {
* Allocate a target list for the given address.
* @param addr The address to fetch.
* @param asid The address space for the fetch.
- * @param size The number of bytes to request.
+ * @param size The number of bytes to pktuest.
* @return Pointer to the new MSHR.
*/
MSHR* allocateTargetList(Addr addr, int asid, int size);
@@ -151,7 +151,7 @@ class MSHRQueue {
* Allocates a target to the given MSHR. Used to keep track of the number
* of outstanding targets.
* @param mshr The MSHR to allocate the target to.
- * @param req The target request.
+ * @param pkt The target request.
*/
void allocateTarget(MSHR* mshr, Packet * &pkt)
{
@@ -181,22 +181,22 @@ class MSHRQueue {
void markInService(MSHR* mshr);
/**
- * Mark an in service mshr as pending, used to resend a request.
+ * Mark an in service mshr as pending, used to resend a pktuest.
* @param mshr The MSHR to resend.
* @param cmd The command to resend.
*/
void markPending(MSHR* mshr, Packet::Command cmd);
/**
- * Squash outstanding requests with the given thread number. If a request
+ * Squash outstanding pktuests with the given thread number. If a request
* is in service, just squashes the targets.
- * @param req->getThreadNum()ber The thread to squash.
+ * @param threadNum The thread to squash.
*/
void squash(int threadNum);
/**
* Returns true if the pending list is not empty.
- * @return True if there are outstanding requests.
+ * @return True if there are outstanding pktuests.
*/
bool havePending() const
{
@@ -213,8 +213,8 @@ class MSHRQueue {
}
/**
- * Returns the request at the head of the pendingList.
- * @return The next request to service.
+ * Returns the pktuest at the head of the pendingList.
+ * @return The next pktuest to service.
*/
Packet * getReq() const
{
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 566e36c27..444954917 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -193,7 +193,7 @@ public:
/**
* Find the block in the cache and update the replacement data. Returns
* the access latency and the in cache flags as a side effect
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The latency of the access.
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
@@ -210,7 +210,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -328,7 +328,7 @@ public:
* @param source The block aligned source address.
* @param dest The block aligned destination adddress.
* @param asid The address space ID.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
{
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 6628f7e7a..514d16bdd 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -454,7 +454,7 @@ class IIC : public BaseTags
/**
* Find the block and update the replacement data. This call also returns
* the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
@@ -470,7 +470,7 @@ class IIC : public BaseTags
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -502,14 +502,14 @@ class IIC : public BaseTags
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
/**
* If a block is currently marked copy on write, copy it before writing.
- * @param req The write request.
- * @param writebacks List for any generated writeback requests.
+ * @param pkt The write request.
+ * @param writebacks List for any generated writeback pktuests.
*/
void fixCopy(Packet * &pkt, PacketList &writebacks);
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 437244660..8f0f3ae27 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -170,7 +170,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The request whose block to find.
+ * @param pkt The request whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -196,7 +196,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -307,7 +307,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh
index 5e0340269..25180a02b 100644
--- a/src/mem/cache/tags/split.hh
+++ b/src/mem/cache/tags/split.hh
@@ -71,13 +71,13 @@ class Split : public BaseTags
Addr blkMask;
- /** Number of NIC requests that hit in the NIC partition */
+ /** Number of NIC pktuests that hit in the NIC partition */
Stats::Scalar<> NR_NP_hits;
- /** Number of NIC requests that hit in the CPU partition */
+ /** Number of NIC pktuests that hit in the CPU partition */
Stats::Scalar<> NR_CP_hits;
- /** Number of CPU requests that hit in the NIC partition */
+ /** Number of CPU pktuests that hit in the NIC partition */
Stats::Scalar<> CR_NP_hits;
- /** Number of CPU requests that hit in the CPU partition */
+ /** Number of CPU pktuests that hit in the CPU partition */
Stats::Scalar<> CR_CP_hits;
/** The number of nic replacements (i.e. misses) */
Stats::Scalar<> nic_repl;
@@ -203,7 +203,7 @@ class Split : public BaseTags
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The memory request whose block to find
+ * @param pkt The memory request whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -219,7 +219,7 @@ class Split : public BaseTags
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -315,7 +315,7 @@ class Split : public BaseTags
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split_blk.hh b/src/mem/cache/tags/split_blk.hh
index f38516180..64d903579 100644
--- a/src/mem/cache/tags/split_blk.hh
+++ b/src/mem/cache/tags/split_blk.hh
@@ -47,7 +47,7 @@ class SplitBlk : public CacheBlk {
bool isTouched;
/** Has this block been used after being brought in? (for LIFO partition) */
bool isUsed;
- /** is this blk a NIC block? (i.e. requested by the NIC) */
+ /** is this blk a NIC block? (i.e. pktuested by the NIC) */
bool isNIC;
/** timestamp of the arrival of this block into the cache */
Tick ts;
diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh
index dfcaa0b67..52956b192 100644
--- a/src/mem/cache/tags/split_lifo.hh
+++ b/src/mem/cache/tags/split_lifo.hh
@@ -203,7 +203,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find
+ * @param pkt The req whose block to find
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -219,7 +219,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -330,7 +330,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh
index 03886b1d8..6d370c5dd 100644
--- a/src/mem/cache/tags/split_lru.hh
+++ b/src/mem/cache/tags/split_lru.hh
@@ -186,7 +186,7 @@ public:
/**
* Finds the given address in the cache and update replacement data.
* Returns the access latency as a side effect.
- * @param req The req whose block to find.
+ * @param pkt The req whose block to find.
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
@@ -202,7 +202,7 @@ public:
/**
* Find a replacement block for the address provided.
- * @param req The request to a find a replacement candidate for.
+ * @param pkt The request to a find a replacement candidate for.
* @param writebacks List for any writebacks to be performed.
* @param compress_blocks List of blocks to compress, for adaptive comp.
* @return The block to place the replacement in.
@@ -313,7 +313,7 @@ public:
* @param source The block-aligned source address.
* @param dest The block-aligned destination address.
* @param asid The address space DI.
- * @param writebacks List for any generated writeback requests.
+ * @param writebacks List for any generated writeback pktuests.
*/
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
index c81ea03d8..d12eeffe0 100644
--- a/src/mem/mem_object.hh
+++ b/src/mem/mem_object.hh
@@ -30,7 +30,7 @@
/**
* @file
- * Base Memory Object decleration.
+ * Base Memory Object declaration.
*/
#ifndef __MEM_MEM_OBJECT_HH__
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 52c81671b..fce063280 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -49,7 +49,7 @@
class System;
/**
- * Page Table Decleration.
+ * Page Table Declaration.
*/
class PageTable
{
diff --git a/src/mem/port.cc b/src/mem/port.cc
index bec9d2274..17924b759 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -29,7 +29,8 @@
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 17b1f4a00..42e369205 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -30,7 +30,7 @@
/**
* @file
- * Port Object Decleration. Ports are used to interface memory objects to
+ * Port Object Declaration. Ports are used to interface memory objects to
* each other. They will always come in pairs, and we refer to the other
* port object as the peer. These are used to make the design more
* modular so that a specific interface between every type of objcet doesn't
diff --git a/src/mem/request.hh b/src/mem/request.hh
index f3647e55f..457310298 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -31,7 +31,8 @@
*/
/**
- * @file Decleration of a request, the overall memory request consisting of
+ * @file
+ * Declaration of a request, the overall memory request consisting of
the parts of the request that are persistent throughout the transaction.
*/
diff --git a/src/mem/vport.cc b/src/mem/vport.cc
index cd297bb8e..8030c5a15 100644
--- a/src/mem/vport.cc
+++ b/src/mem/vport.cc
@@ -29,7 +29,8 @@
*/
/**
- * @file Port object definitions.
+ * @file
+ * Port object definitions.
*/
#include "base/chunk_generator.hh"
diff --git a/src/mem/vport.hh b/src/mem/vport.hh
index 697c8e5f3..c83836258 100644
--- a/src/mem/vport.hh
+++ b/src/mem/vport.hh
@@ -30,7 +30,7 @@
/**
* @file
- * Virtual Port Object Decleration. These ports incorporate some translation
+ * Virtual Port Object Declaration. These ports incorporate some translation
* into their access methods. Thus you can use one to read and write data
* to/from virtual addresses.
*/